--
-- ff_d2
-- Matts DFF x2 aka Syncroniser
-- A little entity to make a simple D flip-flop (no reset)
--
--

library ieee;
use ieee.std_logic_1164.all;

entity ff_d2 is
   port(
      clk : in std_logic;
      d : in     std_logic;
      q1 : out    std_logic := '0';
      q2 : out    std_logic := '0'
   );

-- Declarations

end ff_d2 ;


architecture rtl of ff_d2 is

  signal q_int : std_logic := '0';

begin


  q_int <= d after 200 ps when rising_edge(clk);


  q1 <= q_int;
  q2 <= q_int after 200 ps when rising_edge(clk);

end rtl;