--
-- m_power
--
-- Matt's easy way to get hi, lo (one, zero) into a design.
--
--

library ieee;
use ieee.std_logic_1164.all;

ENTITY m_power IS
   PORT(
      hi : OUT    std_logic;
      lo : OUT    std_logic
   );

-- Declarations

END m_power ;


architecture rtl of m_power is
begin

  hi <= '1';
  lo <= '0';

end rtl;