* version 3 **************************************************************** * For all of these it will be good to * to have `udec_ld_config_reg' on screen, as this will indicate * exactly when the change takes place **************************************** * 1-3 ABCN DCLK Test - 3 parts * 1) Zero Register * 2) Enable ABCN DCLK * 3) Invert ABCN DCLK * * What to look for: * After 1st command: all ABCN clocks stop * After 2nd command: zoom of ABCN_DCLK starting * After 3rd command: zoom of ABCN_DLCK inverting * 1 ZERO V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 0.0 560ns 0.0 + 561ns 0.0 580ns 0.0 + 581ns 0.0 600ns 0.0 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 * 2 ABCN DCLK Enable * V_COM COM_DUP0 0 PWL + 900ns 0 + 901ns 2.5 920ns 2.5 + 921ns 2.5 940ns 2.5 + 941ns 2.5 960ns 2.5 + 961ns 0.0 980ns 0.0 + 981ns 0.0 1000ns 0.0 + 1001ns 0.0 1020ns 0.0 + 1021ns 0.0 1040ns 0.0 + 1041ns 0.0 1060ns 0.0 + 1061ns 0.0 1080ns 0.0 + 1081ns 2.5 1100ns 2.5 + 1101ns 0.0 1120ns 0.0 + 1121ns 2.5 1140ns 2.5 + 1141ns 0.0 1160ns 0.0 + 1161ns 0.0 1180ns 0.0 + 1181ns 0.0 1200ns 0.0 + 1201ns 0.0 1220ns 0.0 + 1221ns 0.0 1240ns 0.0 + 1241ns 2.5 1260ns 2.5 + 1261ns 0.0 1280ns 0.0 + 1281ns 0.0 1300ns 0.0 + 1301ns 0.0 1320ns 0.0 + 1321ns 0.0 1340ns 0.0 + 1341ns 0.0 1360ns 0.0 + 1361ns 0.0 1380ns 0.0 + 1381ns 0.0 1400ns 0.0 + 1401ns 0.0 1420ns 0.0 + 1421ns 0.0 1440ns 0.0 + 1441ns 0.0 1460ns 0.0 + 1461ns 0.0 * 3 ABCN DCLK Enable + Invert * V_COM COM_DUP0 0 PWL + 1600ns 0 + 1601ns 2.5 1620ns 2.5 + 1621ns 2.5 1640ns 2.5 + 1641ns 2.5 1660ns 2.5 + 1661ns 0.0 1680ns 0.0 + 1681ns 0.0 1700ns 0.0 + 1701ns 0.0 1720ns 0.0 + 1721ns 0.0 1740ns 0.0 + 1741ns 0.0 1760ns 0.0 + 1761ns 0.0 1780ns 0.0 + 1781ns 2.5 1800ns 2.5 + 1801ns 0.0 1820ns 0.0 + 1821ns 2.5 1840ns 2.5 + 1841ns 0.0 1860ns 0.0 + 1861ns 0.0 1880ns 0.0 + 1881ns 0.0 1900ns 0.0 + 1901ns 0.0 1920ns 0.0 + 1921ns 0.0 1940ns 0.0 + 1941ns 2.5 1960ns 2.5 + 1961ns 0.0 1980ns 0.0 + 1981ns 0.0 2000ns 0.0 + 2001ns 2.5 2020ns 2.5 + 2021ns 0.0 2040ns 0.0 + 2041ns 0.0 2060ns 0.0 + 2061ns 0.0 2080ns 0.0 + 2081ns 0.0 2100ns 0.0 + 2101ns 0.0 2120ns 0.0 + 2121ns 0.0 2140ns 0.0 + 2141ns 0.0 2160ns 0.0 + 2161ns 0.0 **************************************** * 4-6 ABCN BCO Test - 3 parts * 1) Zero Register * 2) Enable ABCN BCO * 3) Invert ABCN BCO * * What to look for: * After 2nd command: zoom of ABCN_BCO starting * After 3rd command: zoom of ABCN_BCO inverting * 4 ZERO V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 0.0 560ns 0.0 + 561ns 0.0 580ns 0.0 + 581ns 0.0 600ns 0.0 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 * 5 ABCN BCO Enable * V_COM COM_DUP0 0 PWL + 900ns 0 + 901ns 2.5 920ns 2.5 + 921ns 2.5 940ns 2.5 + 941ns 2.5 960ns 2.5 + 961ns 0.0 980ns 0.0 + 981ns 0.0 1000ns 0.0 + 1001ns 0.0 1020ns 0.0 + 1021ns 0.0 1040ns 0.0 + 1041ns 0.0 1060ns 0.0 + 1061ns 0.0 1080ns 0.0 + 1081ns 2.5 1100ns 2.5 + 1101ns 0.0 1120ns 0.0 + 1121ns 2.5 1140ns 2.5 + 1141ns 0.0 1160ns 0.0 + 1161ns 0.0 1180ns 0.0 + 1181ns 0.0 1200ns 0.0 + 1201ns 0.0 1220ns 0.0 + 1221ns 0.0 1240ns 0.0 + 1241ns 0.0 1260ns 0.0 + 1261ns 2.5 1280ns 2.5 + 1281ns 0.0 1300ns 0.0 + 1301ns 0.0 1320ns 0.0 + 1321ns 0.0 1340ns 0.0 + 1341ns 0.0 1360ns 0.0 + 1361ns 0.0 1380ns 0.0 + 1381ns 0.0 1400ns 0.0 + 1401ns 0.0 1420ns 0.0 + 1421ns 0.0 1440ns 0.0 + 1441ns 0.0 1460ns 0.0 + 1461ns 0.0 * 6 ABCN BCO Enable + Invert * V_COM COM_DUP0 0 PWL + 1600ns 0 + 1601ns 2.5 1620ns 2.5 + 1621ns 2.5 1640ns 2.5 + 1641ns 2.5 1660ns 2.5 + 1661ns 0.0 1680ns 0.0 + 1681ns 0.0 1700ns 0.0 + 1701ns 0.0 1720ns 0.0 + 1721ns 0.0 1740ns 0.0 + 1741ns 0.0 1760ns 0.0 + 1761ns 0.0 1780ns 0.0 + 1781ns 2.5 1800ns 2.5 + 1801ns 0.0 1820ns 0.0 + 1821ns 2.5 1840ns 2.5 + 1841ns 0.0 1860ns 0.0 + 1861ns 0.0 1880ns 0.0 + 1881ns 0.0 1900ns 0.0 + 1901ns 0.0 1920ns 0.0 + 1921ns 0.0 1940ns 0.0 + 1941ns 0.0 1960ns 0.0 + 1961ns 2.5 1980ns 2.5 + 1981ns 0.0 2000ns 0.0 + 2001ns 0.0 2020ns 0.0 + 2021ns 2.5 2040ns 2.5 + 2041ns 0.0 2060ns 0.0 + 2061ns 0.0 2080ns 0.0 + 2081ns 0.0 2100ns 0.0 + 2101ns 0.0 2120ns 0.0 + 2121ns 0.0 2140ns 0.0 + 2141ns 0.0 2160ns 0.0 + 2161ns 0.0 **************************************** * 7-8 ACLK Test - 2 parts + Needs L1s * 0.1) L1 * 1) ACLK Enable * 1.1) L1 * 2) Invert ACLK * 2.1) L1 * * After 1st L1 nothing will appear on ABCN_L1, so look for nothing! * After 2nd L1 - Zoom of phase wrt ABCN_BCO * After 3rd l1 - Zoom of phase wrt ABCN_BCO (should be 180 degree * different from 2ND L1) * Send L1 here - it should NOT be seen on ABCN_L1 * 7 ACLK Enable (no L1/COM/RESETB before) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 0.0 560ns 0.0 + 561ns 0.0 580ns 0.0 + 581ns 2.5 600ns 2.5 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 * Send L1 here - it should be in phase with BCO * 8 ACLK Enable + Invert (see L1 phase wrt BCO before/after) * V_COM COM_DUP0 0 PWL + 900ns 0 + 901ns 2.5 920ns 2.5 + 921ns 2.5 940ns 2.5 + 941ns 2.5 960ns 2.5 + 961ns 0.0 980ns 0.0 + 981ns 0.0 1000ns 0.0 + 1001ns 0.0 1020ns 0.0 + 1021ns 0.0 1040ns 0.0 + 1041ns 0.0 1060ns 0.0 + 1061ns 0.0 1080ns 0.0 + 1081ns 2.5 1100ns 2.5 + 1101ns 0.0 1120ns 0.0 + 1121ns 2.5 1140ns 2.5 + 1141ns 0.0 1160ns 0.0 + 1161ns 0.0 1180ns 0.0 + 1181ns 0.0 1200ns 0.0 + 1201ns 0.0 1220ns 0.0 + 1221ns 0.0 1240ns 0.0 + 1241ns 0.0 1260ns 0.0 + 1261ns 0.0 1280ns 0.0 + 1281ns 2.5 1300ns 2.5 + 1301ns 0.0 1320ns 0.0 + 1321ns 0.0 1340ns 0.0 + 1341ns 2.5 1360ns 2.5 + 1361ns 0.0 1380ns 0.0 + 1381ns 0.0 1400ns 0.0 + 1401ns 0.0 1420ns 0.0 + 1421ns 0.0 1440ns 0.0 + 1441ns 0.0 1460ns 0.0 + 1461ns 0.0 * Send L1 here - it should be in NOT phase with BCO **************************************** * 9-11 Mode 80 Tests (3 parts) * 1) Mode 80 Select * 2) Turn off ABCN DCLK * 3) Turn-on ABCN DCLK * * After 1st command: Zoom of ABCN_DCLK doubling * After 2nd command: Zoom of ABCN_DCLK stoping * After 3rd command: Zoom of ABCN_DLCK starting * 9 Mode 80 Sel + DCLK Enable V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 2.5 560ns 2.5 + 561ns 0.0 580ns 0.0 + 581ns 0.0 600ns 0.0 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 2.5 700ns 2.5 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 * 10 Mode 80 Sel (no DCLK) * V_COM COM_DUP0 0 PWL + 900ns 0 + 901ns 2.5 920ns 2.5 + 921ns 2.5 940ns 2.5 + 941ns 2.5 960ns 2.5 + 961ns 0.0 980ns 0.0 + 981ns 0.0 1000ns 0.0 + 1001ns 0.0 1020ns 0.0 + 1021ns 0.0 1040ns 0.0 + 1041ns 0.0 1060ns 0.0 + 1061ns 0.0 1080ns 0.0 + 1081ns 2.5 1100ns 2.5 + 1101ns 0.0 1120ns 0.0 + 1121ns 2.5 1140ns 2.5 + 1141ns 0.0 1160ns 0.0 + 1161ns 0.0 1180ns 0.0 + 1181ns 0.0 1200ns 0.0 + 1201ns 0.0 1220ns 0.0 + 1221ns 0.0 1240ns 0.0 + 1241ns 0.0 1260ns 0.0 + 1261ns 0.0 1280ns 0.0 + 1281ns 0.0 1300ns 0.0 + 1301ns 0.0 1320ns 0.0 + 1321ns 0.0 1340ns 0.0 + 1341ns 0.0 1360ns 0.0 + 1361ns 0.0 1380ns 0.0 + 1381ns 2.5 1400ns 2.5 + 1401ns 0.0 1420ns 0.0 + 1421ns 0.0 1440ns 0.0 + 1441ns 0.0 1460ns 0.0 + 1461ns 0.0 * 11 Mode 80 Sel + DCLK Enable * V_COM COM_DUP0 0 PWL + 1600ns 0 + 1601ns 2.5 1620ns 2.5 + 1621ns 2.5 1640ns 2.5 + 1641ns 2.5 1660ns 2.5 + 1661ns 0.0 1680ns 0.0 + 1681ns 0.0 1700ns 0.0 + 1701ns 0.0 1720ns 0.0 + 1721ns 0.0 1740ns 0.0 + 1741ns 0.0 1760ns 0.0 + 1761ns 0.0 1780ns 0.0 + 1781ns 2.5 1800ns 2.5 + 1801ns 0.0 1820ns 0.0 + 1821ns 2.5 1840ns 2.5 + 1841ns 0.0 1860ns 0.0 + 1861ns 0.0 1880ns 0.0 + 1881ns 0.0 1900ns 0.0 + 1901ns 0.0 1920ns 0.0 + 1921ns 0.0 1940ns 0.0 + 1941ns 2.5 1960ns 2.5 + 1961ns 0.0 1980ns 0.0 + 1981ns 0.0 2000ns 0.0 + 2001ns 0.0 2020ns 0.0 + 2021ns 0.0 2040ns 0.0 + 2041ns 0.0 2060ns 0.0 + 2061ns 0.0 2080ns 0.0 + 2081ns 2.5 2100ns 2.5 + 2101ns 0.0 2120ns 0.0 + 2121ns 0.0 2140ns 0.0 + 2141ns 0.0 2160ns 0.0 + 2161ns 0.0 ******************************* * The rest are single command tests ******************************* ************************************ * 12 Look for: * ABCN_BCO doubling frequency * 12 BCO2x Mode Test V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 2.5 480ns 2.5 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 0.0 560ns 0.0 + 561ns 2.5 580ns 2.5 + 581ns 0.0 600ns 0.0 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 *********************************** * The rest of the tests look at DATAOUT * It will probably be much easier if we put some patterns * on DATA0-3 (clk /1 /2 /4 /8 ??) Then we should at least * see some changes, although it will still be hard * screen graps should ideally show DATAOUT and DATA0-3 ************************************ * 13 Look for: * DATAOUT change in polarity * 13 Linkmode InvSel (Dataout change polarity) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 2.5 560ns 2.5 + 561ns 2.5 580ns 2.5 + 581ns 2.5 600ns 2.5 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 2.5 760ns 2.5 + 761ns 0.0 ************************************ * 14 Look for: * DATAOUT fixed at level on DATA0 * 14 Linkmode Select 0 (Dataout = Data0/2 only – no mux) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 2.5 560ns 2.5 + 561ns 2.5 580ns 2.5 + 581ns 2.5 600ns 2.5 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 2.5 740ns 2.5 + 741ns 0.0 760ns 0.0 + 761ns 0.0 ************************************ * 15 Look for: * DATAOUT fixed at level on DATA2 * 15 Linkmode Select 1 (Dataout = Data1/3 only – no mux) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 2.5 560ns 2.5 + 561ns 2.5 580ns 2.5 + 581ns 2.5 600ns 2.5 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 2.5 740ns 2.5 + 741ns 2.5 760ns 2.5 + 761ns 0.0 ************************************ * 16 NOT IMPORTANT (HARD to DETECT) * Look for: * DATAOUT cycling though all 4 inputs * 16 Quadmode Enable (Dataout selects Data0-3, hard to detect with static inputs) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 2.5 560ns 2.5 + 561ns 2.5 580ns 2.5 + 581ns 2.5 600ns 2.5 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 2.5 720ns 2.5 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 ************************************ * 17 NOT IMPORTANT (HARD to DETECT) * Look for: * DATAOUT should be a clock (like it usually is with the DATA lines * set to 0/1) * 17 Const Dataout Mode (col0=0, col1=1) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 2.5 500ns 2.5 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 2.5 560ns 2.5 + 561ns 2.5 580ns 2.5 + 581ns 2.5 600ns 2.5 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 ************************************ * 18 NOT IMPORTANT (HARD to DETECT) * Look for: * DATAOUT should now show the DATA0/DATA3 input, not DATA0/2 * 18 Col1 Top Data Sel (Data 3) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 2.5 520ns 2.5 + 521ns 0.0 540ns 0.0 + 541ns 2.5 560ns 2.5 + 561ns 2.5 580ns 2.5 + 581ns 2.5 600ns 2.5 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 ************************************ * 19 NOT IMPORTANT (HARD to DETECT) * Look for: * DATAOUT should now show the DATA1/DATA2 input, not DATA0/2 * 19 Col0 Top Data Sel (Data 1) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 2.5 400ns 2.5 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 2.5 540ns 2.5 + 541ns 2.5 560ns 2.5 + 561ns 2.5 580ns 2.5 + 581ns 2.5 600ns 2.5 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 0.0 660ns 0.0 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 ******************************* * 20 * Look for: * 32bits of data, starting with 1010111, on the COM line * 20 Data on ABCN_COM (starting 1010111) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 0.0 400ns 0.0 + 401ns 0.0 420ns 0.0 + 421ns 0.0 440ns 0.0 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 0.0 560ns 0.0 + 561ns 0.0 580ns 0.0 + 581ns 0.0 600ns 0.0 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 2.5 660ns 2.5 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 2.5 780ns 2.5 + 781ns 2.5 800ns 2.5 + 801ns 0.0 820ns 0.0 + 821ns 2.5 840ns 2.5 + 841ns 0.0 860ns 0.0 + 861ns 2.5 880ns 2.5 + 881ns 2.5 900ns 2.5 + 901ns 2.5 920ns 2.5 + 921ns 0.0 940ns 0.0 + 941ns 2.5 960ns 2.5 + 961ns 2.5 980ns 2.5 + 981ns 0.0 1000ns 0.0 + 1001ns 0.0 1020ns 0.0 + 1021ns 0.0 1040ns 0.0 + 1041ns 2.5 1060ns 2.5 + 1061ns 0.0 1080ns 0.0 + 1081ns 2.5 1100ns 2.5 + 1101ns 0.0 1120ns 0.0 + 1121ns 2.5 1140ns 2.5 + 1141ns 0.0 1160ns 0.0 + 1161ns 2.5 1180ns 2.5 + 1181ns 0.0 1200ns 0.0 + 1201ns 0.0 1220ns 0.0 + 1221ns 0.0 1240ns 0.0 + 1241ns 2.5 1260ns 2.5 + 1261ns 0.0 1280ns 0.0 + 1281ns 0.0 1300ns 0.0 + 1301ns 0.0 1320ns 0.0 + 1321ns 2.5 1340ns 2.5 + 1341ns 0.0 1360ns 0.0 + 1361ns 2.5 1380ns 2.5 + 1381ns 0.0 1400ns 0.0 + 1401ns 2.5 1420ns 2.5 + 1421ns 0.0 ******************************* * 21 * Look for: * 32bits of data, starting with 1010111, on the L1 line * 21 Send Data on ABCN_L1 (starting 1010111) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 0.0 400ns 0.0 + 401ns 0.0 420ns 0.0 + 421ns 2.5 440ns 2.5 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 0.0 560ns 0.0 + 561ns 0.0 580ns 0.0 + 581ns 0.0 600ns 0.0 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 2.5 660ns 2.5 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 780ns 0.0 + 781ns 2.5 800ns 2.5 + 801ns 0.0 820ns 0.0 + 821ns 2.5 840ns 2.5 + 841ns 0.0 860ns 0.0 + 861ns 2.5 880ns 2.5 + 881ns 2.5 900ns 2.5 + 901ns 2.5 920ns 2.5 + 921ns 0.0 940ns 0.0 + 941ns 0.0 960ns 0.0 + 961ns 0.0 980ns 0.0 + 981ns 2.5 1000ns 2.5 + 1001ns 2.5 1020ns 2.5 + 1021ns 2.5 1040ns 2.5 + 1041ns 2.5 1060ns 2.5 + 1061ns 2.5 1080ns 2.5 + 1081ns 0.0 1100ns 0.0 + 1101ns 0.0 1120ns 0.0 + 1121ns 0.0 1140ns 0.0 + 1141ns 0.0 1160ns 0.0 + 1161ns 2.5 1180ns 2.5 + 1181ns 0.0 1200ns 0.0 + 1201ns 2.5 1220ns 2.5 + 1221ns 0.0 1240ns 0.0 + 1241ns 2.5 1260ns 2.5 + 1261ns 2.5 1280ns 2.5 + 1281ns 0.0 1300ns 0.0 + 1301ns 2.5 1320ns 2.5 + 1321ns 0.0 1340ns 0.0 + 1341ns 0.0 1360ns 0.0 + 1361ns 2.5 1380ns 2.5 + 1381ns 2.5 1400ns 2.5 + 1401ns 0.0 1420ns 0.0 + 1421ns 0.0 ******************************* * 22 * Look for: * 32bits of data, starting with 0101000, on the RESETB line * 22 Send Data on ABCN_RESETB (starting 0101000) V_COM COM_DUP0 0 PWL + 200ns 0 + 201ns 2.5 220ns 2.5 + 221ns 2.5 240ns 2.5 + 241ns 2.5 260ns 2.5 + 261ns 0.0 280ns 0.0 + 281ns 0.0 300ns 0.0 + 301ns 0.0 320ns 0.0 + 321ns 0.0 340ns 0.0 + 341ns 0.0 360ns 0.0 + 361ns 0.0 380ns 0.0 + 381ns 0.0 400ns 0.0 + 401ns 2.5 420ns 2.5 + 421ns 0.0 440ns 0.0 + 441ns 0.0 460ns 0.0 + 461ns 0.0 480ns 0.0 + 481ns 0.0 500ns 0.0 + 501ns 0.0 520ns 0.0 + 521ns 0.0 540ns 0.0 + 541ns 0.0 560ns 0.0 + 561ns 0.0 580ns 0.0 + 581ns 0.0 600ns 0.0 + 601ns 0.0 620ns 0.0 + 621ns 0.0 640ns 0.0 + 641ns 2.5 660ns 2.5 + 661ns 0.0 680ns 0.0 + 681ns 0.0 700ns 0.0 + 701ns 0.0 720ns 0.0 + 721ns 0.0 740ns 0.0 + 741ns 0.0 760ns 0.0 + 761ns 0.0 780ns 0.0 + 781ns 2.5 800ns 2.5 + 801ns 0.0 820ns 0.0 + 821ns 2.5 840ns 2.5 + 841ns 0.0 860ns 0.0 + 861ns 2.5 880ns 2.5 + 881ns 2.5 900ns 2.5 + 901ns 2.5 920ns 2.5 + 921ns 0.0 940ns 0.0 + 941ns 2.5 960ns 2.5 + 961ns 2.5 980ns 2.5 + 981ns 2.5 1000ns 2.5 + 1001ns 0.0 1020ns 0.0 + 1021ns 0.0 1040ns 0.0 + 1041ns 2.5 1060ns 2.5 + 1061ns 0.0 1080ns 0.0 + 1081ns 0.0 1100ns 0.0 + 1101ns 2.5 1120ns 2.5 + 1121ns 0.0 1140ns 0.0 + 1141ns 0.0 1160ns 0.0 + 1161ns 2.5 1180ns 2.5 + 1181ns 2.5 1200ns 2.5 + 1201ns 2.5 1220ns 2.5 + 1221ns 0.0 1240ns 0.0 + 1241ns 0.0 1260ns 0.0 + 1261ns 2.5 1280ns 2.5 + 1281ns 2.5 1300ns 2.5 + 1301ns 0.0 1320ns 0.0 + 1321ns 0.0 1340ns 0.0 + 1341ns 0.0 1360ns 0.0 + 1361ns 0.0 1380ns 0.0 + 1381ns 0.0 1400ns 0.0 + 1401ns 0.0 1420ns 0.0 + 1421ns 0.0