-- VHDL Entity hybrid.clock_reset_mgr.symbol
--
-- Created:
--          by - warren (pc140.hep.ucl.ac.uk)
--          at - 17:16:41 01/21/09
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1 (Build 17)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clock_reset_mgr is
   port( 
      bco    : in     std_logic;
      por    : in     std_logic;
      clk1x  : out    std_logic;
      clk2x  : out    std_logic;
      locked : out    std_logic;
      por_q  : out    std_logic
   );

-- Declarations

end clock_reset_mgr ;

--
-- VHDL Architecture hybrid.clock_reset_mgr.struct
--
-- Created:
--          by - Matt Warren
--          at - 17:16:41 01/21/09
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1 (Build 17)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


architecture struct of clock_reset_mgr is

   -- Architecture declarations

   -- Internal signal declarations
   signal clk4x    : std_logic;
   signal dout     : std_logic;
   signal por_hold : std_logic;
   signal porq1    : std_logic;
   signal porq2    : std_logic;
   signal qbx2     : std_logic;

   -- Implicit buffer signal declarations
   signal clk1x_internal : std_logic;
   signal por_q_internal : std_logic;


   -- ModuleWare signal declarations(v1.9) for instance 'Udffx2' of 'adff'
   signal mw_Udffx2reg_cval : std_logic := '0';

   -- ModuleWare signal declarations(v1.9) for instance 'Uporq1' of 'adff'
   signal mw_Uporq1reg_cval : std_logic := '0';

   -- ModuleWare signal declarations(v1.9) for instance 'Uporq2' of 'adff'
   signal mw_Uporq2reg_cval : std_logic := '0';

   -- Component Declarations
   component clockx4
   port (
      clk   : in     std_logic ;
      clk4x : out    std_logic 
   );
   end component;
   component count_delay
   generic (
      BITS : integer := 16
   );
   port (
      done : out    std_logic ;
      rst  : in     std_logic ;
      clk  : in     std_logic 
   );
   end component;


begin

   -- ModuleWare code(v1.9) for instance 'Udffx2' of 'adff'
   clk2x <= mw_Udffx2reg_cval;
   qbx2 <= not(mw_Udffx2reg_cval);
   prcudffx2seq: process (clk4x)begin
      if (clk4x'event and clk4x='1') then
         mw_Udffx2reg_cval <= qbx2;
      end if;
   end process prcudffx2seq;

   -- ModuleWare code(v1.9) for instance 'Uporq1' of 'adff'
   porq1 <= mw_Uporq1reg_cval;
   prcuporq1seq: process (clk1x_internal)begin
      if (clk1x_internal'event and clk1x_internal='1') then
         mw_Uporq1reg_cval <= por_hold;
      end if;
   end process prcuporq1seq;

   -- ModuleWare code(v1.9) for instance 'Uporq2' of 'adff'
   porq2 <= mw_Uporq2reg_cval;
   prcuporq2seq: process (clk1x_internal)begin
      if (clk1x_internal'event and clk1x_internal='1') then
         mw_Uporq2reg_cval <= porq1;
      end if;
   end process prcuporq2seq;

   -- ModuleWare code(v1.9) for instance 'Uand' of 'and'
   dout <= not(porq2) and por_hold;

   -- ModuleWare code(v1.9) for instance 'Ub' of 'buff'
   clk1x_internal <= bco;

   -- ModuleWare code(v1.9) for instance 'Uor' of 'or'
   por_hold <= dout or por;

   -- ModuleWare code(v1.9) for instance 'Uor1' of 'or'
   por_q_internal <= por_hold or porq1 or porq2;

   -- Instance port mappings.
   Ucmx4 : clockx4
      port map (
         clk   => bco,
         clk4x => clk4x
      );
   Ucd : count_delay
      generic map (
         BITS => 16
      )
      port map (
         done => locked,
         rst  => por_q_internal,
         clk  => clk1x_internal
      );

   -- Implicit buffered output assignments
   clk1x <= clk1x_internal;
   por_q <= por_q_internal;

end struct;