ITSDAQ Firmware Unified Change/Build Log ================================================================================ Legend (ish): ======================================== FPGA Board Types: NV: Nexys Video G2: Genesys II GLIB Interface Boards: FIB: FMC-IB - FMC-Interface Board FSC: FMC-Single-Chip - for Star-chips FDP: FMC-Display-Port - for Star-things FDM: FMC-DECAL (not ITk project) HTG: HiTechGlobal 4xSFP+ FMC (note this is the default for GBT and LPGBT builds) FQI: FMC-QSFP+ITk - The 2xQSFP+ by Carlos Garcia Argos (Freiburg) Other modifiers STAR - For star-chips (as opposed to '130 chipset) LPGBT - Uses fibres interface to talk to DUT GBT - Ditto IP - GBT Interposer - aka Test Vehicle (TV) IPAM2 - Build for testing AMACv2 via an IP PPA - Petal-Passive-Adapter pinout DDR - BigMem sequencer (uing DDR) enabled. From v_3c6 this the default for NV DPA - Dynamic Phase Adjust (and f/w 8b/10b decoding) in build - default from ~v_2c0 NODPA - No DPA in build 14PB - 14 powerboard stave. F/w has links available too. Also used for 5SS CS - Chipscope included with build (should have matching .ltx file. Hopefully) H - f/w histo enabled ('130 chipset only) SP01SWAP - For hybrid panels with SLVS (SP0 and SP1 lines swapped) EMUHV1 - Emulated HCCStarV1 added to the build (does not change base func: can be ignored) EMUAV1 - Ditto for ABCStarV1 SPECIAL - What is says on the tin - not for you, sorry ;-) Common build types: FIB_STD - 8 data links on J5, 8 on J6, 2 on J0 FIB_AMAC2 - 7 data links on J5, 7 on J6, 2 on J0. AMACv2 data on the D7s. Otherwise same as FIB_STD GBT_ST13S - Stave 130, segmented, 4 fibre build GBT_ST13S_4 - Ditto - just different name GBT_ST13S1 - Ditto, but 1 fibre only LPGBT_S2 - 2 LpGBT Star build with 14 e-links per LpGBT (takes over from 14PB for Pe/St readout) LPGBT_S4 - 4 LpGBT Star build with 14 e-links per LpGBT (not ready yet) *************************************************************************************************** * = Known broken! (default is "Might be broken...") *************************************************************************************************** G2 2024-05-13 c682 LPGBT_S4 PMOD JD re-assigned to SPI + added code to drive PMOD-TC1 G2 2024-04-08 c681 LPGBT_S2_FQI_10G 2-host hdr check latency reduction G2 2024-03-28 c680 LPGBT_S2_FQI_10G 2-host hrd_is_valid from FredUDP10G fix G2 2024-03-27 c67f LPGBT_S2_MIN_FQI_10G_CS 2-host fix 1 G2 2024-03-26 c67e LPGBT_S2_MIN_FQI_10G_CS Cut down build wth CS to debug 10G 2 host problem NV 2024-03-06 b67d FDP_STAR_AIDATLU TLU Clock line is now INPUT as EXTCLK1 NV 2024-03-05 b67c FSC_STAR_EMU EMUASICS test NV 2024-01-05 b67b FIB_STAR Refresh (updated I2C) NV 2024-01-05 b67b FSC_STAR Refresh (updated I2C) NV 2024-01-05 *b67b FDP_STAR Refresh (updated I2C) G2 2024-01-05 c67b LPGBT_S2_FQI_10G Refresh (updated I2C) G2 2024-01-05 c67b LPGBT_S2 Refresh (updated I2C) G2 2024-01-04 c67a FBB_CRATE I2C fix round 2.2 -- seems good! G2 2024-01-04 *c679 FBB_CRATE I2C fix round 2.1 G2 2024-01-03 *c678 FBB_CRATE New TWOWIRE I2C, round 2! G2 2023-12-21 c677 LPGBT_S4 Refresh G2 2023-12-20 c677 LPGBT_S4_FQI_10G Refresh G2 2023-12-15 c676 FBB_CRATE Refresh with below bugfix NV 2023-12-15 b676 FDP_STAR Fixed stupid AMAC halved pulse-width bug NV 2023-12-15 *b675 FDP_STAR reverted TWOWIRE back to b665 version (keeping TW_TRI mods) ----------------------- Vivado 2023.2 ---------------------------- NV 2023-11-09 *b674 FSC_STAR refresh G2 2023-11-09 *c674 FBB_CRATE I2C clk-stretching seems to work! G2 2023-11-08 *c673 FBB_CRATE_CS Still working on clk stretch. Reduced links too! G2 2023-11-07 *c672 FBB_CRATE_CS Still working on clk stretch. Reduced links too! ----------------------- Vivado 2023.1 ---------------------------- G2 2023-10-27 *c671 FBB_CRATE_CS Updated TWOWIRE for I2C clk-stretching. Reduced links for CS RAM! G2 2023-10-26 *c670 FBB_CRATE Refresh sanity check NV 2023-10-11 *b66f FSC_STAR refresh (with updated twowiretri block) G2 2023-10-10 *c66e FBB_CRATE Added I2C clock-stretch detection logic (didn't work!) Reworked I2C tristate system (using records) Updated AMAC DIT,DAH width thresholds to match final AMACStar! NV 2023-07-25 b66d FDP_STAR Updated FDP-only default OPHASE to 0x00ee G2 2023-07-19 c66c LPGBT_S2 I2C on EM4,5 for looking at HTG SFP 0,1 NV 2023-07-13 b66b FDP_STAR Fixed stupid CCR steering bug - everything was on seg 1! NV 2023-06-04 *b66a FDP_STAR Added CCR steering (as segs 0,1) G2 2023-06-20 c669 LPGBT_PP2_EMU_CS Adding chipscope to emuLpGBT for EMP testing G2 2023-06-20 *c668 LPGBT_PP2_EMU_CS NV 2023-03-21 b667 FDP_STAR Fixed no MDC bug NV 2023-03-21 b666 FDP_STAR No pullup on MDC on NV - Removed tristating and upped IOB DRIVE to 16 NV 2023-03-20 b665 FDP_STAR Added MDIO access to the MII Eth PHY on TWOWIRE chan 14 G2 2023-03-08 c664 LPGBT_S4_FQI_10G Refresh NV 2023-02-27 b663 FDP_STAR_ETH100M Build with 100Mb Ethernet ONLY G2 2023-02-20 c662 LPGBT_S4 GBT-SC LpGBTV0/1 steering via GBTSC opcode, Word1(12) (see twiki) also added port-id to returned data - twiki says it should be there! G2 2023-02-17 c661 LPGBTV1_S4 GBT-SC for LpGBTV1 G2 2023-02-17 c660 LPGBTV0_S4 Updated to gbt-sc 4.3, built for LpGBTV0 G2 2023-02-06 c65f LPGBT_S4 Added elink remapper via reg 57 G2 2023-02-06 c65e FBB_CRATE Added "rawsigs_en_steered" to Status: 15.GENSTAT(9:4) NV 2023-02-06 b65d FIB_STAR Adding debug to test clock (re)lock timings G2 2023-02-06 *c65d FBB_CRATE Reworked RawSigs steering (via OUTSIGS) AGAIN! G2 2023-02-10 c65c FBB_CRATE OUTSIGS mapping fix (possibly) G2 2023-01-16 c65b FBB_CRATE Enabled external clock input (PMOD-JA) (a la NV) NV 2022-12-13 b65a FSC_STAR_FINEDC_PS DDR address space mapping fix: 2x64Mx32b: addr(26) = select stripe 3:2 NV 2022-12-12 *b659 FSC_STAR_FINEDC_PS DDR with continuous read from stipes 1:0->3:2 (addr(25) = select stripe 3:2) NV 2022-12-05 b658 vb60c_FSC_STAR_PENN_SE(branch vb60c_updated) rebuild with PMOD clock out logic (a la vb654) NV 2022-12-05 b657 FSC_STAR_PENN_SE Rebuild for diags NV 2022-12-01 b656 FSC_STAR_FINEDC_PS Re-added BUFGs (they are needed!), removed BUFG from clk100 MMCM FB as no phase matching needed here NV 2022-11-30 *b655 FSC_STAR_FINEDC_PS enabled BTC phase shifting, removed BUFG from CLKFB in 4040 MMCM insts. may be a BAD idea! NV 2022-11-30 b654 FSC_STAR_PENN_SE Special: PMOD clock-in looped to PMOD JC9,10 (p,n LVCMOS33) moved to IBUFDS_DIFF_OUT for clock-in, and FAST, 16mA OBUFs NV 2022-11-22 b653 FSC_STAR_FINEDC reverted the below (but made it easier to do in the future) NV 2022-11-22 b652 FSC_STAR_FINEDC Increased TV expected dat/test pipelines latency by 12.5ns NV 2022-11-22 b651 FSC_STAR refresh NV 2022-11-21 b650 FSC_STAR_FINEDC fixes to SysReg(3) IDELAY-like phase shift option NV 2022-11-21 *b64f FSC_STAR_FINEDC finedc present bit added as stat53.13 NV 2022-11-21 *b64e FSC_STAR refresh G2 2022-11-15 c64d LPGBT_FBB_STAR_NOHSF Non HUGESFIFO version with XPM FIFO retained NV 2022-11-11 *b64c FSC_STAR_FINEDC Making HUGESFIFO default Phase shiftable programming changed to SysReg(3) IDELAY-like G2 2022-11-10 c64b FBB_CRATE_HUGESFIFO Ditlo NV 2022-11-09 b64b FSC_STAR_HUGESFIFO Ditlo G2 2022-11-09 c64b LPGBT_S4_HUGESFIFO Trying even larger (12->20kB) stream FIFOs G2 2022-11-09 c64a LPGBT_S4_HUGESFIFO Trying build with larger (6->12kB) stream FIFO, and using XPM NV 2022-11-03 b649 FSC_STAR_FINEDC fixed debug link (56-60) mapping G2 2022-11-03 c648 LPGBT_S4 Driving QSFP reset lines HIGH explicitly NV 2022-11-02 *b647 FSC_STAR_FINEDC Added IDELAY/ISERDES spy to LCB, BTC, PRLP NV 2022-11-02 *b646 FSC_STAR_FINEDC IDELAY/debug harmonised: BCO is link/idelaych 59 removed forcing unused links/delaystat to 0 in starcore_ins NV 2022-10-31 b645 FSC_STAR_FINEDC BCO copied to incoming IDELAY and stream - IDELAY ch 100, mon on link 62 (tried OFB, but can't used with IDELAY) G2 2022-10-27 c644 LPGBT_S4_FQI_10G Net-SoP counter bugfix G2 2022-10-24 c643 LPGBT_S4_FQI_10G Added 10GbE Net-SoP counter a la 1GbE version Fixed Net-data-packet counter G2 2022-10-20 c642 LPGBT_S4_FQI_10G refresh NV 2022-10-19 b641 FSC_STAR refresh (without FINEDC) NV 2022-10-19 *b641 FSC_STAR_FINEDC Added generic to select fine-dutycycle (and phase-shift) NV 2022-10-18 b640 FIB_STAR refresh NV 2022-10-18 b640 FDP_STAR refresh G2 2022-10-14 c63f FDP_STAR refresh NV 2022-10-13 *b63e FSC_STAR_FINEDC FSC LEMO outputs upped to 16mA FAST slew (from 12mA, SLOW) Removed BCO invert option (too slow), hardwired BCO+LCB to LEMOs (1,0 resp.) NV 2022-10-13 *b63d FSC_STAR_FINEDC Added invert prior to ODDR - need the delay anyway :-) NV 2022-10-13 *b63c FSC_STAR_FINEDC Trying ODDR of BCO (no bco invert option) NV 2022-10-11 *b63b FSC_STAR_FINEDC BCO fine phase adjust added NV 2022-10-11 *b63a FSC_STAR_FINEDC Radical: using clk40ps with 25% DC to control BCO DC FF directly NV 2022-10-10 *b639 FSC_STAR_FINEDC Better neg-edge logic NV 2022-10-10 *b638 FSC_STAR_FINEDC FSC BCO logic replaced with fine-DC version (via SysReg1 bits 15,13,12) fine-DC=no enable, invert or course dc options G2 2022-10-06 c637 FBB_CRATE Added outgoing packet decoder with HCC-SoP counter SysStat(29:28) G2 2022-10-06 c636 FBB_CRATE_CS Adding chipscope debugging G2 2022-10-05 c635 LPGBT_S4_FQI_10G refresh G2 2022-10-05 c634 LPGBT_S4 refresh G2 2022-10-04 c633 FBB_CRATE stream-fifo edgecase bugfix - TS fill can cause overflow in special cases pkt_gen type b ro 6 fixed to not send non-idle pattern G2 2022-10-04 c632 FIB_STAR refresh NV 2022-10-04 b632 FIB_STAR refresh G2 2022-09-29 c631 FBB_CRATE Trying fractional IPD instead (wait for fraction of last pkt len) sysreg2(11:8) G2 2022-09-28 c630 FBB_CRATE TX format fix for IPD G2 2022-09-28 *c62f FBB_CRATE Added programmable 16b inter-packet delay to tx_format sysreg2 G2 2022-09-28 c62e FBB_CRATE link sop_counter now uses fifo rdack (was _strb) Added global command for strm debug counter resets: cmd2.5 G2 2022-09-26 c62d FBB_CRATE Datagen HCC-pattern0xd updated to make more realistic packet NV 2022-09-22 b62c FDP_STAR Added simple burster alternative - enabled via 19(CONTROL1).4 G2 2022-09-21 c62b FBB_CRATE_NOPRSMX Rebuild without priority logic in data muxes G2 2022-09-20 c62a LPGBT_S4 refresh G2 2022-09-20 c629 FBB_CRATE refresh G2 2022-08-22 c628 LPGBT_S4 refresh NV 2022-07-29 b627 FIB_STAR refresh G2 2022-07-29 c627 LPGBT_S2 stooopid data_pkt_count fix G2 2022-07-28 c626 LPGBT_S2 Added sysstat data-packet counter - replaces frame counter G2 2022-07-28 c625 LPGBT_S2 Strm SoP counter fix, separated Seq-ID from netpkts_sent counter G2 2022-07-27 c624 LPGBT_S2 OLD bugfix! - stacked-up opcodes incl strm-conf write lost next opcode G2 2022-07-27 *c623 LPGBT_S2 Added 6 words to strm-stat - 3x32b counts: netpkt, sop, time G2 2022-07-27 *c622 LPGBT_S2 G2 2022-07-21 c621 LPGBT_S2 trig = DG err inject bugfix G2 2022-07-20 c620 LPGBT_S2_EMUHV1 Upped DG outstanding triggers to 0xffff (from 16) Fixed emu duplicate streams rate now set individually G2 2022-07-19 c61f LPGBT_S2_EMUHV1 adding emu ... G2 2022-07-18 c61e LPGBT_S2 Increased stream EoF counter from 3 to 8 bits - we may have been overflowing Fan PWM override via sysreg(0).3 G2 2022-07-08 c61d LPGBT_PP2_EMU emuAMACStar bugfix - changed endeavour.v to use 40MHz clock (EMU=emuAMACs on emuLpGBT on SFP2 of HTG) G2 2022-07-08 c61c LPGBT_PP2 Refresh G2 2022-07-04 c61b LPGBT_S4_FQI_10G Refresh G2 2022-06-28 c61a LPGBT_S2 Added TX/RX inverts to LpGBTn regs (60-63), TX=bit 5, RX=bit 4 G2 2022-06-27 b619 FIB_STARLOOP_EMUHV1 HCC decoder defaults to 8b10b mode (instead of Unencoded) G2 2022-06-24 c618 LPGBT_S2_EMUHV1 Added 320Mb compat to emuHCC->emuLpGBT G2 2022-06-23 c617 LPGBT_S2_EMUHV1 flipping HCC640->e-link phase (multiple CS versions, 24/6 too) G2 2022-06-23 c616 LPGBT_S2_EMUHV1 emu LCB/R3L1 bugfix NV 2022-06-23 b616 FSC_STAR_EMUHV1 refresh G2 2022-06-23 c615 LPGBT_S2_EMUHV1 TWOWIRE in rx_packet_decoder regression fix G2 2022-06-21 *c614 LPGBT_S2_EMUHV1 Added EMUHV1 to emuLpGBT NV 2022-06-21 *b613 FIB_STARLOOP_EMUHV1 refresh NV 2022-06-16 *b612 FSC_STAR Added more protection against receiving malformed packets G2 2022-06-13 c611 LPGBT_S2 refresh Atlys 2022-06-07 b610 VIB_STAR Atlys attempt (for irrad mess) (cap-started bugfix too!) NV 2022-05-31 b60f FIB_STAR dbg outputs (eg. J0 on FIB) now default to off (reg23=0, was 0x80) NV 2022-05-31 b60e FIB_STAR J6 OE (reg19.3) now affects ALL outputs, tristates them where possible NV 2022-05-25 b60d vb59f_FSC_STAR_CS (branch vb59f_updated) added CS from 60c NV 2022-05-25 b60c FSC_STAR_CS DDR timeout fix a la 603 added (was only on branch before) NV 2022-05-24 b60b FSC_STAR_CS Added debug catch logic for Jeffs DDR problem (for chipscope) NV 2022-05-24 b60a vb572_FSC_STAR_PS (branch vb572_updated) DPA-disabled bit now in status word (34) moved TV dat,test delays from strm-conf to reg47(2:0) and (6:4) respectively NV 2022-05-24 b609 vb572_FSC_STAR_PS (branch vb572_updated) Re-added PS on DCLK, but from same MMCM so no reset option NV 2022-05-23 b608 vb572_FSC_STAR (branch vb572_updated) added below (v_607) updates below NV 2022-05-23 b607 FSC_STAR Added "IPHASE" to vector input streams - use strm-conf(14:12) IDELAY prog reg9.7 is now manual mode, .15 is man-write-enable NV 2022-05-23 b606 vb572_FSC_STAR (branch vb572_updated) no PS, IDELAY man-mode bugfix retro-fit NV 2022-05-20 b605 FSC_STAR_EMUHV1 play time NV 2022-05-20 b604 FSC_STAR Stream-conf(14:12) revamped to allow MUCH more shifting NV 2022-05-20 b603 vb59f_FSC_STAR (branch vb59f_updated) DDR start-up timeout fix NV 2022-05-20 b602 FSC_STAR DDR back to pre vb5fe, BTC OS possible bugfix NV 2022-05-19 b601 FSC_STAR DDR: reverted vb5fe changes, added new one for timeout NV 2022-05-19 b600 FDP_STAR_TAM1LCB refresh NV 2022-05-18 b5ff FSC_STAR_EMUHV1 emu version (could be fun!) NV 2022-05-18 b5fe FSC_STAR Reworked DDR derandomiser readout to wait for almost_full before looking for SoF NV 2022-05-17 b5fd FIB_STAR_EMUHV1 Bugfix: CCR steering now defaults to all on (was all off when added in vb5e1) R3L1 phase offset set to match LCB (at 14) NV 2022-05-16 b5fc FSC_STAR refresh NV 2022-05-16 b5fb FDP_STAR refresh NV 2022-05-16 b5fa vb59f_FSC_STAR (branch vb59f_updated) fixed trigger=seq-go mode (trig was not disabled) NV 2022-05-16 b5f9 FSC_STAR invalid 8b10b symbols (re-)added to stream (cap2) - marked as K-codes (because that's really what they are) NV 2022-05-16 b5f8 vb572_FSC_STAR_PS (branch vb572_updated) Shmoo bugfix - was only 50MHz NV 2022-05-12 b5f7 vb572_FSC_STAR_PS (branch vb572_updated) synchronised PS clk reset NV 2022-05-12 b5f6 FSC_STAR refresh (FYI no phase shiftable BTC) NV 2022-05-11 *b5f5 FIB_STAR refresh NV 2022-05-06 b5f4 vb572_FSC_STAR_SHMOO (branch vb572_updated) rebuild with shmoo (55MHz BCO) constraints (Shmoo version now the default) NV 2022-05-06 b5f4 vb572_FSC_STAR (branch vb572_updated) Enabled phase shift of DCLK, added rst to PS clk (syscmd.14) NV 2022-05-06 *b5f3 vb572_FSC_STAR_PS (branch vb572_updated) NV 2022-05-06 b5f2 FSC_STAR_PS Enabled PS of DCLK only NV 2022-05-05 b5f1 vb59f_FSC_STAR (branch vb59f_updated) cap3 missing data bugfixes strmfifo: upped timestamp priority and added ts_req checks to TO states G2 2022-04-27 c5f0 FDP_STAR Refresh (justincasement) G2 2022-04-27 c5ef FBB_CRATE Push button debouncer for clk125 domain added NV 2022-04-26 b5ee FDP_STAR Refresh G2 2022-04-26 c5ed FBB_CRATE (branch vc5ab_updated) Added the priority fixes only (strm-stat priority=1 always, autosmx looks as priortity AND src_rdy) G2 2022-04-25 c5ec FBB_CRATE_CS Forced priority for non-data (aka opcode acks etc) G2 2022-04-25 c5eb FBB_CRATE_CS Fix regression in autosmx G2 2022-04-25 c5ea FBB_CRATE_CS Bugfix: added SrcRdy to Priority logic in autosmx BtnL toggles fan PWM mode G2 2022-04-25 c5e9 FBB_CRATE_CS_FANSLOW CS version with fan PWM enabled G2 2022-04-22 c5e9 FBB_CRATE Stream-status packets have priority=1 to squeeze past saturated data NV 2022-04-21 b5e8 FDP_STAR Bugfix: TLUreset(=ECR) was enabled when ExtTrig0 was enabled G2 2022-04-19 c5e7 FBB_CRATE Refresh (long overdue), PMOD_TTC (JA) I2C lines un-swapped NV 2022-03-29 b5e6 vb572_FSC_STAR (branch vb572_updated) reverted some updates to starcore_outs NV 2022-03-29 *b5e5 vb572_FSC_STAR (branch vb572_updated) added BCO DC mentioned below NV 2022-03-29 b5e4 FSC_STAR Added BCO course duty-cycle setting - reg6(3:0) Some PMOD input levels monitored in stat21 NV 2022-03-28 b5e2 FIB_STARLOOP FREDDIE 1G startup debug NV 2022-03-25 *b5e1 FIB_STAR_EMUHV1 Added CCR steering a la burnin-crate - J5=slot0, J6=slot1 NV 2022-03-25 b5e0 FSC_STAR_EMUHV1 LEMOs controlled via EXT_HW reg as per FastDIOs (as per original plan) Added LEMO source 255=High, 254=Low. G2 2022-03-23 c5df LPGBT_S2 refresh NV 2022-03-23 b5df FIB_STAR_EMUHV1 refresh NV 2022-03-22 b5de FIB_STARLOOP_EMUHV1 more auto-det hole plugs G2 2022-03-21 c5dd LPGBT_S2 Refresh NV 2022-03-21 b5dd FIB_STARLOOP_EMUHV1 Fixed auto-det timeout properly (1ms/HPR is a REALLY long time) G2 2022-03-21 *c5dc LPGBT_S2 Refresh (adding auto-det) NV 2022-03-21 *b5dc FIB_STARLOOP_EMUHV1 Fixed timout properly NV 2022-03-20 *b5db FIB_STARLOOP_EMUHV1 Auto-det timeout per step increased to 2ms to catch HPR in unenc NV 2022-03-19 b5da FIB_STARLOOP_EMUHV1 sequenced auto-resync better (settings THEN resync) NV 2022-03-18 b5d9 FIB_STARLOOP_EMUHV1 Added extra clocking stage to unenc path (to match 8b10b) Autodet resyncs before each step NV 2022-03-17 b5d8 FIB_STARLOOP_EMUHV1 HCCdec replaces Unenc Idle(0xff) with 0xbc Changed HCCdec-auto to try 8b10b first after resync NV 2022-03-17 b5d7 FIB_STAR_EMUHV1 refresh NV 2022-03-17 b5d6 FIB_STARLOOP_EMUHV1 refresh NV 2022-03-16 b5d5 FIB_STARLOOP lls.priority fix bugfix NV 2022-03-16 *b5d4 FIB_STARLOOP_EMUHV1 refresh NV 2022-03-16 *b5d3 FIB_STAR_EMUHV1 HCC decoder link rate/enc auto detect (en 23.13), strmstat(5:4) lss.priority CX FIFO into mux bugfix J6 CCR re-activated (common with J5) NV 2022-03-15 b5d2 FDM_DECAL_NOTERM (branch decal_528) hwin running stat added (stat15.14) NV 2022-03-15 b5d1 FDM_DECAL_NOTERM (branch decal_528) BtnD=ext_trigger0, lemos=trig only active FSC build NV 2022-03-11 *b5d0 FDM_DECAL_NOTERM (branch decal_528) Added triggered window mode (en reg23.2, width reg40) NV 2022-03-09 b5cf vb572_FSC_STAR (branch vb572_updated) LEMO1 as input G2 2022-03-09 c5ce LPGBT_S2 Refresh with latest everything G2 2022-03-07 c5cd LPGBT_S4_FQI_10G Refresh with latest everything G2 2022-03-07 c5cc LPGBT_S4_FQI_10G rebuild of vc591 with 640 f/w decoding select fix, stream double invert fix G2 2022-03-07 c5cb LPGBT_S2 Moved MGT MMCMs outside lpgbt/model toplevels NV 2022-03-01 b5ca FDM_DECAL_NOTERM (branch decal_528) removed sw6=powerup override (was added in rebuild = vb578) removed automatic counter clearing - use strmCmd(1) only NV 2022-02-25 b5c9 FDP_STAR refresh with all updates NV 2022-02-24 b5c8 FIB_STAR_EMUHV1 refresh with all updates NV 2022-02-24 b5c7 FIB_STARLOOP_EMUHV1 Fixed SA mode (by stopping the clock) resetting NV 2022-02-23 b5c6 FIB_STARLOOP_EMUHV1 SA MMCM can use internal clk160 - 20.CONTROL2.10 NV 2022-02-23 b5c5 FIB_STARLOOP_EMUHV1 SA-BERT regression fixed NV 2022-02-23 b5c4 FIB_STARLOOP_EMUHV1 EMUHV1 added NV 2022-02-23 b5c3 FIB_STARLOOP rxclk MMCM shared by SA-BERT and SA-EMU but bug=no EMUHV1 NV 2022-02-22 b5c2 FIB_STARLOOP_SPECIAL EMUHV1 using source clocks (not BTCin + MMCM) NV 2022-02-21 b5c1 FIB_STARLOOP_SPECIAL EMUHV1 wired internally, but using MMCM and external BTC NV 2022-02-21 b5c0 FIB_STARLOOP_SPECIAL EMUHV1 wired internally, but using MMCM NV 2022-02-21 b5bf FIB_STARLOOP_SPECIAL EMUHV1 wired internally (it works!) NV 2022-02-21 b5be FIB_STARLOOP_EMUHV1 BERT stand-alone, added some J0 debug on emuHV1 NV 2022-02-21 b5bd FIB_STARLOOP_EMUHV1 link 60=DG0 can now see =DG1 too: set 46.BERT_CTL.13 NV 2022-02-21 b5bc FIB_STARLOOP_EMUHV1 Retained BERT on links 1-6 NV 2022-02-18 b5bb FIB_STARLOOP_EMUHV1 dbg: added reg control of sa-emuHCC NV 2022-02-18 b5ba FIB_STARLOOP_EMUHV1 bugfix emu_rst pulse NV 2022-02-15 b5b9 FIB_STARLOOP_EMUHV1 added delayed, and automatic emu_rst pulse NV 2022-02-15 b5b8 FIB_STAR_EMUHV1 added optional emuhcc dout invert: 20.CONTROL2.9 NV 2022-02-15 b5b7 FIB_STARLOOP_EMUHV1 inverted dataout NV 2022-02-15 b5b6 FIB_STARLOOP_EMUHV1 tsync from source clock domain bugfix, aligned LCB/R3L1 NV 2022-02-15 b5b5 FIB_STARLOOP_EMUHV1 NV 2022-02-15 b5b5 FIB_STAR_EMUHV1 debug outputs on J0 now post emu insertion NV 2022-02-15 b5b4 FIB_STARLOOP_EMUHV1 NV 2022-02-15 b5b4 FIB_STAR_EMUHV1 added emu dataout phase control 20.CONTROL2(15:12) added J6 OE - used 19.CONTROL1.3 to enable J6 outputs set J6 outs to zero! (a temp fix, but forgotten) NV 2022-02-15 b5b3 FIB_STARLOOP_EMUHV1 8b10bdec tidy, err count only when synced NV 2022-02-16 b5b2 FIB_STARLOOP_EMUHV1 NV 2022-02-15 b5b1 FIB_STARLOOP_EMUHV1 LOOP build of below NV 2022-02-15 b5b1 FIB_STAR_EMUHV1 Recent BERT "fixes" removed NV 2022-02-14 b5af *FIB_STARLOOP_EMUHV1 Bug fix 320 8b10b frame-det + simplified logic BERT logic tidied/improved/maybe broken NV 2022-02-14 b5ae *FIB_STARLOOP_EMUHV1 Hanging an emuHCC off J6 NV 2022-02-14 b5ac *FIB_STAR_EMUHV1 emu moved to own entity (no func change, hopefully) G2 2022-02-04 c5ab *FBB_CRATE Fan is always full speed (i.e. PWM disabled) G2 2022-02-02 c5aa *FBB_CRATE Update/refresh NV 2022-02-02 b5aa *FIB_STAR Update/refresh NV 2022-02-02 b5a9 *FIB_STARLOOP Added HCC bit-phase (slip val) in strmstat(3:0) NV 2022-02-02 b5a8 *FIB_STAR_EMUHV1 FIB+emu bugfix NV 2022-02-02 b5a7 *FIB_STARLOOP Added HCC decoder bad symbol counter strmstat(15:12), cleared by COMMAND2.6 and STRMCMD.3 8b10b sync hardenedd to 2 consec idles of same phase NV 2022-02-01 b5a6 FDP_STAR refresh NV 2022-01-28 b5a5 FIB_STAR_EMUHV1 refresh NV 2022-01-28 b5a5 FSC_STAR_EMUHV1 refresh NV 2022-01-28 b5a4 FIB_STARLOOP PRBS bugfix (introduced vb59e) NV 2022-01-28 b5a3 FSC_STAR_EMUHV1 fsc version NV 2022-01-27 b5a2 FIB_STAR_EMUHV1 emu moved to be accessable by more builds - FIB attempt 0 here NV 2022-01-26 b5a1 FIB_STAR Trying out f_count_ones NV 2022-01-20 b5a0 FSC_STAR Added HCC decoder resync as COMMAND2.7 and STRMCMD.2 HCC decoder sync status added as StrmStat.2 ModulePresent status words (20:16) remapped onto LinkPresent(79:0) ModuleCount status word (3) changed to show LinkCount. NV 2022-01-19 b59f FSC_STAR HCCV1 test link fixup: BC_HYB (link 11) swapped with link 12 links 11(12),13 moved from WP debug to proper WP/SCB function links 5,6,11(12),13 moved to 16,17,18,19 NV 2022-01-17 b59e FIB_STARLOOP trying optimised PRBS gen for better shmoo perf NV 2022-01-17 b59d FIB_STARLOOP New build to replace FIB_STAR with BERT Master option G2 2022-01-13 c59b LPGBT_S6_FQI2 Refresh G2 2022-01-13 c59a LPGBT_S2 lpGBT clocking bugfix G2 2022-01-12 c599 *LPGBT_S2 Update/refresh G2 2022-01-12 c598 LPGBT_S6_FQI2 BERT updated to apply to all active links (was only up to link 67) G2 2022-01-11 c597 LPGBT_S6_FQI2 Testing possible FQI2 idea to have 2 lpGBT on DP8,9 NV 2022-01-07 b596 FSC_STAR_EMUHV1 Added BERT PRBS forced reset it init (bugfix: if locked it didn't reset) NV 2022-01-06 b595 FSC_STAR_EMUHV1 Changed start-up value of BERT PRBS away from 0xff (and 0x00) NV 2022-01-06 b594 FSC_STAR_EMUHV1 OLED fix + defaulting to UDPSTack for now (+ shmoo is still default) NV 2022-01-05 b593 FSC_STAR_NOSHMOO NV 2022-01-05 b592 FSC_STAR_EMUHV1_UDPSTACK - rebuild with UDP stack this time NV 2022-01-05 b592 *FSC_STAR_EMUHV1 With added emuHV1 NV 2022-01-05 b592 *FSC_STAR IDELAY man mode bugfix - enable bit is functional - can read value without programming it G2 2021-12-15 c591 LPGBT_S4_FQI_10G 10GbE now on QSFP2.1 (DP4) by default (easier passive cables etc.) G2 2021-12-22 c590 *FIB_STAR Update/refresh G2 2021-12-21 c590 *FBB_CRATE Update/refresh NV 2021-12-21 b590 *FIB_STAR Update/refresh NV 2021-12-21 b590 *FDP_STAR Update/refresh NV 2021-12-21 b590 *FSC_STAR Update/refresh G2 2021-12-21 c590 *LPGBT_S2 Update/refresh (has TX FIFO bugfix, priority and FredUDP) G2 2021-12-21 c58f LPGBT_S8_CS2 (2 lpGBT only)Fred G2 2021-12-21 c58f LPGBT_S8_CS (2 lpGBT only)Priority re-enabled and using more XPM FIFOs G2 2021-12-20 c58e LPGBT_S8_CS (2 lpGBT only)changed ll_pkt_fifo_16_axi8 to use XPM FIFO +half_full G2 2021-12-16 c58d LPGBT_S8_CS (2 lpGBT only)tx_timeout fix, more belt and braces dataflow stuff G2 2021-12-16 c58c LPGBT_S8_CS (2 lpGBT only)re-org of data mux - x-y transposed G2 2021-12-16 c58b LPGBT_S8_CS (2 lpGBT only)Rebuild with with HDS generated vhd (no license since 1/12) G2 2021-12-15 c58a LPGBT_S4_FQI_10GDP4 rebuild of vc568 with 10GbE on DP4 (QSFP2.1) G2 2021-12-15 c589 LPGBT_S8_CS (2 lpGBT only)Using 8 way mux ("mux10g") G2 2021-12-14 c588 LPGBT_S8_CS no priority in mux G2 2021-12-13 c587 LPGBT_S8_CS Added stream FIFO fullness and prioriy to spare nibble in stream data header G2 2021-12-10 c585 LPGBT_S8 gearing up for improved stream-resetting G2 2021-12-08 c584 LPGBT_S8 Added timeout to udp_tx_format for when it gets stuck. (Trying to catch problem in CS) G2 2021-12-07 c583 LPGBT_S8 remapped leds. Using UDPStack and no-10G-mux for baseline testing G2 2021-11-30 c582 LPGBT_S8 Proper S8 this time + jiggled with fan PWM settings But disabled BERT + EC debug streams + SysCon etc to make fit NV 2021-11-29 b581 FSC_STAR Fixed stream 20 (HYB_PRLP) regression + Added reg INVERTS control of HCC WP DATAOUT + OPHASEBnn control of phases G2 2021-11-24 c580 LPGBT_S8 MGT RXUSRCLK = TXUSRCLK set as default NV 2021-11-02 b57f FSC_STAR SHMOO55 is DEFAULT! All FSC builds (and likely all NV builds) will be 55MHz shmoo capbable NV 2021-11-02 b57e FSC_STAR_SHMOO55 Updated shmoo capabable build. G2 2021-11-24 c57d LPGBT_S6 Independent TX and RX build attempt NV 2021-11-23 b57c FSC_STAR Added Cap 3 16b mode - see ITSStarChips twiki G2 2021-11-22 c57b FBB_CRATE_CS See if we can catch CCR sigs leaving the boards where they should! G2 2021-11-19 c57a LPGBT_S6_1USRCLK 6 lpGBTs with RXUSRCLK=TXUSRCLK to save MMCMs/BUFGs (75% LUTs BTW) G2 2021-11-17 c579 *FBB_CRATE Special version, don't use: Slot mapping moved to "lpGBT" mapping: 100,104,108,112,116,120 NV 2021-11-12 b578 FDM_DECAL_NOTERM (branch decal_528) - rebuild of vb528_NOTERM with sw6=powerup override G2 2021-11-10 c577 FIB_STAR G2 version of FIB_STAR NV 2021-11-10 b576 FDM_DECAL_NOTERM sw6 forces *powerup* high (FMC-LA30N) G2 2021-11-09 c575 FBB_CRATE Alternative steering logic NV 2021-11-09 b574 FSC_STAR_EMUAV1_NOPMOD Re-added vector debug streams 22, 26 (and added 10,12) NV 2021-11-08 b573 FSC_STAR_EMUAV1_NOPMOD NV 2021-11-05 b572 FSC_STAR delayed all diff (non-fastdio) sigs by 25ns to allow for early RSTB NV 2021-11-05 b571 FSC_STAR fast dio bugfix NV 2021-11-05 b570 FSC_STAR improved course delay timing constency NV 2021-11-05 b56f FSC_STAR added delays PADID + coarse delay reg40(7:4) G2 2021-11-02 c56e LPGBT_S2_FAN_DBG longer on pulse, pwm controls off pulse-width NV 2021-11-03 b56d FSC_STAR Added ODELAY to RSTB - timing may change - set via reg40(3:0) G2 2021-11-02 c56c LPGBT_S2_FAN_DBG Dbg build sw(4:0) overrides fan pwm setting (note IP=.16) NV 2021-11-02 b56b FSC_STAR_SHMOO55 (branch ddr_shmoo) Rebuild - is project intact post auto-merge? G2 2021-11-02 c56a LPGBT_S2 Rebuild - with FredUDP-GbE (NOT 10GbE!) NV 2021-11-01 b569 FSC_STAR_SHMOO55 (branch ddr_shmoo) Fixed dead debug LEMOs G2 2021-10-28 c568 LPGBT_S4_FQI_10G Rebuild after uppgrading all IP NV 2021-10-28 b567 FIB_STAR J6 CCR sigs active - can be used as per J5 - links(32:39) EM(2) I2C(10) G2 2021-10-27 c565 FBB_CRATE Using UDPStack G2 2021-10-27 c564 FBB_CRATE Added CCR steering (100-105) G2 2021-10-25 c563 LPGBT_S4_FQI_10G Trying with 4 lpGBTs G2 2021-10-23 c563 LPGBT_TEST_10GTEST Fixed swapped lpGBT RX/TX bigbug. Moved 10GbE to FMC-DP7 to allow MGTREFCLKs to have 1 quad each G2 2021-10-14 c562 LPGBT_TEST_10GTEST_CS added 1 clk packet gap going into FredUDP, len fifo tweaks etc G2 2021-10-14 c561 LPGBT_TEST_10GTEST_CS CX FIFO control fixes G2 2021-10-13 c560 LPGBT_TEST_10GTEST_CS TX FIFO control fixes G2 2021-10-10 c55d LPGBT_TEST_10GTEST_CS UDP checksum fix (AGAIN!) - it doesn't work, so must be 0x00 G2 2021-10-10 c55b LPGBT_TEST_10GTEST_CS rx tready rework, tx len calc/insert fix G2 2021-10-10 c559 LPGBT_TEST_10GTEST_CS connected all the data lines (oops!) G2 2021-10-09 c558 LPGBT_TEST_10GTEST_CS TX showing signs of life in WS NV 2021-10-07 b556 FSC_STAR HCC Prober mode option (reg16.13) inverts DATAOUT8 and HYP_PRLP Reworked link mappings, and removed dbg mapping for links 13:10 G2 2021-10-07 c556 LPGBT_TEST_10GTEST_CS udp_tx_format10g first go G2 2021-10-05 c555 LPGBT_TEST_10GTEST_CS 10G UDP RX functional :-):-) G2 2021-10-04 c553 LPGBT_TEST_10GTEST_CS udp_rx_format10g first go G2 2021-09-29 c54e LPGBT_TEST_10GTEST_CS next step G2 2021-09-29 c54d LPGBT_TEST_10GTEST_CS SFP3=10GbE - NV 2021-09-29 b54d FSC_STAR_EMUHAV1 Manual IDELAY bug-fix NV 2021-09-17 b54c FSC_STAR_EMUHAV1 fixed emuAV1 resets NV 2021-09-16 b54b FSC_STAR_EMUHAV1 Updated 3xABC and HCC emu NV 2021-09-16 b54a FSC_STAR_EMUAV1 added idelay value monitoring - selected via reg 9, read via stat34 NV 2021-09-16 b549 FSC_STAR_EMUAV1 regression fix - wrong emu 1b-2b clock used NV 2021-09-15 b548 FSC_STAR_EMUAV1 fix to make vectors work NV 2021-09-15 b547 *FSC_STAR_EMUAV1 Added seperate Vect-compare latency setting for AV1 TESTDAT reg14(15:12) Added DPA "manual mode" -- allows writing delay values directly NV 2021-09-14 b547 FDP_STAR EM_TX routing now via MUX, not OR - allows inversions NV 2021-09-10 b545 FSC_STAR_EMUHAV1 Trying with both 3xABC and HCC emu ... It fits!! NV 2021-09-09 b544 FSC_STAR_EMUHAV1 Trying with both ABC and HCC emu! NV 2021-09-02 b543 FSC_STAR_EMUHV1 Reverted to original UDP (UDPStack) NV 2021-09-02 b542 FSC_STAR_EMUHV1 First go at integrating emuHCCStarV1 NV 2021-08-19 b541 FSC_STAR (FredUDP) upped RX PacketBuffer to 4kB (waw 512B) also upped TX buffer to 4kB (from 2kB) for slight derandomising benefit NV 2021-08-17 b540 FSC_STAR Refresh with FredUDP NV 2021-08-17 b53f FIB_STAR (FredUDP) New PacketBuffer from Carsten, set TX checksum=0000, IP flags=0000 NV 2021-08-16 b53e FIB_STAR (FredUDP) stupid mapping rc tvalid/tkeep swap fix NV 2021-08-16 b53d FIB_STAR (FredUDP) below messes up other things (as expected_, "solution" is to hardwire tready to 1 - buf gets confused otherwise NV 2021-08-16 b53c FIB_STAR (FredUDP) removed a +1 from transport/udp/rxbuf (!) NV 2021-08-12 b53b FIB_STAR (FredUDP) added proper tready into fredudp NV 2021-08-12 b53a FIB_STAR (FredUDP) rotateUserUdpIF=1 NV 2021-08-12 b539 FIB_STAR (FredUDP) forcing UDP - no RawETH NV 2021-08-12 b538 FIB_STAR Carsten UDP - FREDUDP (from FREDDIE project) added. 1st go! NV 2021-08-10 b537 FSC_STAR_SHMOO55 clocks at 55MHz, but DDR still at 400MHz (can't go higher) NV 2021-08-10 b536 FSC_STAR no schmoo sanity check NV 2021-08-10 b535 FSC_STAR_SHMOO50 Updated DDR with 400MHz (vs usual 320MHz) timing, clock 50MHz NV 2021-08-10 b534 FSC_STAR_SHMOO50 Built with 50MHz BCO constraints - for shmoozing NV 2021-07-23 b4b4 FSC_STAR_AV1EMU_PMOD Rebuild of old version with PMODs added like they should be NV 2021-07-16 b533 FSC_STAR Added 32b victor mismatch counters and placed in stat2 block G2 2021-07-19 c532 LPGBT_S2 ditlo NV 2021-07-16 b532 FDP_STAR 8 way data-mux (with 8 FIFOs) - first attempt. G2 2021-07-19 c531 LPGBT_S2 ditlo NV 2021-07-16 b531 FDP_STAR updated data path mux priority system NV 2021-07-15 b530 FDP_STAR pktgen len tuning NV 2021-07-15 b52f FDP_STAR cap len tuning NV 2021-07-15 b52e FDP_STAR Natch 176 looplen - it's actually 22 NV 2021-07-15 b52d FDP_STAR ABC DG resets counter for each loop. Also has 176 in looplen NV 2021-07-15 b52c FDP_STAR Capture len extended from 10 to 16 bits NV 2021-07-14 b528 FDM_DECAL_NOTERM Rebuild of older version only DIFFTERM=FALSE changed NV 2021-07-14 b52b FDM_DECAL_NOTERM DIFFTERM=FALSE NV 2021-07-14 b52a FDP_STAR Added priority to data mux system NV 2021-07-13 c529 LPGBT_S2 ditlo NV 2021-07-13 b529 FDP_STAR Tidied data muxes and added start of 10G multiple data lanes option NV 2021-07-08 b528 FDM_DECAL tided p/dcount_run alignment - no more gap NV 2021-07-08 b527 FDM_DECAL Added stat bit for pcount_run, and handled pcount = 0 condition NV 2021-07-08 b526 FDM_DECAL New pcount for decal pre-count delay - count starts on seqstart NV 2021-07-08 b525 FDM_DECAL New dcount for decal NV 2021-07-07 b523 FDM_DECAL OLED fix! NV 2021-07-06 b520 FDM_DECAL trying an OLED fix ... NV 2021-07-05 b51f FDM_DECAL Tidied decal_deser timings NV 2021-07-05 b51e FDM_DECAL DG rejigged to make more useful tests NV 2021-07-04 b51d FDM_DECAL fixed statread reporting old data regression NV 2021-07-02 b51c FDM_DECAL counter counting accounting accounted-for (trying a new way to do decal counting) NV 2021-07-02 b51b FDM_DECAL StatRead blkid=2 changed to blkid=12 new count modes in strmconf NV 2021-07-02 b51a FDM_DECAL Added cap3 mode to cap data while counting NV 2021-07-01 b519 FDM_DECAL rejigged DG to DIO to be different ... NV 2021-07-01 b518 FDM_DECAL Added DG to DIO - just like we used to ... NV 2021-07-01 b517 FDM_DECAL Outgoing PLLCLK fixed! NV 2021-06-30 b516 FDM_DECAL Changed IDELAY reset - to use /ready from IDELAYCTRL NV 2021-06-30 b515 FDM_DECAL Counter mapping fix NV 2021-06-24 b514 FDM_DECAL DG mapping fix NV 2021-06-24 b512 FDM_DECAL Bugletfix3 NV 2021-06-22 b510 *FDM_DECAL Bugfixing2 NV 2021-06-22 b50f *FDM_DECAL Bugfixing NV 2021-06-22 b50e *FDM_DECAL Added bit counters to decal code, operated via OC_STATREAD(!) Updated OC_STATREAD - countdown timer and more blocks (see twiki) G2 2021-06-18 c50d LPGBT_S2 clock timer bugfix G2 2021-06-17 c50c LPGBT_S2 trial: FEC errors added to LpGBT stats, OLED clk/10 test G2 2021-06-17 c50b LPGBT_S2 EMORSE has last seen DAH width in response word clock period timer to sysstat G2 2021-05-21 c50a FDP_STAR Refresh/trying to see if .bit file compression really makes a difference here G2 2021-04-30 c509 LPGBT_S4 Refresh G2 2021-04-29 c508 LPGBT_S2 Re-added PLL lock to LpGBTn status words G2 2021-04-22 c507 LPGBT_S2_DBGEC Added EC(0),(1) as data links 28,29 for dbg via capture EMORSE(60:32) <= data links(27:0) DBGEC: EC(0),(1) mapped to PMOD-TTC trig_out(JA9), busy_ext(JA10) G2 2021-03-25 c506 LPGBT_S4 First complete S4 build - don't expect too much! G2 2021-03-24 c505 LPGBT_S2 Regression fix! dnlink data corrupt starting v501 Fixed latch inducing code that was eating BUFGs (my bad) Moved LpGBT clock PLL to clock block G2 2021-03-23 c504 LPGBT_S4 YES! S4!! - lets see what happens ... G2 2021-03-23 c503 LPGBT_S2 converted lpgbt_fpga block to vhd for generate compat G2 2021-03-19 c502 LPGBT_S2 signal tidys G2 2021-03-16 c501 LPGBT_S2 LPGBT code re-org - no func change (hopefully) G2 2021-03-11 c500 FDP_STAR NV 2021-03-10 b500 FIB_STAR refresh G2 2021-03-07 c4fe LPGBT_S2 Fan fix 5? G2 2021-03-06 c4fd LPGBT_S2 Fan fix 4? NV 2021-03-04 b4fb FDP_STAR ditlo G2 2021-03-04 c4fb LPGBT_S2 Fan fix 2 Not G2 2021-03-03 c4fa LPGBT_S2 Fan fix? No! NV 2021-03-03 b4f9 FDP_STAR Updated timer for OLED and fan G2 2021-03-03 c4f9 LPGBT_PP2_EMU Added links 0 to 27 for debug G2 2021-03-03 c4f8 FBB_CRATE Added I2C on PMOD-C/D (pin 1=SCK,2=SDA). Channels 1,0 respectively NV 2021-02-26 b4f7 FDP_STAR OPHASE default set to 0xe NV 2021-02-24 b4f6 FDP_STAR refresh - ditlo G2 2021-02-24 c4f6 LPGBT_S2 refresh - includes 8b10b decoding (post data-path reorg) G2 2021-02-17 c4f5 LPGBT_PP2_EMU refresh G2 2021-02-16 c4f4 FBB_CRATE ditlo NV 2021-02-16 b4f4 FIB_STAR Inverting data BEFORE 8b10b isn't what we want! G2 2021-02-16 c4f3 FBB_CRATE ditlo NV 2021-02-16 b4f3 FIB_STAR Stream invert applies to all data sources now G2 2021-02-08 c4f2 FBB_CRATE G2 builds updated for latest datapath changes NV 2021-02-14 b4f2 FIB_STAR bugfix - looking good! NV 2021-02-14 b4f1 FIB_STAR more moving readout blocks around NV 2021-02-13 b4f0 FIB_STAR moved hcc decoder to readout block NV 2021-02-12 b4ef FIB_STAR complete rework of datapath post ISERDES - all 8b@80 now NV 2021-02-09 b4ed FIB_STAR CX problem with DG moving to 160 domain attempted fix NV 2021-02-09 b4ec FIB_STAR Unenc fix G2 2021-02-09 c4eb FBB_CRATE DG PRBS bugfix - invert option re-added G2 2021-02-08 c4ea FBB_CRATE Refresh NV 2021-02-08 b4e9 FIB_STAR Moved 10b8b aligner and decoder to clk80 (from clk160) NV 2021-02-08 b4e8 FIB_STAR Gearbox tweak3 NV 2021-02-07 b4e5 FIB_STAR Set PRBS to start at non-zero NV 2021-02-07 b4e4 FIB_STAR re-worked 8b10b gearbox NV 2021-02-02 b4e3 FIB_STAR More teeny 8b10b dec tweeks NV 2021-01-29 b4e2 FIB_STAR Teeny 8b10b dec tweeks NV 2021-01-28 b4e1 FIB_STAR Sync resets for 8b10b decoder et al. NV 2021-01-28 b4e0 FIB_STAR BERT init bugfix NV 2021-01-27 b4df FIB_STAR Rebuild for BERT testing G2 2021-01-25 c4de LPGBT_S2 astar deser regression bugfix G2 2021-01-25 c4dd *LPGBT_S2 DG 16b@40 bugfix G2 2021-01-22 c4dc *LPGBT_S2 Targeted BERT reset when multi G2 2021-01-22 c4db *LPGBT_S2 BERT updates for multi G2 2021-01-22 c4da *LPGBT_S2 More DG options for model, and added back internal Model connection G2 2021-01-21 c4d9 *LPGBT_S2 DL byte-swap option (56.7) and debug data (56.3 + 16.12) G2 2021-01-21 c4d8 *LPGBT_S2 DG option added to CCR and LpGBT-like loopback too G2 2021-01-20 c4d6 *LPGBT_S2 Adding BERT - try 0 G2 2021-01-20 c4d5 *LPGBT_S2 Using latest code again, with small mods to constraints G2 2021-01-20 c4d4 *LPGBT_S2 Reverted to pre seg steering CCR G2 2021-01-19 c4d3 *LPGBT_S2 Removed Model-LpGBT internal link option (56.12) G2 2021-01-19 c4d2 *LPGBT_S2 EC channels mapped back to proper home (LpGBTn=EMn) G2 2021-01-19 c4d1 *LPGBT_S2_PPATEST TEST VERSION!! Mapped CCR links onto segments a la PPA ONLY for people called Dennis! G2 2021-01-18 c4d0 *LPGBT_S2 Added CCR segment steering (see twiki Reg List) NV 2021-01-15 b4cf *FIB_STAR Rebuild for BERT testing GLIB 2021-01-13 94cf GBT_IPAM2 Remapped EM to use 160Mb e-links (on a 320Mb elink pitch) and went back to single stream GLIB 2021-01-13 94ce GBT_IPAM2 Enabled all streams to allow rx_link to be demuxed correctly(!) G2 2021-01-12 c4cd LPGBT_PP2_EMU rx mapping bugfix G2 2021-01-11 c4cb LPGBT_PP2_EMU PP2 build with emuAMACs on LpGBT-MODEL0 G2 2021-01-08 c4ca LPGBT_PP2 First go at PP2 build +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++++ 2021 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ NV 2020-11-19 b4c9 FIB_STAR DG counter rollover bugfix G2 2020-11-17 c4c8 LPGBT_S2 IC looking good - going for increased buffer size (40 = 32 data byte capable) NV 2020-11-17 b4c7 FIB_STAR_SP01SWAP refresh G2 2020-11-17 c4c7 LPGBT_S2 Updated to latest gbt-sc - ic_tx.vhd changed - fingers crossed G2 2020-11-17 c4c6 LPGBT_S2 Timeout reverted to 30ms, gbtsc ocb double word bug fix + more timeout err codes G2 2020-11-17 c4c5 LPGBT_S2 Longer GBT-IC timeout (30ms->300ms) NV 2020-11-16 b4c4 FIB_STAR More small BERT fixes NV 2020-11-16 b4c3 FDP_STAR Auto L1 bugfix (L0A period > L1A period would not work) NV 2020-11-13 b4c2 FDP_STAR BERT refinements NV 2020-11-12 b4c1 FIB_STAR LCB delay offset changed to 14 (from 0) - better OOTB results NV 2020-11-11 b4c0 FIB_STAR HCC PRBS BERT enabled version G2 2020-11-11 c4bf LPGBT_S2 refresh NV 2020-11-05 b4be FIB_STAR PRBS BERT trial 0 NV 2020-11-04 b4bd FIB_STAR_SP01SWAP refresh NV 2020-10-30 b4bc FIB_STAR Update to latest BERT code G2 2020-10-20 c4bb FBB_CRATE Update to latest BERT code NV 2020-10-20 b4bb FIB_STAR BERT take 2 NV 2020-10-20 b4ba FIB_STAR_AMACV2_TEST Silly bugfix (the AMAC bus is not pulled high in emu! Doh!) NV 2020-10-19 b4b9 *FIB_STAR_AMACV2_TEST emu-AMAC with buses (ITSDAQDataFormat#AMACV2_TEST_builds) STATREAD takes snapshot of statblock pre sending (so counters don't jump) NV 2020-10-12 b4b8 FSC_STAR_SEESPECIAL Special SEE with remapped IO NV 2020-10-13 b4b7 FIB_STAR Added BERT options (a la FBB) D0-5 have 1 BERT each An additional BERT services all other links NV 2020-10-12 b4b6 FSC_STAR_AV1EMU OLED init fix GLIB 2020-10-08 94b5 GBT_IPAM2 Upgraded for PP2 crate (4/8x EM) testing NV 2020-10-07 b4b4 FSC_STAR_AV1EMU Cap3 with TS inserted if multiple per packet. Overlaps optimised. NV 2020-10-06 b4b3 FSC_STAR_AV1EMU strm_en = 0 no longer clears the strm shift reg NV 2020-10-05 b4b2 FSC_STAR_AV1EMU Capture3 using capture start bugfix. More TS bits added as stat 14 NV 2020-09-30 b4b1 FIB_STD Refresh NV 2020-09-30 b4b0 FDM_DECAL_TERM Tidied deser machine disable handling NV 2020-09-28 b4af FDM_DECAL_TERM Invert option connected this time!! NV 2020-09-28 b4ae FSC_STAR_AV1EMU Next-gen data-gen generated (see Starchips twiki) G2 2020-09-21 c4ad LPGBT_S2 refresh to grab general updates NV 2020-09-16 b4ac FDP_STAR HCC Unenc mode decoder working NV 2020-09-16 b4ab FDP_STAR Cap2 bugfix - increased length of inactivity check NV 2020-09-14 b4aa FDP_STAR DG update NV 2020-09-14 b4a9 FDP_STAR Update with fixed deser bug NV 2020-09-12 b4a8 FSC_STAR_AV1EMU_CS Fixed ABCStar deserialiser bug + more DG G2 2020-09-11 c4a7 FDP_STAR G2 build may be useful NV 2020-09-10 b4a6 FSC_STAR_AV1EMU_CS Rebuilt below with CS added NV 2020-09-10 b4a6 FSC_STAR_AV1EMU Added emu prlp phase180 control (swap pr and lp) NV 2020-09-10 b4a5 FSC_STAR_AV1EMU stupid bugfix (introduced due to tidying - there is a lesson there!!) NV 2020-09-10 b4a4 *FSC_STAR_AV1EMU refresh, for sanity NV 2020-09-09 b4a3 *FSC_STAR_AV1EMU Emu lines set to dat=0xda and test=0x75 (@640Mb) when no-emu build fixed bugs in auto-L1/R3 gen fixed phasing bug in PRLP to emu NV 2020-09-06 b4a2 FSC_STAR_AV1EMU_CS Bug huntin' time NV 2020-09-04 b4a1 FSC_STAR_AV1EMU Emu option to be remapped as per remap board - set bit 20.2 (Control2.2) NV 2020-09-04 b4a0 FSC_STAR_AV1EMU Added dly pipe offset to the vect expected data -- SEE counters now use raw data (unaffected by all but inv in strmconf) NV 2020-08-28 b49f FDP_STAR Added SEE counters on data 1 NV 2020-08-27 b49e FSC_STAR Temp and OLED trial fix NV 2020-08-27 b49d FIB_STAR_AMACV2_TEST Bugfix - emu-AMACs connected this time NV 2020-08-26 b49c FDM_DECAL_TERM Links connected this time! NV 2020-08-26 b49b FDM_DECAL_TERM Refresh for sanity NV 2020-08-25 b49a FSC_STAR Command2 bugfix (cmd2 was being retained, thx Bruce), Added TS counter to status(11:10) NV 2020-08-25 b499 FSC_STAR TestDataout counters added: edges on (31:0), integrated 1.56ns steps (31:0) NV 2020-08-24 b498 FSC_STAR Trying testout edgecounter 640 NV 2020-08-24 b497 FSC_STAR_CS Back to RSTB, with optional invert now reg 18.6, applied to all NV 2020-08-24 b496 FSC_STAR_CS bugfix: reg 14.12 didn't work!! NV 2020-08-24 b495 FSC_STAR_CS Vect-RST(B) invert option - reg 14.12 NV 2020-08-21 b494 FSC_STAR_CS More seq output CS added NV 2020-08-21 b493 FSC_STAR_AV1EMU_CS Seq output CS added G2 2020-08-21 c493 FBB_CRATE Ditlo NV 2020-08-21 b493 FSC_STAR_AV1EMU Added IP address to OLED, moved FPGA_TEMP to sysstat(1) NV 2020-08-19 b492 FSC_STAR_AV1EMU Oled fix NV 2020-08-19 b491 FSC_STAR_AV1EMU Inverted RSTB in hardware - now used as RST in reg and vect G2 2020-08-18 c490 FBB_CRATE 1st try at 36 BERTs at once NV 2020-08-18 b490 FSC_STAR_AV1EMU vect-ID bugfix (was enabled by the wrong reg!!). fast-dio in vect mode now under EXT_HW_DRV reg control G2 2020-08-17 c48f FBB_CRATE BERT fix and cleanup - more func and reduced resoures - yay! G2 2020-08-17 c48e FBB_CRATE First go at 320Mb BERT NV 2020-08-14 b48d FIB_STAR_AMACV2_TEST Added AMAC reset command (Command2.9), moved block back to top level NV 2020-08-13 b48c FSC_STAR_AV1EMU Fixed double inversion of incoming stream for vect compare NV 2020-08-06 b48b FIB_STAR Refresh NV 2020-08-06 b48a FSC_STAR_AV1EMU En bits added to RTVECT_CTL for Remapper lines in vector NV 2020-07-29 b489 FSC_STAR Improved data-gen NV 2020-07-29 b488 FSC_STAR Re-enabled seq2 NV 2020-07-29 b487 FIB_STAR_SP01SWAP Bugfix (last good build was 323!!) NV 2020-07-28 b486 FSC_STAR Added ASV1 option with RSTB and ID in vector NV 2020-07-27 b485 FIB_STAR_AMACV2_TEST Stupid unused sigs=0 clash. Moved test into diogrpfmc/fib_star NV 2020-07-27 b484 FIB_STAR_AMACV2_TEST Doh - swapped EM TX, RX NV 2020-07-27 b483 FIB_STAR_AMACV2_TEST Special build with 8 emu AMACS (CHIPIDs 8-15, EFUSEIDs 0x12348-f) NV 2020-07-20 b482 FSC_STAR 1st attempt at rolling buffer (for DECAL, but testing here) G2 2020-07-16 c481 FBB_CRATE BERT_RESET also resets errinjects-counter G2 2020-07-15 c480 FBB_CRATE Yet another silly bugfix to a bugfix to a bugfix G2 2020-07-15 c47f FBB_CRATE stream invert must apply to DG too! G2 2020-07-14 c47e FBB_CRATE must try harder G2 2020-07-14 c47d FBB_CRATE silly bugfix (bug introduced in c47b!!) G2 2020-07-14 c47c FBB_CRATE inj counter reset G2 2020-07-14 c47b FBB_CRATE removed BERT_RX_INV - inverts obey strm conf now G2 2020-07-13 c47a FBB_CRATE bugfix - err injects count bugfix G2 2020-07-13 c479 FBB_CRATE bugfix - fixed BERT inject err command G2 2020-07-09 c478 FBB_CRATE bugfix in BERT link select G2 2020-07-09 c477 FBB_CRATE debug(6) (strm 124) was missing G2 2020-07-09 c476 FBB_CRATE Rejigged DG to include BERT and rationalised other instances G2 2020-07-07 c475 FBB_CRATE Bugfix - forgot about sending LFSR on BTC line NV 2020-07-03 b474 FSC_STAR Looking at better emu timing - with clk160n - seems to work NV 2020-07-02 b473 FSC_STAR Bug fix in link 7 vector check invert NV 2020-07-01 b472 FSC_STAR Vector compare now respects if stream is inverted in strmconfig NV 2020-07-01 b471 FSC_STAR Vect-debug streams aligned with, added clocks-on during vects only (14.5) NV 2020-07-01 b470 FSC_STAR Added vect expected data to strms 24, 26 NV 2020-06-30 b46f FSC_STAR vect_clk_en bugfix for BCO, added debug match streams 28,30 NV 2020-06-29 b46e *FIB_STAR_SP01SWAP 2020 refresh of special build with SP0 and SP1 swapped G2 2020-06-29 c46d FBB_CRATE direct mode added to CCR so BERT works here NV 2020-06-29 b46d FSC_STAR_CS Updates to OPTIONS generic - but no func change NV 2020-06-25 b46c FSC_STAR_CS latency fixes, high res properly applied, dat,test skew removed NV 2020-06-24 b46b FSC_STAR_CS TVECT latency resolution increased to 160Mb steps NV 2020-06-25 b46a FDM_DECAL_TERM LVDS TERM=TRUE version NV 2020-06-25 b469 FDM_DECAL Yes, it's real, and there is a new one ... NV 2020-06-24 b468 FSC_STAR_CS COMMAND2(CRC_RESET) fix when used to reset reset emu NV 2020-06-24 b467 FSC_STAR_CS NV 2020-06-23 b466 FSC_STAR_NODDR3_CS Added programmable CHIP-ID - reg20.(7:4) NV 2020-06-23 b465 FSC_STAR_NODDR3_CS Added emu reset from crc_clr and vect_intclks bit NV 2020-06-21 b464 FSC_STAR_NODDR3_CS Lets go chipsco (vect-emu matching seems not to work :-( ) NV 2020-06-19 b463 FSC_STAR EMU-ASIC reset bit added (reg 20.1) NV 2020-06-19 b462 FSC_STAR TVect CRC resets added (command2 bit too) NV 2020-06-19 b461 FSC_STAR Added generate PRLP from L1 (as per R3L1) option (reg16.5) NV 2020-06-15 b460 FSC_STAR ABCStarV1-Emu included as option - Select with CONTROL2.0 (reg20.0) NV 2020-06-15 b45f FSC_STAR Missing emu chip-id fix NV 2020-06-15 b45e FSC_STAR Vector check using count mode added NV 2020-06-15 b45c FSC_STAR IDELAYCTRL clock fix (ditlo) [+ unfinished vector stuff] NV 2020-06-12 b45b FDP_STAR_NOBIGMEM Changed IDELAYCTRL clock back to 200MHz G2 2020-05-20 c45a LPGBT_S2 Added sys-fmc ports (can test HS-I2C code) NV 2020-05-19 b459 FSC_STAR Added I2C master-code option - set TW control (3:0) = 0xf NV 2020-05-11 b458 FSC_STAR_AV1EMU LCB encoder serial command input fix - LCB read gen problem NV 2020-05-07 b457 FSC_STAR_AV1EMU_NOPMOD ABCStarV1 emu as is connected as per SCB G2 2020-04-28 c456 LPGBT_S2_DENNIS_CS IC bugfix + update to CERN gbt-sc 3.0 Atlys 2020-04-02 a455 VADAPT_AMAC_H Updated to current (UDP etc) - needs testing - first build in 18m! G2 2020-04-02 c455 LPGBT_S2_DENNIS_CS CS on LpGBT IC lines NV 2020-03-31 b454 FIB_PPA_STAR Trying out 3 way overload NV 2020-03-31 b453 FDP_STAR Trying out overloading "or" for records NV 2020-03-30 b452 FDP_STAR bugfix transferring L0A/BCR to trig block NV 2020-03-17 b451 FDP_STAR LCB decoder on rawsigs LCB decodes L0As and BCR feeds counters NV 2020-03-17 b450 FDP_STAR TS packlets added when Cap2 triggered NV 2020-03-13 b44f FDP_STAR Missed EOP fix, "synced" state added to 8b10b dec NV 2020-03-11 b44e FDP_STAR More HCC 8b10b bug fixes NV 2020-03-10 b44d FDP_STAR HCC 8b10b cap2 bug fixes G2 2020-03-05 c44c FBB_BERT_I2CPB111111 First G2 BERT build G2 2020-02-12 c44b FBB_CRATE_I2CPB111111 SPECIAL - replaces ToAMAC with I2C pair ALL *SLOTS* NV 2020-02-12 b44a FDP_STAR_NODPA Ditlo NV 2020-02-12 b449 FIB_STAR_NODPA Trying out IDELAYCTRL REFCLK=312.5MHz (may break Eth,DDR) G2 2020-02-11 c448 LPGBT_S2 I2C SDA/SCK set low always - tristate still controls line, but this may avoid glitches NV 2020-02-11 b448 FIB_STAR_NODPA Want to scan the eye ... G2 2020-02-07 c447 LPGBT_S2 EM for second LpGBT now working (EM channel 1) G2 2020-02-06 c446 LPGBT_S2 Added rawsigs steering via OUTSIGS a la GBTx G2 2020-02-06 c445 LPGBT_S2_DENNIS MGT TXOUTCLK on JB7/8 (nee TLU_TCLK) NV 2020-02-04 b444 FDP_STAR IBUF_LOW_PWR = false G2 2020-02-04 c444 FBB_CRATE IBUF_LOW_PWR = false NV 2020-01-24 b443 FDP_STAR DG for link-decoding bugfix NV 2020-01-24 b442 FDP_STAR Added DG to pre-8b10b "link-decoding" options NV 2020-01-24 b441 FDP_STAR_TAM1LCB Isolate em_ser_out_all <= em_ser_out(0) only NV 2020-01-23 b440 FDP_STAR Flags bug fixed NV 2020-01-23 b43f FDP_STAR_TAM1LCB invert em_ser_out(1) NV 2020-01-23 b43e FDP_STAR_TAM1LCB fixed em_ser_out(1) typo bug NV 2020-01-23 b43d FDP_STAR New 64b block format for 8b10b enc data see Starchips twiki NV 2020-01-23 b43c FDP_STAR 8b10b decoder data formatter bugfix NV 2020-01-22 b43b FDP_STAR Bruce added patterns to HCC pattgen NV 2020-01-21 b43a FIB_STAR Added Data-gens to D2 and D3 (config same as D0, D1 resp.) NV 2020-01-21 b439 FDP_STAR Bugfix: BERT stat regs no longer zero NV 2020-01-21 b438 FDP_STAR Added BERT invert rx data option (via BERT_CTL reg) NV 2020-01-21 b437 FIB_STAR refresh for sanity NV 2020-01-21 b436 *FDP_STAR_TAM1LCB removed 2 EM streams, added BERT dbg instread NV 2020-01-20 b435 FIB_STAR Updated BERT regs, standalone works by default NV 2020-01-16 b432 FIB_STAR Realised BERT depended on link setup. shouldn't, now doesn't. NV 2020-01-17 b431 *FDP_STAR_TAM1LCB Special Craig build with ToAMAC1 on both LCB outputs NV 2020-01-16 b42a FIB_STAR BERT-Gen uses correct 160MHz ext clk (BCO is actually BTC) NV 2020-01-16 b429 FIB_STAR BERT-Gen uses external clock input (BCO, J5->J6)(didn't work) Trig makes error, BERT-GEN connected to dbgstrm(4,5)= (60,61) NV 2020-01-15 b428 FIB_STAR BERT added (seemed to work!) G2 2020-01-15 c428 LPGBT_S2 CCR LCB/R3L1 swaps via (via OUTSIGS) (vc426 idea abandoned) NV 2020-01-14 b427 FIB_STAR DG for BERT added (not actual BERT yet) G2 2020-01-13 c426 LPGBT_S2 Alternative CCR mapping added (via OUTSIGS) NV 2020-01-06 b425 FDP_STAR multi-host UDP fixes: separate seq-no counters, DefSet ack NV 2020-01-03 b424 FDP_STAR_CS multi-host UDP src-id now transmitted via FIFO (using MN) NV 2020-01-03 b423 FDP_STAR_CS updated UDP oc-port handling (not working) ********* New Vivado Version -- 2019.2 ******** ---- 2 0 2 0 ------------------------------------------------------------------------------- NV 2019-12-19 b422 FDP_STAR refresh G2 2019-12-19 c421 FIB_LOOPTEST_PRBS3 J6 back to all PRBS outs, J0 has copies of some J5 ins: D0,lo,D1,lo,D4,lo,D5 (lo=diff logic low) G2 2019-12-18 c420 FIB_LOOPTEST_PRBS2 Copied J5 D0-D4 ins to J6 BCO-SP1 outs. NO streams G2 2019-12-18 c41f FIB_LOOPTEST_PRBS PRBS outs on J6 D0-D3: 640Mb, D4-7:320Mb, the rest 160Mb G2 2019-12-17 c41e FBB_CRATE_NODIFFTERM FMC DIFF_TERM = FALSE! G2 2019-12-13 c41d LPGBT_S2 Net TX bug fixed! G2 2019-12-11 *c416 GBT_ST13S Sanity check (yep - insane!) G2 2019-12-10 *c415 LPGBT_S2 Trying with indendent MGT- RX clocking G2 2019-12-09 *c414 LPGBT_S2 Added EM loopback option (reg 51=0x60). G2 timestamp bug fixed. G2 2019-12-06 *c413 FBB_CRATE refresh NV 2019-12-06 *b412 FIB_STD_H Variable len event packets (set reg 32.13 to enable) G2 2019-12-04 c40d FIB_STD_H refresh G2 2019-12-04 c40c FIB_STAR G2 version (new!) NV 2019-12-04 b40b FIB_STD refresh NV 2019-12-04 b40a FIB_PPA_STAR refresh GLIB 2019-12-04 940a GBT_IPAM2 refresh NV 2019-12-04 b409 FSC_STAR refresh NV 2019-12-04 b409 FDP_STAR refresh G2 2019-12-03 c408 LPGBT_S2 refresh G2 2019-12-02 c407 GBT_ST13S_CS UDP/Raw mode bit added to sys status G2 2019-12-02 c406 GBT_ST13S_CS added rx count and rejigged sysstat to make fit G2 2019-12-02 c405 GBT_ST13S_CS added net counters reset command (SR1.8) added MAC "frame-success" counter G2 2019-11-29 c404 GBT_ST13S_CS extended sysstat 32, added loads of nic mon counters etc includes rx and tx stats vects def_mac_set opcode re-enabled G2 2019-11-29 c403 GBT_ST13S_CS udp_tx_format SM fix G2 2019-11-29 c402 GBT_ST13S_CS TX UDP CS added G2 2019-11-28 c402 GBT_ST13S refresh G2 2019-11-28 c401 LPGBT_S2_NORAWETH Added tighter flow control to udp_tx_format G2 2019-11-27 c400 LPGBT_S2_NORAWETH RawEth disabled G2 2019-11-27 c3ff GBT_ST13S_H Added the histo option to RO_OPTIONS, so this is now a new build type G2 2019-11-27 c3fe GBT_ST13S Added endless cap mode to 130 (a la star) G2 2019-11-27 c3fd LPGBT_S2 EM emu bugfix (intro'd trying to fix real EM one) G2 2019-11-27 c3fc LPGBT_S2 Added dnlink dg options (a la _TEST) G2 2019-11-27 c3fb GBT_ST13S Refresh G2 2019-11-27 c3fa LPGBT_S2 Sanity check G2 2019-11-26 c3f9 LPGBT_S2 Added missing ec_pattgen sig (hangover from _TEST) May have caused EM path to be removed! G2 2019-11-26 c3f8 LPGBT_S2 Both LpGBTs made identical, more loopback opts. Added EM->StartCap bit reg23.8 Added IFG control (G2 only) via sysreg2 G2 2019-11-19 c3f6 LPGBT_S2 AMAC-EC moved to EM(0) and EM(1) added for LpGBT(1) Added AMAC-emu to Models for loopback testing NV 2019-11-19 b3f6 FDP_STAR SWAPPED EM(0) and EM(2) to match data links G2 2019-11-19 c3f5 GBT_ST13S_CS Trying TXBUF_EN = TRUE in _gt.vhd NV 2019-11-19 b3f5 FDP_STAR Re-added FDR EM(!) NV 2019-11-19 b3f4 FDP_STAR Added no rxwaittx option (untested) G2 2019-11-19 c3f4 GBT_ST13S_CS All TX clocks use TX(1) NV 2019-11-18 b3f3 FDP_STAR Added EM-in(0:3) as dbg streams 118,120,122,124 G2 2019-11-18 c3f2 GBT_ST13S_CS G2 2019-11-18 c3f1 GBT_ST13S_CS G2 2019-11-15 c3f0 FBB_CRATE Refresh G2 2019-11-14 c3ef GBT_ST13S Refresh NV 2019-11-12 b3ef FDP_STAR Refresh GLIB 2019-11-07 93ed GBT_IPAM2 Another changed to , linelfsr and gap durations GLIB 2019-11-07 93ec GBT_IPAM2 Changed linereset, linelfsr and gap duration GLIB 2019-11-07 93eb GBT_IPAM2 Added more EMs and LSFR EM gen func (EM ctl bit 61) NV 2019-11-07 b3ea FDP_STAR reverted to old UDP NV 2019-11-07 b3e9 *FDP_STAR UDP still bad - hardcoded src/dst ports = 60001 NV 2019-11-07 b3e8 *FDP_STAR UDP bug-fix. Also f/w tx-src-port = rx-dst-port NV 2019-11-06 b3e7 *FDP_STAR Seperate auto-L1 and auto-R3 enables (19.10, 19.15) L0A SOLO trigger option - see Stars twiki page + multi-port UDP (which broke the build) NV 2019-11-06 b3e6 FIB_STD Refresh for Thomas NV 2019-11-06 b3e5 FDP_STAR bugfixed L1,R3 counters stuck at zero NV 2019-11-06 b3e4 FDP_STAR fixed L1A/R3 double-counting, and added ecr as reset NV 2019-11-05 b3e3 FDP_STAR Added L1A and R3 counters - stat 54,55 NV 2019-11-05 b3e2 FDP_STAR re-added option to delay R3/L1 as per '130 auto-L1 G2 2019-11-05 c3e2 LPGBT_S2 New build type for 2xLpGBT. Updates to R3/L1 auto-triggering too NV 2019-11-04 b3e1 FDP_STAR trigger_top_star: no trigger-count busy bug fixed NV 2019-11-04 b3e0 FDP_STAR ccr_manager fifo no-longer fills when not enabled NV 2019-11-04 b3df FDP_STAR R3/PR improves NV 2019-11-01 b3dd FSC_STAR First go at Star PR/R3 aware f/w NV 2019-10-24 b3dd FSC_STAR Added CRCs to inputs stat 12,13 0 see twiki:ITSDAQStarChips#Readout_Link_Mapping NV 2019-10-24 b3dc FSC_STAR Added CRCs to rawsigs and seq2 - see stat 10,11 NV 2019-10-28 b3db FIB_STAR Debug streams moved to 56-62 NV 2019-10-24 b3da FSC_STAR Back to DPA version NV 2019-10-24 b3d9 FSC_STAR_NODPA Fixed over-zeolous tidying NV 2019-10-24 b3d7 FSC_STAR_NODPA Tidied code, removed fifo depth from status. No CS. NV 2019-10-23 b3d6 FSC_STAR_NODPA_CS BigMem Vectors working! NV 2019-10-23 b3d5 FSC_STAR_NODPA_CS Nuther BigMem fix -- do need to end on time tho NV 2019-10-23 b3d4 FSC_STAR_NODPA_CS Nuther BigMem fix -- no need for VectEnd in all cases NV 2019-10-23 b3d3 FSC_STAR_NODPA_CS BigMem addr_count jumping to start_addr at end bugfix NV 2019-10-23 b3d2 FSC_STAR_NODPA_CS Fixed 3d1 bugs, Seq-Reset pulse added - Command2.12 NV 2019-10-23 b3d1 FSC_STAR_NODPA_CS Improved bigmem vect timing. NV 2019-10-23 b3d0 FSC_STAR_NODPA_CS BigMem logic changes (FIFO too) + disabling is cleaner NV 2019-10-22 b3cf FSC_STAR_NODPA_CS Both rawseq and bigmem-stripe0 via SIGS_IDLE BigMem: added zeroing when not running NV 2019-10-18 b3ce FSC_STAR_NODPA_CS LEMO mapping bug fixed NV 2019-10-18 b3cd FSC_STAR_NODPA_CS DDR (re)fix - I 4rsed a merge NV 2019-10-17 b3cc FSC_STAR_NODPA_CS Cap3 bug fix. DDR addr/2 fix (may still be bad tho) ALL cap start->data offsets changed NV 2019-10-16 b3cb FSC_STAR_NODPA_CS LEMO debug outs remapped for this build (DDR CS too) NV 2019-10-16 b3ca FDP_STAR_NODPA_CS LEMO debug outs remapped. DDR CS re-enabled. NV 2019-10-15 b3c9 FDP_STAR_NODPA Capture3 added. NV 2019-10-14 b3c8 FIB_PPA_STAR OLED reset connected to Darkmode Added Eth PHY MDIO signals as TWOWIRE channel 14 (0xe ;-) ) NV 2019-10-14 b3c7 FIB_PPA_STAR Added Darkmode option (via sw(7)). NV 2019-10-14 b3c6 FIB_PPA_STAR Dennis spotted the bug (FIB_PPA_STAR sigs not inverted as per FIB)! Moved CCR bus enables to bits 6:4 in OUTSIGS (harmonisation) NV 2019-10-11 b3c5 FDP_STAR_DDR_CS Bugfix: VectorEnd state flux up fixed. NV 2019-10-11 b3c4 FDP_STAR_DDR_CS Bugfix: SeqGo working again! NV 2019-10-11 b3c3 FDP_STAR_DDR_CS Attempts to make vector running more robust. Added error bit to sq_stat NV 2019-10-10 b3c2 FDP_STAR_DDR_CS QDR readback improved, added capture_start delay (regs 39,38) NV 2019-10-09 b3c1 FDP_STAR_DDR_CS First QDR version (also added some SQ stat regs) NV 2019-10-08 b3c0 FSC_STAR_DDR_CS Fixed seq logic NV 2019-10-08 b3bf FSC_STAR_DDR_CS DDR debug version with CS rebuild G2 2019-10-02 c3bf FBB_CRATE Rebuild with updated BTC pinout NV 2019-09-27 b3be FSC_STAR NV 2019-09-27 b3bd FSC_STAR_NODPA Added reg bit to show if DPA enable (54.4) NV 2019-09-16 b3bc FIB_PPA_STAR Refresh GLIB 2019-09-20 93bb GBT_IPAM2 New IC added here too (and generally getting build up to date) G2 2019-09-19 c3ba LPGBT_TEST Trying out new IC NV 2019-09-18 c3b9 FSC_STAR_DDR_CS DDR debug version with CS NV 2019-09-18 c3b8 FSC_STAR_DDR Test build with DDR included G2 2019-09-18 c3b8 GBT_ST13S1 IC Wr auto read response for OC reply G2 2019-09-18 c3b7 FBB_CRATE First go at pinout for V1 PCB G2 2019-09-17 c3b6 GBT_ST13S1_CS Buggly fix - reg not connectd gbtsc block - IC works! G2 2019-09-17 c3b5 GBT_ST13S1_CS One more IC/EC swapsy G2 2019-09-16 c3b4 GBT_ST13S1_CS bugfix - was no OC_GBTSC in build!!! NV 2019-09-16 b3b4 FDP_PPA_STAR Star build this time - was 130 (doh!) G2 2019-09-16 c3b3 GBT_ST13S1 Swapped IC & EC around in GBT frame (!!) NV 2019-09-14 b3b2 FDP_PPA_STAR YANB G2 2019-09-13 c3b1 LPGBT_14PB Radical take 3: use MGT txusrclks on stave - WORKS!!! G2 2019-09-13 c3b0 LPGBT_TEST Radical take 2: use MGT txusrclks for rxusrclks - WORKS!!! G2 2019-09-13 c3af LPGBT_TEST MGT RXs use BUFGCE (didn't work) G2 2019-09-13 c3ae LPGBT_TEST MGT TXs shared MMCM G2 2019-09-13 c3ad LPGBT_TEST TX & RX MMCM - sanity check squared G2 2019-09-13 c3ac LPGBT_TEST Back to RX MMCM - sanity check - still bad (???) G2 2019-09-13 c3ab LPGBT_TEST Radical: use txusrclks for rxusrclks G2 2019-09-12 c3aa LPGBT_TEST BUFGCE RX reduced rst-pipe - still not good G2 2019-09-12 c3a9 LPGBT_TEST BUFGCE RX (improved) version G2 2019-09-12 c3a8 LPGBT_TEST MMCM RX version G2 2019-09-12 c3a7 LPGBT_TEST Cross-check (Model moved to DP2 in TEST version now) G2 2019-09-12 c3a6 LPGBT_14PB_2lpGBT attempting a slightly better reset structure G2 2019-09-11 c3a5 LPGBT_14PB_2lpGBT simplified gtcommon reset G2 2019-09-11 c3a4 LPGBT_14PB_2lpGBT new MGT clocking scheme, lpGBT models on DP2,3 G2 2019-09-11 c3a3 LPGBT_14PB_2lpGBT common reset for lpGBT0/1 via reg 60 G2 2019-09-10 c3a2 LPGBT_14PB_2lpGBT Fixed lpGBT status mapping, and added lpGBT1(61) status G2 2019-09-09 c3a2 LPGBT_14PB_2lpGBT Fixed partial bad stream map bug (streams 10,12?) G2 2019-09-09 c3a1 FBB_CRATE Swapped EM ins and outs G2 2019-09-09 c3a0 LPGBT_14PB_2lpGBT the right number of streams G2 2019-09-09 c39f LPGBT_14PB_2lpGBT sigs bugfix G2 2019-09-06 c39e LPGBT_14PB_2lpGBT NOT TESTED! G2 2019-09-05 c39d FBB_CRATE_NODPA G2 2019-09-05 c39c FBB_CRATE Added LCB delay to R3L1 delay too G2 2019-09-04 c39b FBB_CRATE BTC now working G2 2019-09-04 c39a FBB_CRATE New build for the FMC-BurningBlade - the burn-in crate FMC/system NV 2019-09-02 b399 FDP_STAR_NODPA IDELAY phase control version (no Dynamic Phase Adjustment) NV 2019-09-02 b398 FDP_STAR This time really with all 24 links (debug links moved to 56-62) G2 2019-09-02 c398 LPGBT_14PB Code now supports using using links 29-31 etc. - should not affect this build G2 2019-08-16 c397 GBT_ST13S_H_3GBT Reverted to original reset G2 2019-08-16 c396 LPGBT_14PB Update to latest everything else G2 2019-08-15 c395 GBT_ST13S_H_3GBT GBT control bit mapping fix + trial reset change (resetOnBitslip_s = '1') (much worse) + GBT stat (56-59) now rx_lock_lost count NV 2019-08-15 b394 FDP_STAR Without the JPM DPA (aka also without 8b10b) blocks NV 2019-08-14 b393 *FIB_STAR_SP01SWAP_NODPA Trying without the JPM DPA (+8b10b) blocks G2 2019-08-14 c393 GBT_ST13S_H_3GBT 3 GBTs, but all other options enabled G2 2019-08-14 c392 GBT_ST13S_H G2 2019-08-14 c391 GBT_ST13S_H Doh, same version num but with histo! (had to turn off SysCon and stream-delay 640 to make fit, but still AWESOME to have 112 links/streams each with histo!) G2 2019-08-13 c391 GBT_ST13S Added individual GBT phase80 settings (was global before) NV 2019-08-13 b391 FDP_STAR Trig-data stream changed to 127. trig-data strm-conf field set to 0xaaaa NV 2019-08-13 b390 FDP_STAR Fixed incorrect trig-data strm-id NV 2019-08-13 b38f FDP_STAR 24 links enabled, improved trig-data FIFO latency (moved to _plus with plus disabled) G2 2019-08-10 c38e GBT_ST13S Fixed incorrect widebus mode enable bit polarity G2 2019-08-10 c38d GBT_ST13S Added all-GBT TX/RX resets to GBTGEN_GTL (ST13S is now alwyas a 4 GBT) G2 2019-08-09 c38c GBT_ST13S1 Added all-GBT TX/RX resets to GBTGEN_GTL G2 2019-08-09 c38b GBT_ST13S1 Longer reset time, and individual resets to each GBT (RX and TX) added G2 2019-08-09 c38a GBT_ST13S1 Removed rx_ready driving tx_elink_enc_en G2 2019-08-09 c389 GBT_ST13S1 Bugfix: Connected DP2/3 (which GBT2/3 if in build) Set all TX ICEC to 00 - it may have messed up TX path G2 2019-08-09 c388 GBT_ST13S1 New build type for single GBT only (faster turnaround debugging) NV 2019-08-08 b388 *FIB_STAR_SP01SWAP Refresh of special build with SP0 and SP1 swapped G2 2019-08-08 c387 GBT_ST13S_4 Added TX elink data = elink id option (a la LPGBT TEST) fixed ocb_strmconf_rd NV 2019-08-07 b386 FSC_STAR PS Dec/Inc via SysReg1 bits 12/13 (it works!) - Note SysReg(1) is now a "command-pulse" reg G2 2019-08-07 c386 GBT_ST13S_4 Added option to swap TW SCK/SDA - see TW twiki G2 2019-08-07 c385 GBT_ST13S_4 Fixed PMOD_TTC mapping - user sees no difference NV 2019-08-06 b384 FDP_STAR New clkgen, with PS (but disabled for now) G2 2019-08-05 c383 GBT_ST13S_4 OUTSIGS HMULTI has GBT2,3 added NV 2019-08-05 b382 FDP_STAR TWOWIRE125 added G2 2019-08-05 c382 GBT_ST13S_4 Now with PMOD-TTC (doh!) G2 2019-07-26 c381 GBT_ST13S_4 Refresh (ingly good) NV 2019-07-23 b380 FDP_STAR Updated Star 64b block handling G2 2019-07-25 c380 LPGBT_TEST Bugfix in raweth TX path, rejigged SysCoreReset to reset (lp)GBT MMCM/PLLs G2 2019-07-24 c37f LPGBT_TEST_CS Chipscope debug on TWOWIRE125 ++ G2 2019-07-24 c37e LPGBT_TEST_CS Chipscope debug on TWOWIRE125 G2 2019-07-24 c37d LPGBT_TEST Rebuild for sanity NV 2019-07-23 b37c FSC_STAR_60MHZ Build with 60MHz BCO G2 2019-07-23 c37c LPGBT_TEST TWOWIRE moved to sys GLIB 2019-07-22 937b GBT_IPAM2 EM timeout bugfix NV 2019-07-19 b37a FIB_STD SysReg reset-all (1=0x80) re-added G2 2019-07-18 c379 LPGBT_TEST EM timeout fix G2 2019-07-12 c375 LPGBT_TEST removed count check etc. now EoP can be long 1 or long 0 G2 2019-07-11 c374 LPGBT_TEST Added extra post deglitch serin line to PMOD JA9, added nodeglitch option to EM_CTL.4 added EM RX bit count check and trailing spurion ignore G2 2019-07-11 c373 LPGBT_TEST EMORSE "execute old" bugfix G2 2019-07-11 c372 LPGBT_TEST Added EM debug lines on PMOD JB JB 7:em_ser_in(14),8:em_ser_out(14),9:em_rx_error,10:em_rx_start G2 2019-07-10 c371 GBT_ST13S_4 trying with local clocks for sanity G2 2019-07-04 c36b GBT_ST13S_4 Removed BCAST stuff for streams - they're not used G2 2019-07-04 c367 GBT_ST13S_2 Sanity check too G2 2019-07-07 c366 LPGBT_TEST Sanity check G2 2019-07-04 c365 GBT_ST13S_4_H Histo now fits too. G2 2019-07-04 c364 *GBT_ST13S_4 FOUR GBTs! HTG version (all are for now) - does not work tho :-( G2 2019-07-04 c363 LPGBT_TEST Now using RTYP_STARA G2 2019-07-02 c362 LPGBT_14PB Add (back) the IC monitoring streams NV 2019-07-02 b361 FDP_STAR Inverted R3L1 lines G2 2019-07-01 c360 GBT_ST13S_2GBT_HTG_H Refresh G2 2019-06-28 c35f LPGBT_14PB CCR downlinks, no Model, no HCC-decoder G2 2019-06-25 c35d LPGBT_TEST Added AMACv2a emu on EM15 G2 2019-06-24 c35c LPGBT_TEST GLIB 2019-06-24 935c GBT_IPAM2 More hysterical: H>6, L<1) GLIB 2019-06-21 935b GBT_IPAM2 Changed rx detect to hysterical counter (0-7, H>5, L<2) EM tx width setting control via reg 53 GLIB 2019-06-21 935a GBT_IPAM2 Changed rx detect to 4 in 5 bits (@80Mhz) changed detection limits +/- 1 to compensate for >/< tests GLIB 2019-06-20 9359 GBT_IPAM2 Added AMACv2a emu on em ch 15 GLIB 2019-06-20 9358 GBT_IPAM2 Glitch ignore increased from 12.5 to 25ns, slightly shorter gap between tx and rx-enable ... G2 2019-06-18 c358 LPGBT_TEST Added AMACv2a emu connected to Model-EC G2 2019-06-18 c357 LPGBT_TEST Changed model-dnlink clocking structure G2 2019-06-18 c355 LPGBT_TEST Slight change to EC -> EM conversion G2 2019-06-18 c354 LPGBT_TEST_CS added clocking stage to lpgbt-fpga downlink enc G2 2019-06-17 c353 LPGBT_TEST_CS G2 2019-06-14 c351 LPGBT_TEST dg double values, count nibble order bugfix G2 2019-06-14 c350 LPGBT_TEST Lots of simple DG options - see twiki LpGBT regs GLIB 2019-06-12 934f GBT_IPAM2 EM "resetline" pulse extended from 5us to 50us GLIB 2019-06-12 934e GBT_IPAM2 Fixed runt pulse in 8MHz clock GLIB 2019-06-12 934d GBT_IPAM2 EM "resetline" 8MHz clock in place of pulse G2 2019-06-11 c34c LPGBT_TEST More simplified DG - 8b counter only. Uplink G2 2019-06-11 c34b LPGBT_TEST Simplified dnlink DG - counter only, zero padding on uplinks where needed (e.g. loopback) G2 2019-06-10 c34a LPGBT_TEST plugged Model dnlink into LpGBT1 data Model uplink set with fixed e-uplink data patterns (0x6030, 6131 etc) moved debug streams around - see twiki G2 2019-06-10 c349 LPGBT_TEST removed unused logic (internal pattgen etc) added Model back in (DP1) added EMORSE 5us hi, lo "linereset" option ec_pattgen changed to "0000000100110111" GLIB 2019-06-10 9348 GBT_IPAM2 EM "resetline" option added G2 2019-06-06 c346 LPGBT_TEST improved ec_pattgen, loopback non-clocking G2 2019-06-06 c345 LPGBT_TEST 1 more fix to dnlink dbg streams again! G2 2019-06-06 c344 LPGBT_TEST [1 more fix to dnlink dbg streams] NOT G2 2019-06-05 c343 LPGBT_TEST fixed dbn stream mapping, bypassed lpgbt-fpga pattgen G2 2019-06-05 c342 LPGBT_TEST Added EC pattgen, and simple loopback G2 2019-06-05 c341 LPGBT_TEST Reworked EC data readout debug channel (added resets too) GLIB 2019-06-05 9341 GBT_IPAM2 EM out on all L0COMs and R3L1s and bugfix G2 2019-06-04 c340 LPGBT_TEST Bug in pattgen decode fixed G2 2019-06-04 c33f LPGBT_TEST_CS Back to RTYP_CAPONLY G2 2019-06-04 c33e LPGBT_TEST_CS Changed dnclk_en to s40 (from 1) G2 2019-06-03 c33d LPGBT_TEST_CS EM(14) on EC. RTYP_130M. Model on DP1 G2 2019-06-03 c33c LPGBT_TEST_CS Test pattern on EC downlink. + A little CS added. Model on DP1 NV 2019-06-03 b33c FDP_STAR_CS More CS lines added NV 2019-05-31 b33b FDP_STAR_CS BIGMEM sequencer testing G2 2019-05-31 c33b LPGBT_TEST Includes Model on DP1. 2 e-links only (links 0,1). CAPONLY NV 2019-05-19 b33a FIB_PPA Register defaults can be updated based on BUILD - for non-star builds reg 16 defaults back to 0x9801 NV 2019-05-19 b339 FIB_PPA Finally spotted the stupid stupid bug NV 2019-05-18 b338 *FIB_PPA Maybe this one will actually have data-links! [Nope :-(] NV 2019-05-17 b337 *FIB_PPA Passive Petal adapter version is born! G2 2019-05-14 c336 GBT_ST13S_2GBT_HTG_H Histo added G2 2019-05-14 c335 GBT_ST13S_2GBT_HTG Use MGT REFCLK from HTG (now that we can program it!) G2 2019-05-13 c334 GBT_ST13S_2GBT_HTG Core CORECTL mapping G2 2019-05-13 c333 GBT_ST13S_2GBT_HTG Rebuild with latest GLIB fixes GLIB 2019-05-10 9333 GBT_ST13S_2GBT bugfix in trigger top in 130 mode + further bugfix in RX GLIB 2019-05-10 9332 GBT_ST13S_2GBT bugfix in RX stream pre-decode/map G2 2019-05-09 c331 GBT_ST13S_2GBT Nuther go ... GLIB 2019-05-08 9331 GBT_ST13S_2GBT bugfix from prev ver: rawsigs triggers no longer ignored GLIB 2019-05-08 9330 GBT_ST13S_2GBT RAWSIGS mapping changed for segmented objects - see twiki TX mode 320 now a single bit per GBT (GBTCORE_CTLn register) RX mode 320 governed by stream-config reg G2 2019-05-02 c32f LPGBT_TEST Test pattern on EC G2 2019-05-02 c32e LPGBT_TEST 14 links per LPGBT only G2 2019-05-01 c32d LPGBT_TEST ICEC on links 64-67 G2 2019-05-01 c32c LPGBT_TEST back to real uplink data only, added IC, and EM on EC Removed Eths and LpGBT-Model G2 2019-04-30 c32b LPGBT_TEST_FRM Added reg config of options - like scrambler bypass. G2 2019-04-30 c32a LPGBT_TEST_FRM resets structure changed, lots more debug stat bits AAAAND Carlos I2C C/D li lines swapped :-) G2 2019-04-30 c329 LPGBT_TEST_FRM dn/upframes connected as data G2 2019-04-27 c328 LPGBT_TEST Test build2 with I2C -> Carloa FMC conn (untested) G2 2019-04-26 c327 LPGBT_TEST Test build - but links are somewhat connected G2 2019-04-26 c326 GELIX GELIX build (with reduced Eth FIFOs) GLIB 2019-04-25 9326 GBT_ST13S_2GBT re-enabled 320Mb TX option GLIB 2019-04-25 9325 GBT_ST13S_2GBT Added GBT0,1 COM enable via OUTSIGS reg GLIB 2019-04-25 9324 GBT_ST13S_2GBT Added links 26,27 to the build. G2 2019-04-24 c324 GBT_ST13S_2GBT test build NV 2019-04-16 b323 FIB_STAR_SP01SWAP Special build with SP0 and SP1 swapped NV 2019-04-16 b323 FIB_AMAC2_SP01SWAP Special build with SP0 and SP1 swapped GLIB 2019-04-08 9321 GBT_ST13S_2GBT Removed stuff from GBT core - it may work! - large buffs too. G2 2019-04-04 b31f FDP_STAR Re-build to grab trigger fix from b31c GLIB 2019-04-04 931e GBT_ST13S_2GBT Smaller link FIFOs - see streamstat word 1(9:8) GLIB 2019-04-04 931d GBT_ST13S_2GBT_MINI Missing links 8-15 per GBTx (links masks=0x3ff00ff) NV 2019-04-03 b31c FIB_STAR Ext/TLU trig connected to LCB-L0-gen. ALSO: From now on only lowest 3 bits of OUTSIGS reg used GLIB 2019-04-02 931b GBT_ST13S_2GBT_MINI NOT ALL STREAMS Used all OPHASEB across the 2 GBTs. GBT0 32,10 GBT1 76,54. Ditto INVERTS GBT0 11:8, 3:0; GBT1: 15:12, 7:4. G2 2019-04-02 c31a GBT_ST13S_HTG As below with HTG control lines as outputs G2 2019-04-02 c318 GBT_ST13S_HTG Trying GBTCLK0 + Added 120MHz clock out to HTG-FMC CLK2 ... + Fixed HTG clk sel error G2 2019-04-01 c317 FIB_STAR Fixed stream_reg not connected to DIO bug G2 2019-04-01 c316 GBT_ST13S Trying no LVDS_25/DIFF-TERM on MGT clock in G2 2019-03-29 *c315 GBT_ST13S Added control lines for HTG-FMC-4x-SFP clocks G2 2019-03-29 c314 GBT_ST13S Added dedicated HTG-FMC-SFP Osc I2C on TWOWIRE(14) NV 2019-03-29 b313 FDP_STAR Fixed EM TX = 1 bug G2 2019-03-29 c312 GBT_ST13S Added GBT-SC-IC RX/TX bitswap options reg(GBT_CONTROL)(13:12) G2 2019-03-29 c311 GBT_ST13S Fixed possible bug in GBT-SC core ... G2 2019-03-28 c310 GBT_ST13S Added more of OCB_SC GLIB 2019-03-28 930f GBT_ST13S_2GBT 2 GBT version, no histo. NV 2019-03-28 b30f FIB_STAR Added inputs on J6 to loopback monitor BTC/BCO, LCB, R3L1 G2 2019-03-28 c30f GBT_ST13S Fixed FMC_LA to/downto mismatch. Note this build includes IC/EC... NV 2019-03-27 b30e FDP_STAR LEMO trig in option added - use reg 18.(15:14) NV 2019-03-27 b30d FDP_STAR All FMC options in sub-block G2 2019-03-27 c30c FIB_STAR Added UDP G2 2019-03-26 c30b FIB_STAR Added missing signals to FMC block G2 2019-03-26 c30a GBT_ST13S Proper GBT build .... hmmmm G2 2019-03-26 c309 FIB_STAR USE_GBT_CLKS via signal, not generic (otherwise same as vc308) G2 2019-03-26 c308 FIB_STAR First go, seems okay (not!) G2 2019-03-23 c306 GBT_TEST Trying the other MGTCLK (it worked! GBT is up) G2 2019-03-22 c305 GBT_BERT G2 2019-03-22 c304 GBT_TEST DYNAMIC mode enabled, GBT-FPGA internal DG removed G2 2019-03-22 c303 GBT_TEST Will no CS revive net i/f? G2 2019-03-21 c302 *GBT_TEST_CS CS version (n/w interface dead!!!) G2 2019-03-20 c301 GBT_TEST ignoring rx_ready G2 2019-03-19 c300 GBT_TEST Found a little change of in new wrt CGA (mea culpa) G2 2019-03-19 c2ff GBT_TEST Sorted out some reset fluxups created when moding for Modelsim G2 2019-03-19 c2fe GBT_TEST Added pattgen back into build ... G2 2019-03-18 c2fd GBT_TEST Fixed up some unconnected signals G2 2019-03-12 c2f6 GBT_TEST Moved GBT control reg to 62 (GBT_CORECTL0) NV 2019-03-12 b2f5 FDP_STAR Inverted LCB too (Bruce said so!) G2 2019-03-12 c2f4 GBT_TEST TX vs RX ready fix NV 2019-03-12 b2f3 FDP_STAR Inverted EM_TX at out - no more need to invert at source G2 2019-03-12 c2f2 GBT_TEST Fixed rx=tx bug NV 2019-03-06 b2eb FSC_STAR_HPC Hardware mods for HCC Probe Card ONLY NV 2019-03-06 b2e9 FDP_STAR Accounted for EM TX being inverted pre-OR of (3:0) GLIB 2019-02-28 92e8 GBT_ST13S Option to switch ext trig sources - see reg 33 NV 2019-02-27 b2e7 FDP_STAR Uninverted the Ds. Inverted the BCOs. May match sch now.... NV 2019-02-27 b2e6 FSC_STAR FSC with 8b10b decoder included (aka HCC ISER mode) now matches FIB ver. NV 2019-02-26 b2e5 FDP_STAR First FDP (FMC-0514) build GLIB 2019-02-25 92e4 GBT_ST13S UDP version GLIB 2019-02-25 92e3 GBT_IPAM2 Adding UDP again GLIB 2019-02-25 92e2 GBT_IPAM2 IPAM2 rebuild GLIB 2019-02-24 92e1 GBT_ST13S GLIB bugfix done right! GLIB 2019-02-18 92e0 *GBT_ST13S GLIB bugfix in net part GLIB 2019-02-15 92df *GBT_ST13S GLIB build update to current. But NO HISTO or UDP NV 2019-02-15 b2de FIB_STAR Improved end of oc handling (no more missing last word!) NV 2019-02-15 b2dd FIB_STAR Separated addr, data write citeria NV 2019-02-14 b2dc FIB_STAR Address incrementing in steps of 16 ... NV 2019-02-14 b2db FIB_STAR Second go - this time with address incrementing in steps 8 NV 2019-02-14 b2da FIB_STAR First go with DDR and new BIGMEM_WR/RD opcode NV 2019-02-11 b2d9 FIB_STAR Removed inserted zeros to pad blocks when data not valid in Cap2 NV 2019-02-08 b2d8 FIB_STAR Improved 0 opcode check, DDR example design added NV 2019-02-08 b2d7 FSC_STAR FSC version NV 2019-02-08 b2d6 FIB_STAR Removed 0 opcode check NV 2019-02-08 b2d5 FSC_STAR FSC version NV 2019-02-08 b2d4 FIB_STAR Hopefully fixed a silly bug with generics etc. NV 2019-02-07 b2d3 FCS_STAR Inverted DataOut 8 - fixies HCC SCB swap NV 2019-02-05 b2d2 FIB_STAR Attempt to fix very old zero opcodes in a packet bug NV 2019-02-05 b2d1 FIB_STAR Fixed StrmConf mapping bugs NV 2019-02-05 b2cf FIB_STAR ABC Cap2 improved. Better handling of mode changes. Added second datagen to D1 (conf via reg(DG1_CONF) NV 2019-02-04 b2ce FIB_STAR StrmConfs applicabilty fixed (Strm 0 8b10b_en, 320_en was used for all) NV 2019-02-02 b2cd FIB_STAR Cap2 missing SoF in back to back conditions fixed NV 2019-02-02 b2cc FIB_STAR FIB version NV 2019-02-01 b2cb FSC_STAR Much improved Cap2 for HCC encoded data Also syscon is good state. See twiki for details NV 2019-01-28 b2c7 FIB_STAR_1 1 stream build, trying to get syscon going better NV 2019-01-25 b2c2 FIB_STAR Trying out a little uart interface NV 2019-01-25 b2c1 FIB_STAR Updated patt gen with HPR packet. fixed invert makes cap2 in abc bug NV 2019-01-24 b2c0 FIB_STAR Added Ash test stand-alone options - push btnL and it writes to HCC reg enabling outputs Changed default LCB OPHASE to 1 (was 0) NV 2019-01-23 b2bf FSC_STAR Fixed inverted data! (it mostly works inverted in 8/10b!!) NV 2019-01-23 b2be FSC_STAR FSC version NV 2019-01-23 b2bd FIB_STAR Cap2 does 8b/10b - but not perfectly methinks NV 2019-01-21 b2bc FSC_STAR FSC version NV 2019-01-21 b2bb FIB_STAR Added TS before Cap2 data, but only if FIFO is idle NV 2019-01-21 b2ba FIB_STAR FIB version NV 2019-01-21 b2b9 FSC_STAR Same as below, but correct version this time NV 2019-01-21 b2b8 FSC_STAR Capture2 opcode fixed (says it's vb2a7 aaaaargh!) NV 2019-01-19 b2b7 FIB_STAR HCC mode raw mode ISERDES nibble reversed NV 2019-01-18 b2b4 FIB_STAR HCC mode enabled! NV 2019-01-18 b2b3 FSC_STAR FSC build NV 2019-01-18 b2b2 FIB_STAR Fixed ABC datagen data NV 2019-01-17 b2b1 FIB_STAR More debug outputs - almost all of J0. Fixed DG inverts NV 2019-01-16 b2b0 FSC_STAR FSC ditlo NV 2019-01-16 b2af FIB_STAR Cap2 fixed. Pattgen improving NV 2019-01-15 b2ae FIB_STAR Really added the datagen this time NV 2019-01-15 b2ad FIB_STAR Added datagen on J6 D0 (rest of J6=in: i.e connect J5-J6 with 50-way cable) NV 2019-01-15 b2ac FSC_STAR FSC: abc_mode hardwired NV 2019-01-15 b2ab FIB_STAR abc_mode hardwired - NOTE: reports vb2aa again :-( NV 2019-01-15 b2aa FIB_STAR FIB!! Similar to FIB_AMAC2. Only has J5 links (0-6) in build. NV 2019-01-14 b2a9 FSC_STAR Non-HCC - extra bit to get Data10 driven by disabling SCMD, SFCMD NV 2019-01-14 b2a8 FSC_STAR HCC-deser trial - ABC mode (aka no 8b/10b etc) should still work NV 2019-01-14 b2a7 FSC_STAR Non-HCC - set the ABC bit in StrmConfig too! NV 2019-01-11 b2a6 FSC_STAR Non-HCC input + Corrected HCC DATA 3,4,5,8,9,10 mappings NV 2019-01-11 b2a5 FSC_STAR Non-HCC input + Data0 to Data2-Data10 MUX (reg 16(15:12)) NV 2019-01-10 b2a4 FSC_STAR Added Capture2 and friends (not fully tested) NV 2019-01-09 b2a3 FSC_STAR Re-worked link code for future (welcome "xlink") Should be no change to functionality (fingers crossed) NV 2019-01-08 b2a2 FSC_STAR Enabled HCC input de-serialiser etc. (Montreal mode!) NV 2019-01-07 b2a1 FSC_STAR Fixed SEQ_PATTERN timing NV 2018-12-13 b2a0 EMU_ABCSTAR Making EMUs great again GLIB 2018-12-13 929f GBT_IPAM2 Build for controlling AMACv2s connected to an Interposer/TestVehicle (1 link only) NV 2018-12-07 b29e FSC_STAR Added RCLK320 mode to CCR_CTL reg NV 2018-12-07 b29d FSC_STAR Using non-DPA/HCC-decoder deser NV 2018-12-07 b29c FSC_STAR hcc_mode now enables auto NV 2018-12-05 b29b FSC_STAR Fixed SEQ_PATTERN operation NV 2018-12-05 b29a FSC_STAR Added FusePP 200us pulser via COMMAND2(15) NV 2018-12-04 b299 FSC_STAR 8b10b decoder AGAIN - this time with it in the build ;-) NV 2018-11-28 b298 FSC_STAR trying 8b10b decoder NV 2018-11-28 b297 FSC_STAR Added datains and second seq, and R3L1 NV 2018-11-28 b296 FSC_STAR First go with HCC sigs + Seq fixed NV 2018-11-30 b295 FSC_STAR * Data0 mapped to seqs(15:14) NV 2018-11-29 b294 FSC_STAR more sigs mapped to both LEMOs NV 2018-11-28 b293 FSC_STAR changed COM_ENA/CCR_CTL map NV 2018-11-28 b292 FSC_STAR Added seq_pattern start address: reg 30 NV 2018-11-28 b291 FSC_STAR More enable bits, depricateds too - see twiki! NV 2018-11-28 b290 FSC_STAR added lbc_en: reg16.0, fixed 320 readout, started on hcc code (disabled) NV 2018-11-27 b28f FSC_STAR fxied missing streams bug NV 2018-11-26 b28d FSC_STAR fixed strm_stat_rd bug (introduced in 28c) NV 2018-11-26 b28d FSC_STAR Test with IBUF_DIFF ... NV 2018-11-26 b28c FSC_STAR back to auto swLCB (i.e no more RAWSEQ(14) enable as per below) NV 2018-11-23 b28b FSC_STAR RAWSEQ(14) enables swLCB now, and fixed LCB align bug NV 2018-11-23 b28a FSC_STAR slight change to raw lcb handling NV 2018-11-23 b289 FSC_STAR Added outgoing sigs as input streams 16-19 NV 2018-11-22 b288 FSC_STAR Added output sigs debug too (LEMO_STRM 16-19) NV 2018-11-22 b287 FSC_STAR Inverted inverted links. Stream numbers in again too :-) NV 2018-11-22 b286 FSC_STAR LEMO_STRM works (but on links, not strms) NV 2018-11-22 b285 FSC_STAR All ins mapped to readout this time NV 2018-11-22 b284 FSC_STAR All ins mapped NV 2018-11-22 b283 FSC_STAR All ins mapped NOT NV 2018-11-21 b282 FSC_STAR Swapped chan 8 i2c pair NV 2018-11-21 b281 FSC_STAR struct change, disp on, temp readout, tw_present ... NV 2018-11-21 b280 FSC_STAR Fixed FASTDIO bug NV 2018-11-20 b27f FSC_STAR With readout stream included this time! NV 2018-11-20 b27e FSC_STAR * Proper ABCStar build (LEMO0 = DataIn, LEMO1 = RAWSEQ(15)) NV 2018-11-19 b27d EMU_ABCSTAR_CS Fixed stuck after one packet bug :-) Seems very happy now - lots of HPRs NV 2018-11-18 b27c EMU_ABCSTAR_CS Packet decoder works - new format see twiki https://twiki.cern.ch/twiki/bin/view/Atlas/ITSDAQDataFormat130#ABCStar%20Sub-Block NV 2018-11-16 b27b EMU_ABCSTAR_CS Added packet decoder (untested!!) + changes to link org code which may add bugs ... NV 2018-11-06 b27a FSC_LOOP re-build with rewritten lost code :-( also has S40 fix etc NV 2018-11-16 b279 EMU_ABCSTAR_CS Fixed missing S40 and got display going again NV 2018-11-08 b278 FSC_LOOP Fixed badly setup streams and missing serout(0) NV 2018-11-07 b277 FSC_LOOP First FSC_LOOP build NV 2018-11-04 b276 EMU_ABCSTAR_CS Corrected RAWSIGS timing too. NV 2018-11-04 b275 EMU_ABCSTAR_CS Corrected RAWSEQ timing. NV 2018-11-02 b273 EMU_ABCSTAR_CS Added more CS to understand SEQ timing NV 2018-11-02 b272 EMU_ABCSTAR_CS Added lcb_raw onto RAWSEQ/SIGS(9:8) -- send msbs first, msb first. e.g 0x7855: 01 11 10 00 01 01 01 01 NV 2018-11-02 b270 EMU_ABCSTAR_CS Added LP/PR on RAWSEQ/SIGS(4) NV 2018-11-02 b26f EMU_ABCSTAR_CS Added rawseq/sigs 10MHz sync - used to gen LCB too NV 2018-10-22 b26d EMU_ABCSTAR_CS Serial control test version: use RAWSEQ/SIGS: 0=l0a, 1=bcrf, 2=fcmd, 3=cmd Send sigs at 40Mb, Data at 80Mb (RCLK = 80MHz). CHIPID=2 cmd: 10111110, a/h(1), hid(4), RnW, aid(4), ad(8), [dat(32)] fcmd: 1010, fcmd_delay(2), fcmd_word(4) NV 2018-10-20 b26c EMU_ABCSTAR First go ... NV 2018-10-18 Added stat 52 - TWOWIRE port present indicator NV 2018-10-02 b26b FIB_STD_H Update NV 2018-09-26 b26a FDM_DECAL Used rawsigs(15) to trigger capture instead of trig 9269 Complete reworking of readout block gen to operate at Link level (was Module) Many changes to how code is generated - ripe for bugs. 9268 Changed to record for stream data (interim update) GLIB 2018-09-12 9267 GBT_ST13S_H 1st segmented version. See new OUTSIGS option and slight RAWSIGS remap GLIB 2018-09-12 9266 GBT_ST13S_H Updated with latest fixes (see below) NV 2018-09-12 b266 FIB_AMAC2_H ditlo Atlys 2018-09-12 a266 VADAPT_AMAC_H Added capt-starts counter (status 35) Spy really reduced to 8b per stream NV 2018-09-11 b262 FIB_AMAC2_H J0 I2C mapping changed to match FIB_STD but Spy broken NV 2018-09-10 b260 FIB_AMAC2_H Spy reduced to 8b per stream (BW issues) and 0x40 order changed (see twiki) Atlys 2018-09-07 a25e VADAPT_AMAC_H ditlo (EMU_AMACv2 remains removed) NV 2018-09-07 b25e FIB_AMAC2_H Added spy for ABC130 (at last) see SPYSIG_CTL reg twiki entry Added L1Auto driven from DTRIG1 option (reg 23.6) Atlys 2018-09-05 a25c VADAPT_AMAC_H ditlo (EMU_AMACv2 remains removed) NV 2018-09-05 b25c FIB_AMAC2_H Fixed n packets in FIFO counter overflow bug In high BW conditions, a packet gets "held" in the f/w NV 2018-09-05 b25b FIB_AMAC2_H Fixed first time stream enabled spurious packet Atlys 2018-09-04 a259 VADAPT_AMAC_H ditlo (EMU_AMACv2 remains removed) NV 2018-09-04 b259 FIB_AMAC2_H Reset detect activated for RTYP_130M setups Attempted to fix spurios packet after boot (datagen) Changed datgen rollover value to aid merged debug NV 2018-09-03 b258 FIB_STD_H Rebuilt sans AMACv2 Atlys 2018-09-03 a257 VADAPT_AMAC_H ditlo + removed EMU_AMACv2 NV 2018-08-03 b257 FIB_AMAC2_H Reduced AMAC response timeout to 200-250us Atlys 2018-08-15 a256 VADAPT_AMAC_H ditlo NV 2018-08-15 b256 FIB_AMAC2_H Improve EM startup and flow. Neg-glitch handling. Default A2F=1 handled better (although data will be flagged as error) Atlys 2018-08-14 a251 VADAPT_AMAC ditlo NV 2018-08-14 b254 FIB_AMAC2 Reworked EM code a little - improved SM structure and logic Long gap now added pre-TX always. RX disabled during send, but active immed. after Better anti-glitch (ignores spurios 0's and 1's now) AND EM Inverts now split between TX (reg 49) and RX (reg 50) NV 2018-08-13 b252 FIB_AMAC2 Extra EM state checks - trying to get rx and tx not to clash Atlys 2018-08-13 a251 VADAPT_AMAC ditlo NV 2018-08-13 b251 FIB_AMAC2 reverted rising edge change, added reset em decoder at start of transaction Atlys 2018-08-13 a250 VADAPT_AMAC_H ditlo NV 2018-08-13 b250 FIB_AMAC2_H Added EM input rising edge detect (i.e. stuck at 1 won't do anything) NV 2018-08-07 b24f FIB_AMAC2_H Added map D3 instead of D7 for EM as per a24d NV 2018-08-07 b24e FIB_AMAC2_H Uninverted EM lines and swapped J5/6 I2C CL/DA lines (And remapped J5/6 I2C to chan 0, 2) Atlys 2018-08-07 a24d VADAPT_AMAC_H Invert option for em channels (reg 49). Option to use D3 instead of D7 for EM RX (reg 23.5) NV 2018-08-07 b24c FDM_DECAL DIFFTERM back to false. NV 2018-07-27 b24b FDM_DECAL_TERM DIFFTERM=true! And really fixed missing clk problem, Set term-on via option in pkg GLIB 2018-08-02 924a GBT_ST13S_H added Ext trig on FMC-IB D0 pins (P:ext0 N:ext1) Atlys 2018-07-27 a249 VADAPT_AMAC_H AMAC on Atlys. + ABC130 (on links 0-3 (streams 0-7)) NV 2018-07-27 b247 FDM_DECAL Fixed missing constaint on fmc_clk0_m2c (pllclk) NV 2018-07-25 b245 FIB_AMAC2_H Added deglitcher for serialin, and lengthened BITGAP_MAX NV 2018-07-25 b244 *FIB_AMAC2_H (re)added full quiecent time at end of recieves NV 2018-07-25 b243 *FIB_AMAC2_H Longer QUIESCENT value in endeavour_master ^^^^^^^^^^^^^^^^^^ Vivado 2017.4.1 from now on ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ NV 2018-07-24 b242 FDM_DECAL First Vivado DECAL build NV 2018-07-24 b241 FIB_AMAC2 AMAC2 with most of FIB_STD GLIB 2018-07-20 923d *GBT_ST13S_H added clk crossing rx fifo. GBT1 only build. Atlys 2018-07-12 a23b IDC130_TTC_H RAWSEQ can drives streams and be triggered GLIB 2018-07-13 923b GBT_ST13S_H GBT1 only. GLIB 2018-07-12 923a GBT_ST13S No histo. GBT1 only. GLIB 2018-07-12 9238 GBT_ST13S_H Ditlolo Atlys 2018-07-12 a238 IDC130_TTC_H Ditlo NV 2018-07-12 b238 FIB_IDCONLY_H Larger Stream FIFO, ^^^^^^^^^^^^^^^^^^ Everything is MERGED from now on (except DECAL) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^ All NV builds have TLUTCC from now on (except DECAL) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ GLIB 2018-07-10 9237 GBT_ST13S_H_MERGED GBT1 only ATLYS 2018-07-06 a237 IDC130_TTC_H_MERGED Additional Datagen set CHIPID option added ATLYS 2018-07-09 a236 IDC130_TTC_H_MERGED GLIB 2018-07-09 9236 GBT_ST13S_H_MERGED Histo in now (GBT1 only) GLIB 2018-07-09 9235 GBT_ST13S_MERGED like below but works ;-) GLIB 2018-07-06 9234 GBT_ST13S_MERGED Odd/even streams merged. GBT1 only ATLYS 2018-07-06 a234 IDC130_TTC_MERGED Odd/even streams merged. GLIB 2018-07-03 922f GBT_ST13S_MERGED Both GBTs in the build 1st all links(0-27), 2nd links 12-23 only NV 2018-06-28 b22e FIB_STD_TLUTTC_H TWOWIRE with delays - control word: sck (11:10), sda (9:8) see twiki GLIB 2018-06-28 b22d GBT_ST13S Both GBTs in the build 1st all links(0-27), 2nd links 0-15 only GLIB 2018-06-27 b22c GBT_ST13S Connected the TX - that should help ;-) GLIB 2018-06-26 b22b GBT_ST13S Current code with remapped GLIB/GBT files and fixed TTC mapper GLIB 2018-06-26 b22a GBT_ST13S Another rebuild of v9201 with unmapped TX elinks set to 0. GLIB 2018-06-25 b229 GBT_ST13S Rebuild of v9201 with the 1 ttc pair mapped to all TTC segments and TWOWIRE to FMC added GLIB 2018-06-25 b228 GBT_ST13S Same again with L0COM on ALL TX elinks! GLIB 2018-06-25 b227 GBT_ST13S Rebuild pre TTC expand but with TWOWIRE GLIB 2018-06-25 b226 GBT_ST13S Fix REG_GBT2_ETX/ERX used for GBT1 too bug GLIB 2018-06-22 b225 GBT_ST13S Added TWOWIRE to FMC1+FMC-IB/J0 (right/forward FMC) NV 2018-06-07 b224 FIB_STD_TLUTTC_H Un-fixed fixed pinmap NV 2018-06-07 b223 FIB_STD_TLUTTC_H Uninverted all TLU signals NV 2018-06-07 b222 FIB_STD_TLUTTC_H Inverted all TLU signals NV 2018-06-07 b222 FIB_STD_TLUTTC_H Fixed TLU pin map ATLYS 2018-06-05 a221 IDC130_TTC_H Update to latest everything (except UDP) NV 2018-06-04 b220 FIB_STD_TLUTTC Test build with its_protocol block to abstract net protocol from MAC NV 2018-06-01 b21f FIB_SOIE_TLUTTC_H Soie version NV 2018-05-31 b21e FIB_STD_TLUTTC_H Full build, should work. Note will auto switch to UDP, but not back to Raw :-( NV 2018-05-27 b21d FIB_IDCONLY_TLUTTC_H Auto switch responses regardless of mode NV 2018-05-26 b21c FIB_IDCONLY_TLUTTC_H* combined Raw + UDP again ... (ARP failed, doh) NV 2018-05-26 b21b FIB_IDCONLY_TLUTTC_H Raw only test version with TREADY=1 always NV 2018-05-25 b21a FIB_IDCONLY_TLUTTC_H Raw only test version GLIB 2018-05-19 9214 GBT_ST13S OC bugfix GLIB 2018-05-18 9213 GBT_ST13S All TTC segments driven from common L0C/L1R - note using OPHASEB10/32 not OPHASE NV 2018-05-09 b210 FIB_STD_TLUTTC_H Full version. Even has UDP option NV 2018-05-09 b20f FIB_IDCONLY_TLUTTC Changed polarity of sw7 action: now dn=RawEth, up=(test)UDP NV 2018-05-09 b20e FIB_IDCONLY_UE Both UDP and RawEth - uses sw7 to select NV 2018-05-02 b20d FIB_STD_UDP_D More links for throughput testing NV 2018-05-01 b20c FIB_IDCONLY_UDP UDP event data now working NV 2018-04-29 b209 FIB_IDCONLY_UDP_D More Debug added NV 2018-04-28 b208 FIB_IDCONLY_UDP_D UDP with Xilinx Debug (nee chipscope) in the build NV 2018-04-27 b207 FIB_IDCONLY_UDP UDP Test - Corrected data format (i.e. v.203 is useless) NV 2018-04-24 b203 FIB_IDCONLY_UDP UDP Test GLIB 2018-04-05 9201 GBT_ST13S ALL streams this time, but no histo - it's too big :0 GLIB 2018-04-04 9200 GBT_ST13S_H GBT build with even streams on GBT1 enabled GLIB 2018-04-04 91ff GBTSTIB_TGRW_H (back to old stream fifo) GLIB 2018-03-26 91fc GBTSTIB_TGRW_H_CS GBTSC chipscope debug (new stream fifo) NV 2018-03-21 b1fb FIB_SOIE_H Updated GBTSC test setup. Also has link 3. GLIB 2018-03-20 91fa GBTSTIB_TGRW_H GBTSC EC seems to be up and running. Note loop back is not good, but link 3 will answer with some data - see twiki. GLIB 2018-03-19 91f9 GBTSTIB_TGRW_H Added linkID setting to ocb_gbtsc. GLIB version has 1,2 GLIB 2018-03-19 91f8 GBTSTIB_TGRW_H First go at GBTSC *EC* GLIB 2018-03-12 91f7 GBTSTIB_TGRW_H This version is missing the first GBTSC-IC data word. not sure if tx or rx issue NV 2018-03-12 b1f7 FIB_SOIE_H Working on GBTSC still GLIB 2018-03-09 91f5 GBTSTIB_TGRW_H Hopefully fixed GBTSC code - include loopback option - see reg GBT_CONTROL,14 NV 2018-03-09 b1f4 FIB_SOIE_H Fixed dtack wired-or bug (AGAIN!!) GLIB 2018-03-08 b1f3 GBTSTIB_TGRW_H IC loopback test. NV 2018-03-02 b1f0 FIB_SOIE_H * GLIB 2018-03-08 91f1 GBTSTIB_TGRW_H Fixed proper version of OC_GBTSC, connected to GBT1 (of GBT1,2) - might even work GLIB 2018-03-04 91f0 GBTSTIB_TGRW_H Proper version of OC_GBTSC, connected to GBT1 (of GBT1,2) - might even work NV 2018-03-02 b1f0 FIB_IDCONLY_H * Really fixed OC_GBTSC in loopback mode for testing NV 2018-03-01 b1ef FIB_IDCONLY_H Fixed OC_GBTSC in loopback mode for testing NV 2018-03-01 b1ed FIB_IDCONLY_H Added OC_GBTSC in loopback mode for testing (failed) GLIB 2018-02-28 91ed GBTSTIB_TGRW_H First build with new OC_GBTSC ATLYS 2018-02-20 a1ec DRV_TTC Updated TWOWIRE with more speeds NV 2018-02-08 b1e9 FIB_STD_H - ATLYS 2018-02-08 a1e9 IDC130_TTC_H Added Sys Default MAC Set opcode (0xF2 and wrong dest mac packet drop ATLYS 2018-02-06 a1e5 IDC130_TTC_H - NV 2018-02-06 b1e5 FIB_STD_H MAC words reversed properly this time! NV 2018-02-05 b1e4 FIB_STD_H MAC words reversed NV 2018-02-05 b1e3 FIB_STD_H Default MAC may actually work this time ... ATLYS 2018-01-26 a1e1 IDC130_TTC_H Default MAC in SysRegs - see twiki NV 2018-01-26 b1e0 FIB_STD_H Added SysRegs for programming default MAC - see twiki ATLYS 2018-01-24 a1de IDC130_TLU_H MAC routing build NV 2018-01-23 b1dd FIB_STD_H Bugfix NV 2018-01-23 b1dc FIB_STD_H Alternative default MAC approach: first-come is-default NV 2018-01-23 b1db FIB_STD_H No more net-acks NV 2018-01-23 b1da FIB_STD_H ^^^^ 2 0 1 8 ^^^^ NV 2017-12-13 b1cc FDM_DECAL ISE build - added frmclockperiph + enables in reg ATLYS 2017-12-11 a1c9 CHESS2B_TLU Special version for Luigi with TLU enabled by default - And signals echoed on VMOD-CHESS2 debug outs NV 2017-12-08 b1c8 FDM_DECAL Added debug outputs on PMOD JC, Viv build NV 2017-12-04 b1bf FIB_STD_H Trying less complicated constraints NV 2017-12-01 b1bd FIB_STD_H Build after moving all fmc files to own lib GLIB 2017-12-01 91bc GBTSTIB_TGRW_CS Changed bitgen StartUpClk to JtagClk for djtgcfg use NV 2017-11-29 b1bb FIB_STD_H VIVADO BUILD! And it seems to work (only the net connect checked tho) NV 2017-11-28 b1ba FDM_DECAL Clock really changed to 20MHz SQUARE WAVE!!, frmclk = 40MHz now NV 2017-11-27 b1b7 FDM_DECAL Clock changed to 20MHz, added frameclock at same freq too GLIB 2017-11-27 91b8 GBTSTIB_TGRW_CS More chipscope signals and more depth NV 2017-11-10 b1b4 FDM_DECAL Auto phase operational NV 2017-11-10 b1b3 FDM_DECAL Capture mode operational NV 2017-11-08 b1b2 FDM_DECAL First DECAL build ATLYS 2017-11-06 a1b1 VADAPT_TTC GLIB 2017-11-02 91af GBTSTIB_TGRG_CS Added chipscope on SC signals GLIB 2017-11-02 91ae GBTSTIB_TGRG Set to FEC mode on both RX and TX GLIB 2017-11-01 91ad GBTBERT_TGRW GLIB 2017-11-01 91ac GBTSTIB_TGRW Fixed reg/stat read missing last word bug ATLYS 2017-10-25 a1a9 ABCN_TTC_PTRGO Down button sends a PAUSE packet. Hopefully ... GLIB 2017-10-24 91a9 GBTSTIB Moved build dir and project to trunk/ise/glib_itsdaq Lots of path, softlink etc changes for rational building Also enabled histo NV 2017-10-23 b1a7 FLOOP640_SPL FIB Loop special - Rebuild with ONLY 1 link in the build GLIB 2017-10-23 91a8 GBTSTIB Refresh build to check all still works (in my head too!) NV 2017-10-20 b1a6 FLOOP640_SPL FIB LOOP special - Only has a 640 counter on ser 0 ATLYS 2017-10-20 a1a5 ABCN_TTC_PTRGO Removed RAWCOM from com_decoder ATLYS 2017-10-20 a1a4 ABCN_TTC_PTRGO Added abcn command decoder to extract trigs from RAWSIGS and RAWCOM ATLYS 2017-10-12 a1a3 ABCN_TTC_PTRGO Improved CMDTRIG timing when DELAY=0 ATLYS 2017-10-12 a1a2 ABCN_TTC_PTRGO ABCN PTrigOut ATLYS 2017-10-12 a1a1 IDC130_TTC_PTRGO_H Special build for Dennis to play with shortish pulses out of PMOD-TTC NV 2017-10-05 b1a0 F2V_STD2_H (+TLU) Build for James to see ... ATLYS 2017-10-03 a19f IDC130_TTC_H Added build info to status 36: (15:8) RO_TYPE, (7:0) DIO_TYPE ATLYS 2017-09-08 a19e IDC130_TTC_H Refresh NV 2017-08-30 b19d FIB_SOIE_H SOIE version with the extra TTC NV 2017-08-29 b19c FIB_STD_H More TTC ports, via OUTSIGS: J5: STT, J6:STB, J0:ID0 (note OPHASE is still common to all) NV 2017-08-18 b19b FIB_STD_H Refresh with histo NV 2017-07-27 b199 FIB_STD Refresh for FIB_STD. Good build! NV 2017-07-27 b198 FIB_IDCONLY Added reset stream seqid command NV 2017-07-26 b197 FIB_IDCONLY IDC L0COM/L1R3 o/ps un-inverted, IDC o/ps now port 7 - matches SOIE NV 2017-07-26 b196 FIB_STD J6 on streams 64-79 (and unchanged J5 0-15, IDC 128-131) NV 2017-07-26 b195 FIB_IDCONLY IDC datas un-inverted (bug fix), and 160 removed NV 2017-07-21 b194 FIB_IDCONLY_H 160MHz clock on "fmc_clk1_m2c" LVDS line (but as output) - for use with FMC105 ATLYS 2017-07-21 a193 DRV_TTC Refresh NV 2017-07-19 b192 FIB_SOIE_H Another TWOWIRE fix NV 2017-07-19 b190 FIB_SOIE_H SOIE build with all the greatest and latest ATLYS 2017-07-19 a191 VADAPT_TTC Refresh NV 2017-07-18 b18f FIB_IDCONLY_H Fixed bug introduced by 18d NV 2017-07-17 b18d FIB_SOIE_H * Added more clocking the ack_gen (aka reply packet gen) NV 2017-07-16 b18c FIB_SOIE_H Alternative iserdes clk_div trial NV 2017-07-15 b18b FIB_SOIE_H Improved twowire (for I2C at least, other modes may be worse :-( ) NV 2017-07-13 b189 FIB_IDCONLY Fixed histo packet len bug NV 2017-07-12 b188 FIB_IDCONLY Raw packet filter option added (see histo reg) NV 2017-07-12 b187 FIB_STD_H Added "all packets" count to v1 histo data NV 2017-07-11 b186 FIB_IDCONLY_H Histogrammer upgrade - data format v1 counters added: num hits, num pkts, pkts dropped etc readout on bin full mode " NV 2017-07-10 b185 FIB_STD Build for this hardware - good luck BNL :-) (and Seqnum fix re-applied) NV 2017-06-21 b184 FIB_SOIE Unfixed SeqNum = 0 bug - Causing too much s/w havocAlso turned off histo to make it build faster NV 2017-06-20 b183 FIB_SOIE_H Moved to OPHASEB for individual phases output bussesSee reg 40-43 NV 2017-06-20 b182 FIB_IDCONLY Quick test - fixed deadness (missed reset) NV 2017-06-20 b181 FIB_SOIE_H Dead NV 2017-06-20 b180 F2V_STD8 Removed strm_reset from FIFO/sender block NV 2017-06-19 b17f F2V_STD8 Changed strm_reset command to be much softer:Will only work if streams are already disabled (or Idle) NV 2017-06-09 b17e F2V_STD8 ATLYS 2017-05-30 a17d IDC130_TLU_H ROTOHRO mode added NV 2017-05-16 b17c FIB_SOIE_H Histo autoreadout mode when data stops flowing > 30us NV 2017-05-16 b17b FIB_SOIE_H com/l1r com output delay control bug fix ATLYS 2017-05-16 a17a IDC130_TLU_H Fixed bug in com/l1r output ATLYS 2017-05-15 a179 VADAPT_TLU_H * ATLYS 2017-05-15 a178 IDC130_TLU_H * Histos on! NV 2017-05-13 b177 FIB_SOIE_H * rebuild NV 2017-05-13 b176 FIB_IDCONLY_H * changed IDC stream numbers to their proper home: 128-131 NV 2017-05-13 b175 FIB_IDCONLY_H * Fixed histo rollover bug, added ramplet mode to datagen NV 2017-05-12 b174 FIB_SOIE_H * Fixed datagen 1BC and histo 1BC and 3BC bugs NV 2017-05-12 b173 FIB_SOIE_H * Removed latches and some unneeded features from clocks gen(Series 7 MMCMs have nice reset inputs) NV 2017-05-11 b172 FIB_SOIE_H * changed to synchro data mux in rouadout block(worsefor FF usage, but we only use 10%!!) NV 2017-05-09 b170 F2V_STD8 Making sure this works for Dennis NV 2017-05-09 b16f F2V_STD2 Making sure this works for Dennis NV 2017-05-08 b16e FIB_SOIE_H Fixed datagen to include chipis in counters NV 2017-05-08 b16d FIB_SOIE_H Added 3BC to histo,fixeddatagen to have internal counter - better at high rates NV 2017-05-04 b16b FIB_SOIE_H Fixed raw needed by histo bug and histoto readout on reset bug NV 2017-05-04 b16b FIB_SOIE_H Histo test - only streams on J6 ATLYS 2017-04-27 a16a VADAPT_TLU TLU build, no other changes ... NV 2017-04-25 b169 FIB_SOIE_H Unswapped SAMTEC I2Cs (for test),UnswapI2C on IDC (because it was wrong) NV 2017-04-21 b168 FIB_SOIE_H Added I2C on FMC-IB J0 (IDC) NV 2017-04-20 b167 FIB_SOIE_H First SOIE build - I2C on 10,11 (Sam J5, J6)Links:Sam J5 19-26, J6 51-58, IDC J0 64-64 NV 2017-04-10 b164 FIB_IDCONLY_H Fixed little datagen bug NV 2017-04-10 b163 FIB_IDCONLY_H INCLUDES basic ABC130 Histogrammer!! GLIB 2017-04-10 9166 GBTSTIB Fixed reversed SC registers bug GLIB 2017-04-10 9165 GBTSTIB Rebuild for sanity GLIB 2017-03-22 9160 GBTSTIB Reconnected SC registers GLIB 2017-03-21 915f GBTSTIB Rebuild with 16 GBT1 links only GLIB 2017-03-20 915e GBTSTIB First go at Peter Staves Interposer (8 + 8 links) NV 2017-03-16 b15c FIB_STAVE Switched SE lines to p side of Samtec (FMC-IB backwards) NV 2017-03-16 b15b FIB_STAVE Tidied some inferred latches in the code - builds faster!(I hope it still works ;-) !) NV 2017-03-16 b15a FIB_STAVE RAL stave with Data 14-26 on J6, with PMODs, I2C on chan 0 GLIB 2017-03-14 9156 GBTBERT TGRW debug - bert 360 sends count + added ophase :-) ++ added longer bert start delay and 1024 match to lock GLIB 2017-03-13 9155 GBTBERT TGRW debug - bert 360 sends count GLIB 2017-03-13 9154 GBTBERT TGRW More Fixes for 320Mb capture, BERT more careful not to lock onto zeros now GLIB 2017-03-10 9153 GBTBERT TGRW Fixes for 320Mb deser (cap only) GLIB 2017-03-10 9152 GBTBERT TGRW Fixes for 320Mb mode GLIB 2017-03-10 9151 GBTBERT TGRW reworked with independent 160 and 320 modes GLIB 2017-03-09 914f GBTBERT TGRW TX=GBT_FRAME, RX=WIDEBUS GLIB 2017-03-09 9150 GBTBERT TGRW Extended BERT pattern - 16B long series of K0,K1 - makes for easier capture decoding GLIB 2017-03-08 914e GBTBERT TGRG TX and RX = GBT_FRAME (aka not WIDE) GLIB 2017-03-08 914d GBTBERT Bug fix - GBTCORE_CTL0 was also GBTCORE_CTL1 GLIB 2017-03-07 914c GBTBERT with 20+20 e-links captured GLIB 2017-03-07 914b GBTBERT playing with GBT core config options, more BERT registers BERT and GBT reg bits MOVED - check wiki. GLIB 2017-03-06 9149 GBTBERT Fixed delay tracking changing data in BERT pipeline GLIB 2017-03-06 9148 GBTBERT GBT TX AND RX to both be WIDEBUS MODE - DOH! GLIB 2017-03-06 9147 GBTBERT Set all TX data to 0xac - more edges GLIB 2017-03-06 9146 GBTBERT Set all TX data to 0x4f - lets see what capt. sees ... GLIB 2017-03-04 9145 GBTBERT fix 5 GLIB 2017-03-04 9144 GBTBERT fixed data pattern GLIB 2017-03-04 9143 GBTBERT Nuther BERT fix GLIB 2017-03-03 913f GBTBERT Fixed no-timeout bug (but still no capture) Offset each TX stream, so distuishable GLIB 2017-03-03 913e GBTBERT Switchable BERT. see GBT_CONTROL reg GLIB 2017-03-03 9141 GBTBERT Capt fix and new BERT algo GLIB 2017-03-03 9141 GBTBERT Added reg controlled GBT1-TX inversion GLIB 2017-03-03 9140 GBTBERT All 4 bert lock/delay status at once GLIB 2017-03-02 913d GBTBERT Switched bert to GBT2, turned TX wide-bus mode off GLIB 2017-03-02 913b GBTBERT GBT1 (of GBT1 and GBT2) polarity flipped GLIB 2017-03-02 913a GBTBERT tester bug fixes ... GLIB 2017-03-02 9138 GBTBERT tester - e-links 28, 30 NV 2017-02-22 b135 FIB_STD With PMODs enabled GLIB 2017-02-22 9137 G_LCBDG LCB data generator GLIB 2017-02-22 9136 GBTTEST Trying no-mux option for data (getting ready for LCB datagen) GLIB 2017-02-22 9133 GBTTEST Made TX dependent on rxReady - cleans up bad e-links GLIB 2017-02-22 9132 GBTTEST Removed more SC stuff, elinks f000f on both GBTs GLIB 2017-02-21 912f GBTTEST disabled SC1 status - still only link-1 working GLIB 2017-02-21 912e G_ST130 GBT Stave build - L0COM/L1R3 over 160Mb e-links etc - seems good GLIB 2017-02-21 912d GBTTEST Rebuild after tidy + re-enable SC1 control - 1 link working!! :-( GLIB 2017-02-21 9131 GBTTEST Enable both SC status words again (only got 1 GBT :-( ) GLIB 2017-02-21 9130 GBTTEST Disable both SC status words - 2 links working! GLIB 2017-02-20 912c GBTTEST 2 GBT links working NV 2017-02-16 b125 FIB_IDCONLY Added PRNG to fmc_clk1_m2c line (but as output), for use with FMC105 (xil)use sw(7:6) to control freq. NV 2017-02-16 b124 FIB_LOOP Checking to see if this works at 160Mb) NV 2017-02-16 b121 FTCDS_TEST Changed to 160Mb link (from 320) GLIB 2017-02-16 911f GBTTEST Datagen with counters 2x80Mbb GLIB 2017-02-16 9126 GBTTEST Trying all 20 elinks GLIB 2017-02-16 9123 GBTTEST Trying again ... (worked!) GLIB 2017-02-16 9122 GBTTEST ASIC packet datagen 2x80Mb (dead!) NV 2017-02-15 b120 FTCDS_TEST Quick and dirty test rig for TCDS-FMCs NV 2017-02-10 b118 FIB_STD Undid reversed reg init values bug ... ATLYS 2017-02-10 a118 VADAPT Undid reversed reg init values bug ... ATLYS 2017-02-09 a116 VADAPT Added inverts for streams (strm_reg) and outputs (reg INVERTS) ATLYS 2017-01-24 a115 ABCN_TTC ABCN rebuild with SPYSIGS re-added ATLYS 2017-01-24 a114 MAD12 Attempt to get more links for Carlos. Failed on 3 constraints!! ATLYS 2016-12-22 a113 CHS2 re-inverted saci-clk to be correct, as was originally done (sorry :-( ) ATLYS 2016-12-22 a112 CHS2 CHESS-2 SACI loop removed, expected to work with real thing :-) Merry Christmas!! ATLYS 2016-12-22 a111 CHS2 CHESS-2, more SACI logic fixes - saci cmd loop to resp back via internal pipeline ATLYS 2016-12-21 a110 CHS2 CHESS-2, add 40MHz clock to CHESS-2 + SACI logic fixes ATLYS 2016-12-16 a10f CHS2 CHESS-2, first build for testing NV 2016-12-15 b050 FIB_IDCONLY First attempt at IDC only f/w - links 16,17 (streams 32-36) now with Nexys I2C (that includes FMC I2C) on TWOWIRE channel 15 NV 2016-12-15 b04f FIB_LOOP now with triggerrerered datagen NV 2016-12-13 b04c FIB_LOOP J5 out, J6 in, 2x160Mb streams on each output NV 2016-12-13 b04b FIB_STD All connectors included - NOT TESTED NV 2016-12-03 b052 FIB_IDCONLY Below didn't work reverting to orignal TWOWIRE for now NV 2016-12-03 b051 FIB_IDCONLY Changed TWOWIRE operation (removed SCL /pulse at before start) GLIB 2016-11-06 91b0 GBTSTIB_TGRW Back to Widebus RX, 16 links enabled. (No CS) ATLYS 2016-09-26 a10e VADAPT Peters new board, with ATLYS 2016-09-26 a10d IDC_PRNG3 PRNG on D13-15 ATLYS 2016-09-21 a10c IDC_PRNG PRNG D15 ATLYS 2016-08-08 a10b PANEL Fixed D2 to be input for PANEL builds - Tidied "Peter TB mode" to be D2R_I2C_EN (and IDC mode) NV 2016-07-27 b045 F2V2_TTT Added clk160 for ABCx_EMU use NV 2016-07-27 b044 F2V2_TTT Changed to MMCM multiplier of 24 - because coregen said so! NV 2016-07-26 b043 F2V2_TTT rebuild with bank-voltage back to 2V5 - works! (i forget when I set it to 3v3 :-( ) need to investigate this further - may be a sillyness NV 2016-07-26 b042 *F2V2 Added DDR to OSERDES "NV 2016-07-26 b041 *F2V2 rejigged constraints - isolated clk125, clk40, clk40_ext. moved from 640 ISERDES to 320 DDR - 640 is >> Artix-2 spec (which is 400ish !!) - tidied, fixed rgmii constraints - rationalised net_top resets - We now have NO TIMING VIOLATIONS - yeee haaa! - But does it work ... And need to DDR OSERDES now ..." ATLYS 2016-07-26 a10a IDC130_TDC Reworked constraints - to match NexysV work - lots of TIGs to decouple uunrelated clocks NV 2016-07-20 b03d F2V2 removed core_rst - not needed. NV 2016-07-20 b03c F2V2 Coreclks reset fixed - does NOT reset anything else NV 2016-07-20 b03b F2V2 Soft resets working (except rst_coreclks) - fixed 0 payload opcode handling with multi-oc packets (I think) ATLYS 2016-07-20 a105 PANEL Soft resets working (except rst_coreclks) fixed 0 payload opcode handling with multi-oc packets (I think) NV 2016-07-08 b046 F2V_ABCN ATLYS 2016-07-06 a102 IDC130_TTC ATLYS 2016-07-06 a101 ABCN_TTC NV 2016-06-21 b031 F2V_ABCN again NV 2016-06-14 b02f F2V_ABCN (!) The first build with an ABCN option! NV 2016-06-13 b02e F2V_DRV ATLYS 2016-05-27 a100 PANEL_TLU_CS more debugging a non-problem ATLYS 2016-05-26 a0fd ABCN_TLU trying things with event fifo to fix stuck packets ATLYS 2016-05-25 a0fc PANEL_TLU_CS ATLYS 2016-05-24 a0fb ABCN_TLU ATLYS 2016-05-24 a0fa IDC_TLU Improved TLU-TDC handling ATLYS 2016-05-23 a0f9 IDC_TLU TLU i/f waits 4x12.5ns before deciding to keep a trigger (was 2x12.5ns) If trigger is rejected, nothing happens (except maybe a TDC word) Note SVN has this as va0f8, sorreeeeee! ATLYS 2016-05-23 a0f8 IDC_TLU ATLYS 2016-05-20 a0f7 IDC_TTC last trid = 0xffff at reset, busy assert count fix ATLYS 2016-05-20 a0f6 IDC_TTC added last TLU TRID readback - status 27 ATLYS 2016-05-18 a0f5 ABCN_TTC ATLYS 2016-05-18 a0f4 ABCN_TLU ATLYS 2016-05-17 a0f3 IDC_PANEL ATLYS 2016-05-17 a0f2 IDC_TLU Slight change to data handling ATLYS 2016-05-14 a0f0 IDC_TLU_P improved timing for trigger data storage - fixed TDC output inhibit - only 1 TDC work per trig now - Added IDE I2C on RESET pair option (TB_PETER_MODE) This is enabled (hence "_P"). sck=_P, sda=_N. CH10 ATLYS 2016-05-11 a0e7 ABCN_TTC ATLYS 2016-05-11 a0e6 ABCN_TLU ATLYS 2016-05-11 a0e5 IDC_TTC ATLYS 2016-05-11 a0e4 IDC_TLU Delayed duplicate triggers option added Added burst trigs to trigger data (good thing?) Tried to reduce timing errors. Failed. Improved stream fifoing (72-in, 18-out) HSIO 2016-05-06 4442 only HSIO 2016-05-04 443f HSIO 2016-05-04 4441 trying some better timing constraints. HSIO 2016-05-04 4440 Fixed decoder type (doh! was ABCN) ATLYS 2016-05-03 a0d2 IDC_TTC Simulated working TLU as TTC PMOD option (reg 33.0) ATLYS 2016-05-03 a0d1 IDC_TLU Option to turn anti-glitch off (reg 31.3) ATLYS 2016-05-01 a0d0 IDC_TLU TLU inferface demands trigger-in is high for >25ns before progressing with handshake. TRID resets to 0xffff ATLYS 2016-04-30 a0cf IDC_TLU PMOD_TTC inputs can be switched to TLU handler a la Dennis' PMOD_TLUD Added counters for ECRs and BCRs, with "command" resets ATLYS 2016-04-30 a0ce IDC_TLU More options for event data packets: choose TLU word instead of timestamp word at start choose timestamp word after every event word changed event data timestamps to hires mode ATLYS 2016-04-26 a0cd IDC_TTC Added Drv I2C lines (only in IDC/non-TLU builds) ATLYS 2016-04-26 a0cc DRV_TTC rebuild - refresh - no changes ATLYS 2016-03-17 a0ca IDC130_TLU ATLYS 2016-03-17 a0c9 ABCN_TLU ATLYS 2016-03-17 a0c8 IDC130_TLU ATLYS 2016-03-17 a0c7 ABCN_TLU Added tlu_trid=0 debug pin NV 2016-03-03 b02c F2V8 Added datagen - see reg 36, twiki 640Mb capture included (not tested) sysreg/stat working ATLYS 2016-03-03 a0c6 DRV_TLU ATLYS 2016-03-03 a0c5 IDC130_TTC added datagen - controlled by reg 36-39 see twiki ATLYS 2016-02-26 a0c1 IDC130_TLU fixed sysstatrd returned opcode, cap640 work (works in sim) ATLYS 2016-02-24 a0bf IDC130_TTC with untested cap640 too ATLYS 2016-02-17 a0be ABCN_TTC ATLYS 2016-02-12 a0bd Makefile build NV 2016-02-09 b116 FIB_STD Programmable inverts for stream in (via strm reg) and control outputs (reg INVERTS) NV 2016-02-05 b02a makefile build NV 2016-02-05 b029 F2V8 Added System Reg & Stat Wr, Rd (see twiki) Added PMOD_TLU on JB, PMOD_TTC on JC - untested ATLYS 2016-02-05 a0bb NV 2016-01-28 b023 F2V_DRV First attempt at a simple Driver i/f NV 2016-01-27 b022 F2V8 (Net IDELAY=0) - fixed Samtec remap bug NV 2016-01-27 0 -- Note new version number -- the lower 3 nibbles are now common across all boards ---- NV 2016-01-26 b054 FIB_STD Inverted all FMC signals - seems the FMC-IB pinout is swapped :-( NV 2016-01-26 b053 FIB_STD Added INVERTS register (#48) NV 2016-01-16 b021 F2V8 (Net IDELAY=0) NV 2016-01-15 b020 F2V8 (Net IDELAY=7) NV 2016-01-15 b01f Netloop+CS IDELAY=19 NV 2016-01-15 b01d Netloop+CS IDELAY=7 NV 2016-01-15 b01d Netloop+CS IDELAY=0 NV 2016-01-15 b01c Netloop+CS IDELAY=11 NV 2016-01-13 b015 Netloop+CS JA-0: rxc, 1: clk125, 2: clk125_90 NV 2016-01-13 b014 Netloop+CS no timing shift, clk125s on JA NV 2016-01-13 b013 Netloop+CS shifted rx timings 24 steps NV 2016-01-13 b012 Netloop+CS shifted rx timings 8 steps NV 2016-01-13 b011 Netloop+CS shifted rx timings 16 steps NV 2016-01-13 b010 Netloop+CS NV 2016-01-12 b00f F2V2 NV 2016-01-12 b00e Net loopback only ... NV 2016-01-12 b00d F2V2 with chipscope NV 2015-12-22 b00c F2V2 changed default OPHASE NV 2015-12-22 b00b F2V16 more of the same (but a silly ver!) NV 2015-12-21 b00a F2V2 rebuild on laptop after much SVN shenanigans NV 2015-12-21 b009 F2V2 some ABCN (mostly) triggering mods NV 2015-12-18 b008 F2V16 version with 16 links (no PMODs) NV 2015-12-11 b001 1st version with Ethernet, no DIOs yet NV 2015-12-10 b000 Happy birthday to me ATLYS 2015-12-04 a0ba DRV phase control on DXouts - see reg 34 - OPHASE_DX HSIO 2015-12-01 443a slight changes to outsigs HSIO 2015-12-01 4439 updated to latest HSIO build, ALSO, new:- Has the new stream delay option as per '130 (streamconfig 14:12) - BUT BUT IDELAY is not changed ATLYS 2015-10-30 a0b9 IDC130_TLU TLU disables TDC when disabled ATLYS 2015-10-29 a0b8 IDC130_TLU L0ID in data stream timestamps ATLYS 2015-10-23 a0b7 ABCN_TTC ATLYS 2015-10-23 a0b6 ABCN_TLU stream status readback fix ATLYS 2015-10-22 a0b5 ABCN_TLU ATLYS 2015-10-22 a0b4 ABCN_TTC added other ext-triggers to the LED (pre=enables) ATLYS 2015-10-22 a0b3 ABCN_TTC ATLYS 2015-10-22 a0b1 ABCN_TLU * ATLYS 2015-10-22 a0b0 ABCN_TTC * ATLYS 2015-10-21 a0ae IDC130_TLU Timeouts now programmable by reg 32: RO_FIFO_TO. defaults to 50KHz (no change) ATLYS 2015-10-21 a0ad IDC130_TLU reverted back to faster packet fill timeout ATLYS 2015-10-21 a0ac IDC130_TLU reverted oc_dtack_n resolution (no more if 'Z' ...) WORKS! ATLYS 2015-10-21 a0ab IDC130_TLU *data packet fill timeout changed: 10x longer ATLYS 2015-10-21 a0aa IDC130_TLU *has outgoing phase offset compile option (no change, though) ATLYS 2015-10-19 a0a7 ABCN_TLU * ATLYS 2015-10-19 a0a6 ABCN_TTC * HSIO 2015-10-19 4437 added more TLU sigs to debug pins, fixed tlu_trig LED HSIO 2015-10-19 4436 proper phase compensation to match Atlys HSIO 2015-10-19 4435 Inverted BCO on IDCs to match Atlys phase HSIO 2015-10-16 4434 code re-org to match Atlys, added fine delay on IDC outgoing signals too ATLYS 2015-10-15 a0a4 IDC130_TTC * ATLYS 2015-10-15 a0a3 ABCN_TTC * ATLYS 2015-10-15 a0a2 Further fixes for stream config readout, TLU TDC inhibit for trigger number "triggers" ATLYS 2015-10-14 a0a1 Fixes for stream config readout (not) ATLYS 2015-10-14 a09e Added more debug tlu lines ATLYS 2015-10-14 a09d IDC_TLU fixed dropped packet count ATLYS 2015-10-13 a09b CHS1 Jaya John (Oxford) build - well tested and working ATLYS 2015-10-10 a09c IDC_TLU added extra trigger data (TDC etc) - rejigged format a little: see twiki ATLYS 2015-10-10 a09a CHS1 fixed fifo_ack_gen ATLYS 2015-10-08 a099 CHS1 added special functions (e.g. sync reset) ATLYS 2015-10-07 a098 CHS1 Includes Rui's start on SPI on TWOWIRE channels 1,2 ATLYS 2015-10-06 a097 CHS1 first attempt ATLYS 2015-10-06 a096 IDC130 fixed d008 format =2 ( was 1??? :-) ) Updated trigger code to log l0id asap, and added ts to tlu data ATLYS 2015-09-25 a095 IDC130 fixed d008 format =1 (was 2???) ATLYS 2015-09-25 a094 IDC130 fixed dead clock from nor 320_lock bug ATLYS 2015-09-24 a093 IDC130 640mb data deser, fixed 2x160 demux ATLYS 2015-09-22 a092 IDC130 reg/stat bugfixes ATLYS 2015-09-22 a091 IDC130 new 640Mb serialised COM. increased reg, statblock ATLYS 2015-09-21 a090 IDC130 with 10x faster timeout for packet filling ATLYS 2015-09-21 a08f IDC130 (same as 8d below, but not accidently overwritten!) ATLYS 2015-09-18 a08e PANEL ( part of test below - for comparison) ATLYS 2015-09-18 a08d IDC130 (test to check logic utilisation) ATLYS 2015-09-07 a08c ABCN ATLYS 2015-09-07 a08b DRV Fixed OC_ECHO not working ... ATLYS 2015-08-07 a08a DRV Fixed DRV line assign bug (tmu_com_invert) ATLYS 2015-08-06 a089 DRV ATLYS 2015-07-31 a088 IDC with buttons working properly ATLYS 2015-07-17 a083 ABCN ATLYS 2015-07-17 a082 IDC with btnC = send Status, btnU = send regblock ATLYS 2015-07-07 a080 IDC updatd arch version: cx, packet xoff, etc HSIO 2015-07-07 4430 first outing of new CX firmware, packet level xoff, dropped packet counter ATLYS 2015-06-26 a07c ABCN build ATLYS 2015-06-11 a07b IDC build ATLYS 2015-06-11 a07a DRV fixed double counting in PMOD_TTC TRIG_2 ATLYS 2015-06-11 a079 DRV updated pkt detect looking for 65b with 01xxxxxxxx... ATLYS 2015-06-11 a078 DRV rebuild with some some muxing changes reverted ATLYS 2015-06-11 a077 DRV unswapped PMOD_TLU trig and busy outputs ATLYS 2015-06-11 a076 DRV fixed 25ns busy generated when busylen set to 0 (no CX) ATLYS 2015-06-09 a072 Back to clock crossing firmware - better for debugging (oops same ver) ATLYS 2015-06-09 a072 Trial with clock crossing (CX) firmware - better for debugging ATLYS 2015-06-08 a071 DRV build ATLYS 2015-06-03 a06e IDC-PTTC Robusterised the stream fifos against overflow tried to make a smarter passive mux enabled all 1s packet un-detect ATLYS 2015-06-02 a06c IDC-PTTC removed clock crossing logic ATLYS 2015-06-02 a06b IDC PMOD-TTC fixed tdc readout ATLYS 2015-06-02 a06a IDC PMOD-TTC with input trig counters ATLYS 2015-06-01 a066 IDC PMOD-TTC integration - I2C in, rest is still in-progress (there, but ..) ATLYS 2015-05-28 a064 IDC New structure - clock segregation - should function the same ATLYS 2015-05-20 a05d DRV 40MHz readout mode added ATLYS 2015-05-19 a05c ABCN lots of debug outputs added - see twiki HSIO 2015-05-13 4423 fixed TDC no-command bug HSIO 2015-05-07 4421 fixed IDC mapping bug ATLYS 2015-05-06 a059 IDC TLU sigs on VMODIB D12,D13 ATLYS 2015-05-06 a058 IDC rebuild with latest TLU and trigger mods HSIO 2015-05-06 441f refixed TDC data align, killed spurios TLU_tclk HSIO 2015-04-28 441d fixed TDC status register entries HSIO 2015-04-28 441c moved TDC to top level - fixed TDC inputs bug HSIO 2015-04-27 441b moved TDC to top level, updated tlu/tdc ids to be more robust changed trigger paths with delay at end of chain HSIO 2015-04-16 441a TDC included build ATLYS 2015-04-13 a057 DRV fixed header detect bug - MAY work ATLYS 2015-04-09 a056 ABCN shows nice signs of life ... ATLYS 2015-04-08 a055 DRV ATLYS 2015-04-08 a054 ABCN (not working!) ATLYS 2015-04-03 a053 IDC. Modified ISERDES2 generics (MODE=RETIMED, WIDTH=4) Seems to work on new Atlys'!! ATLYS 2015-03-25 a050 IDC. Debug outputs: D4-5=delayed D0-1; D8-11=demuxed D0.0,D0.1,D1.0,D1.1 ATLYS 2015-03-25 a04c IDC Added Driver controls, but they don't quite work ATLYS 2015-03-23 a049 IDC Fixed no OUTSIGs bug. HSIO 2015-03-23 4417 added MAC address filtering on if0 - it was off!! HSIO 2015-03-23 4416 build - added sim lines - disp works (don't know why :-( ) ATLYS 2015-03-20 a047 Driver build of recent FW. Includes TLU, busy etc. as mentioned below HSIO 2015-03-20 4414 build - rebuilt for sanity HSIO 2015-03-14 4413 build - fixed mapping bug ATLYS 2015-03-13 b03d Variable busy length - see reg 10. TLU trigger number recieve control, see reg 31 *** NOTE: TLU controls from reg 19 MOVED to reg 31 *** HSIO 2015-03-13 4412 build Variable busy length - see reg 10. TLU trigger number recieve control, see reg 30*** NOTE: TLU controls from reg 19 MOVED to reg 31 *** ATLYS 2015-03-05 a037 busy changed back, added lu_trig and tlu_clk to MBCSV1 lemos ATLYS 2015-03-05 a036 Busy changed to make sync ATLYS 2015-03-05 a035 TLU sigs inverted (good with PMOD-bodge) ATLYS 2015-03-05 a034 TLU sigs un-inverted ATLYS 2015-03-05 a033 TLU sigs inverted with LEDs ATLYS 2015-03-04 a032 CMOS TLU HSIO 2015-02-13 440f HSIO 2015-02-13 440e Changed packet fifo to not preload opcode HSIO 2015-02-12 443e Makefile build HSIO 2015-02-08 443d Added sysreg ext clock selection HSIO 2015-02-08 443c Added sysreg stuff, with high-level resets HSIO 2015-02-06 440c Increasetimestamp timeout x8 (i.e. "empty" net-packet fills in 3ms, was 400us HSIO 2015-02-06 440b fixed ab c mode capture and mode80 capture HSIO 2015-02-04 440a shifted ABC mode data a by a bit HSIO 2015-02-02 4409 changed HCC-ABC bit mapping - looks good in sim now HSIO 2015-02-02 4408 changed HCC bit mapping HSIO 2015-02-02 4407 fixed dead capture bug HSIO 2015-01-30 4406 remapped HCC data format decoder, fixed capture mode to not be HCC/ABC mode dependent HSIO 2015-01-23 4405 rejigged capture, look good in sim. attemped an HCC data format decoder ...Fixed ABC data offset bug (I think) HSIO 2015-01-20 4404 Added opcode-start signal in P5 HSIO 2015-01-09 4403 Can invert COM on Driver using bit 6, reg_drv_conf HSIO 2015-01-08 4401 HCC option added ... HSIO 2015-01-07 443b Added output signal delay controls via reg 11. 0xdcba d:DCLK c:RESET, b:L1R, a:COM ATLYS 2014-11-14 a02a MBH35 with serout ATLYS 2014-10-28 a029 DRV ATLYS 2014-10-28 a028 MBH35 Err ... now it really works ATLYS 2014-10-28 a027 MBH35 fixed trailing zero bug (again!) ATLYS 2014-10-28 a026 MBH35 modified packet handling (fifo half-empty check) HSIO 2014-10-23 4400 Top + Bot build UNTESTEDanged pinout to Driver, use with driver fw >= d040 ============= ATLYS 2014-10-20 a025 DRV proper decoder this time! even works! ATLYS 2014-10-17 a024 DRV rebuild ATLYS 2014-10-14 a023 MBH35 deser in place, sim says it works ATLYS 2014-10-14 a022 MBH35 fixed rawsigs sync too ATLYS 2014-10-13 a021 MBH35 first attempt at deser ATLYS 2014-10-13 a020 MBH35 20MHz RAWSEQ sync. CKFAST invert option ATLYS 2014-10-09 a01f MBH35 20MHz BCO option (reg16,10) ATLYS 2014-10-09 a01e CMOS aka MBH35 - no packet decoding yet ATLYS 2014-10-07 a018 DRV ATLYS 2014-10-02 a017 CMOSversion – MAC address now e0:dd:cc:bb:0n, n ser by sw(3:0) ATLYS 2014-10-01 a016 At last a log is born HSIO 2014-08-21 438e As perprevious, but with streams this time ;-) HSIO 2014-08-15 438d Added Bottom Driver I2C ATLYS 2014-07-21 a000 birthday! HSIO 2014-07-04 4380 TLU Calib updated HSIO 2014-07-03 437f Added TDC TLU mode (reg 19. bit 14) HSIO 2014-06-27 437e reallyreally fixed no-ts bug HSIO 2014-06-27 437d reallyfixed no-ts bug + better TLU-IB led mapping HSIO 2014-06-27 437c fixed no-timestamp option for packetiser bug HSIO 2014-06-26 437b ABC130streams for top only - should be fine for TB HSIO 2014-06-26 4378 build with usual ABC130 streams, burster in TLU debug added, trigger data stream =144 HSIO 2014-06-26 4376 TLU interface with degug mode added. L0ID works now too (OUTSIGS =0x2222). Only2streams HSIO 2014-06-24 4371 TLU interface in a good state HSIO 2014-06-20 4369 ABC130packet filling with timestamp instead of zeros noteslightly modified data format: link-id is now "block type". see twiki HSIO 2014-05-29 435d Fixed RAWSIGS idle output to not set all others low during signal assert Reinstated old TDC calib, chaged clk switch clock to clk125 lemo_bco_out now uses DDR to regen the clock on the pin HSIO 2014-05-29 435c tdc foobed HSIO 2014-05-29 435b tdc with encoded output too HSIO 2014-05-23 434e tdc test run HSIO 2014-05-23 434d no streams - test for tlu IO HSIO 2014-05-12 434c Added TLU_MODE (CONTROL1, bit 11) - so far send short busy after each trig_ext HSIO 2014-05-09 434b fixed bugs in sigs decoder, encoder and counters. Looks good in sim. HSIO 2014-05-09 434a reworked trigger top layer and more: - no more OC_RAWCOM (0x101) - temporary removal triggered = pattern go option- BCR and ECR decoding from ABC130 CMD stream - OCRAW_START lemo changed to pretrig - ORs ocraw_start and undelayed non-raw/seq trigger source- Pretrigger stretch option added in CONTROL1, bit 9 - Status reg changed to look at 32b L0ID instead of 24b L1ID - Added L0ID_L1 status word - contains the last L0ID sent by l1_autogen HSIO 2014-05-08 4349 Added OC_COMMAND(ECR) as counter reset for l1_autogen HSIO 2014-05-08 4348 (yes, same version, oops!) Automatic L1s from L0s option: reg CONTROL1, bit 10 HSIO 2014-05-06 4348 Idle high option for RAWSIGs/SEQ HSIO 2014-04-29 4345 Added option to stretch trig_out pulse reg CONTROL1, bit 8First build with separate ocb and locallink libs HSIO 2014-03-31 4343 Removed BUFGMUX - it's syncrhonous, DOH DOH DOH! HSIO 2014-03-31 4342 Added DIFF_TERM for P5 ext clock input ... HSIO 2014-03-13 4341 Ready for new Driver schema bit HSIO 2014-03-13 4340 "improved" timing constraints ... functionally the same as 433c HSIO 2014-03-12 433c Fixed cyclic bug in sequencer HSIO 2014-03-10 433a 65MHz BCO capable!! Took >30m to build, so just a proof of principle for when we need it HSIO 2014-03-10 4339 50MHz BCO capable. Stable clock switching in place - see reg 0.Some LEMOs remapped: 1= Busy out, 2 = BCO out, 3=BCO in, 4=Trig inMore DCM status bits in statword 15. HSIO 2014-03-06 4332 External clock on LEMOs added - can select either Clocky via P2, or LEMO HSIO 2014-03-05 4331 Clockyfix - pin swaps on IDC conn. Works! HSIO 2014-03-04 4330 Clockybuild. Clocky didn't work. HSIO 2014-02-24 432f Swapped clock/r3 to Driver - needs updated Driver f/w (>0xd02b) HSIO 2014-02-21 432e Added bottom driver connection HSIO 2014-02-20 432d fixed deser machine for "odd" state HSIO 2014-02-20 432c REALLYChanged header trailer detect to H=0001,0 HSIO 2014-02-20 432b Changed header trailer detect to H=0001,0 HSIO 2014-02-12 432a ISE14!This build with HSIO-A13 HSIO 2014-02-07 4329 added clock board test on P2 pins, incl. ext_clk input HSIO 2014-01-30 4328 moved I2C IO blocks to top level HSIO 2014-01-30 4327 reverted to stave250 version on TWOWIRE HSIO 2014-01-29 4326 Changed ABC130 pkt packing timeout tick from 1KHz to 500kHz! HSIO 2014-01-28 4325 Changed ABC130 pkt packing timeout tick from 10KHz to 1KHz HSIO 2013-12-13 4323 Changed reg 18 mappings - see twiki, tidied some BUFGs to help build HSIO 2013-12-13 4321 Added TMU readback on link 20 (stream 40) HSIO 2013-12-11 4320 Fixed inverted RAWOUT_EN, Capture fixed (broke it when I fixed it last time) HSIO 2013-12-10 431f Fixed missing RAWOUT_EN bugMade capture start when NON in RAWOUT_EN mode and when new SCAN_EN bit rises HSIO 2013-12-09 431e re-worked Driver dx lines and seq to incorp ABC SCAN HSIO 2013-12-06 431c increased capture len to 10b = max 6 packets = 60kb = 7.6kB HSIO 2013-12-05 431b Re-Fixed Capture 60b bug - it's not a bug :-( HSIO 2013-12-05 431b Fixed Capture 60b bug, increased SEQ ram to 16kx16 HSIO 2013-12-05 431a Added capture_start on SCAN_EN HSIO 2013-11-29 4313 smarter header-trailer det - looks for 01 head and 0 trail - i.e 00FFFFFFFFFFFFFF isn't data! HSIO 2013-11-27 430f reverted to old tx_packet_format an tried a new ddr block for HSIO-A13 HSIO 2013-11-26 430e tryingto fix HSIO-A13 - failed HSIO 2013-11-24 430d Atlys single-chip version: Fixed channel stream assignments to match driver: 2=left, 14=right (or did I get that backwards) HSIO 2013-11-21 430b changed abc pkt head det to 01 (from 1) HSIO 2013-11-18 4307 8IH+HSIO-A13 + 4T. Moved IDELAY blocks to pins, reworked output blocks HSIO 2013-10-23 4303 8IH+HSIO-A13 - new sequencer and improved spy (see rawsigs option). Changes to some opcode handler mechanics - might be buggy Also noticed some incorrect packet lens - still looking ... HSIO 2013-10-11 41f2 16TH16BH possible tx CRC fix HSIO 2013-10-11 4300 Version jump - v42nn is being used by the stave250 branch HSIO 2013-09-30 41ed fixed CAL_EN register missing bug HSIO 2013-09-27 41ec moved the final ABC130 verilog. HSIO-A13, 1T A13+ FCF on B28-29 (120,122) - not seeming to work! HSIO 2013-09-19 41ea changed rx_packet_decoder to comply better with LL on the input - look out for CHOMPs!! HSIO 2013-09-18 41e9 HSIO-A13, 1T A13 HSIO 2013-09-17 41e8 HSIO-A13 only - now only stores source MAC when ethtype=0x876X - good for switch operation when more broadcast packets are expected HSIO 2013-09-13 41e5 16TH8IH - stavelet build HSIO 2013-09-13 41e4 ABC130test build HSIO 2013-09-11 41e1 *16TH16BH rebuild for Carlos with histos on top and bottom (NO IDC) HSIO 2013-09-07 41f0 16TH16BH - fixed short packet padding bug HSIO 2013-09-07 41ef 16TH16BH - hope it works Carlos - I've not tried it at all :-) HSIO 2013-09-06 41e0 *16TH8IH with external clock input on LEMO-J3. reg 0 = 0x100 to enable. HSIO 2013-09-05 41d9 *16TH8IH stavelet version with mutiple eth type support. Some opcodes may not work. Please report. HSIO 2013-08-29 41d8 fixed spy bug. ABC130 only version HSIO 2013-07-31 41d4 Fixed mux bug HSIO 2013-07-26 41cd same as 41cc, but with the muxed signals driving the HSIO-A13 - more realistic Works if mux_sel_inv is set - reg 23, bit 1 HSIO 2013-07-25 41cc 16T8I-A13 + HSIO-A13 -- with new mux and a mux sel invert bit (see control reg) HSIO 2013-07-25 41cb 16 Topstreams, 8 IDC streams, all ABC130 (16T8I-A13) + HSIO-ABC130FORGOT TO ADD THE COMLO and L1R3 muxes - fairly useless! HSIO 2013-07-24 41ca HSIO-ABC130 only HSIO 2013-07-22 41c9 +48T16B8IH - Everyone happy? HSIO 2013-07-21 41c8 16T16B8I - better for Carlos? HSIO 2013-07-21 41c7 48T8I - 1-wire for the stave HSIO 2013-07-21 41c6 16T16B- 1-wire for Sergio and Carlos too HSIO 2013-07-15 41c3 16TH8IH - Added I2C/1-wire controller on TWOWIRE ports 3,7 HSIO 2013-07-10 41be 2xABC130 only (on 124,126) 160MHz readout option - set reg 23 bit 2 HSIO 2013-07-09 41bb 16TH8IH - new option for sending DCS opcodes (TWOWIRE) on Eth-Type 0x8766 - reg 23,3 HSIO 2013-07-04 41b5 2xABC130 only (on 124,126) running at 80MHz readout. incl. single hit generator HSIO 2013-07-02 41b3 48T8I (no histo) - Go Peter go! HSIO 2013-07-02 41b2 1ABC130+8IH - chain of 2 abc130s on stream 124. abc130_test.cpp updated too. bug: no hits reported HSIO 2013-05-30 41ac 16TH8IHCleaned up SVN, added missing files and changed RAWSIGS to allow sending stave signals HSIO 2013-05-14 41ab 16TH8IHPlaying with compiling the ABC130 block and the readout block independently and including them as cores. HSIO 2013-05-14 41a8 added ext-trig debug outs HSIO 2013-05-01 41a7 16 top+ IDC (incl. histo) - added/moved some debug mappings HSIO 2013-04-26 41a6 16 top+ IDC (incl. histo) - fixed mode40 bug but there may be more ... HSIO 2013-04-24 41a4 16 top+ IDC (incl. histo) - fixed status and register readback bug HSIO 2013-04-05 419e 16 top, 16 bot (incl. histo) NO IDC HSIO 2013-04-05 419d 16 top, all IDC (incl. histo) fixed ext trigger bugs (>1!) - reworked ext trig edge detector, added more sync. Slight mod to status readback - might fix missing words bug. HSIO 2013-03-27 4194 16 top, 16 bot (incl. histo) NO IDC with added stream output debugs on P3 HSIO 2013-03-26 4192 16 top, 16 bot (incl. histo) NO IDC HSIO 2013-03-25 4191 fixed IDC BCO/DCLK swap. 16 top, 4 IDC (incl. histo) HSIO 2013-03-14 418d readout130 build for 12 modules double sided stave (no histo) HSIO 2013-03-14 418c fx100 build. top: all 48.idc: all HSIO 2013-03-11 4189 top: 16 raw, 48 histo. idc: all HSIO 2013-03-11 4188 top: 1raw, 2 histo. Added stream id in data correction HSIO 2013-03-11 4187 top: 16 raw, 32 histo. Use stream src 1 to switch to second raw set HSIO 2013-03-11 4186 First test with RAW multi stream mode HSIO 2013-03-11 4185 48 tophisto only, 0 bot, 4 IDC (with histo) HSIO 2013-03-11 4184 48 top(no histo), 0 bot, 4 IDC (with histo) HSIO 2013-03-08 4182 16 top, 16 bot, 2 IDC (incl. histo) HSIO 2013-03-08 4181 16 top, 4 IDC (incl. histo) HSIO 2013-02-28 417c Stavelet top and bottom + 1 IDC (the second one) HSIO 2013-02-28 4180 Stavelet + IDCs - has optimally phased trigger window option HSIO 2013-02-27 417a Moved output block to top level BCO/DCLK output drivers changed - now using DDR buffers Added primative trigger window - enable reg 23.9, adjust using 10:0 of reg 15 moved noise_en bit in control reg (now 23.13) HSIO 2013-02-08 416d 2 ABC130-chips HSIO 2013-02-05 416c ABC130-chip sending data HSIO 2013-01-29 4162 First iteration with ABC130 chip inside HSIO (stream 64)New opcode - RAWSIGs - for driving L0/L1/R3/COM signals HSIO 2013-01-02 4151 ABC130pkt formatting tidy, length optimised HSIO 2012-12-21 414b ABC130proto version. Readout for modules of ABC130 or ABCN type. Specify at build time.Only 1 data stream per ABC130 Module. Raw and capture modes. data gen works too,but needs enable via bit 5 in CONTROL reg HSIO 2012-11-29 413b fixed hysteresis code typo, added RAWCOM pattern go (which may not really work) HSIO 2012-11-12 4136 Added programmable busy_delta hi and low levels (aka hysterisis) - see reg 17Tidyied readout_top and ro_unit a little HSIO 2012-11-09 4135 changed structure to allow histos to be built without rawfifo option HSIO 2012-11-02 4132 busy bugfix HSIO 2012-11-01 4131 updated trig_decoder to skip over BCC headers - no more spurios trigger counts?? HSIO 2012-10-30 4130 fixed hd_delta stuck at max bug, added vbusy, added harder seq_reset HSIO 2012-10-29 412f REALLYreverted histo header change (for now) HSIO 2012-10-29 412e reverted histo header change (for now) HSIO 2012-10-29 412d changed deser (and ht_delta)header det from "12zero+11101" to 15zero+"111010" to try stop wrong counting. Added no-en reset to delta HSIO 2012-10-26 412c changed histo header det from "11101" to "000000000000011101" HSIO 2012-10-22 412b added lemo_trig_i invert option (See reg 3) HSIO 2012-10-02 412a improved ro_deser, fixed busy_en HSIO 2012-09-14 4129 fixed some timing inconsistencies with BCO vs DCLK. Removed EOS porch remapping option - it was broken anyway. HSIO 2012-08-23 4123 Rebuild using makefile generated .mcs (and .bit with CCLK) HSIO 2012-08-22 411f Added pullups to TWOWIRE ports HSIO 2012-08-22 4121 Added timestamp for make builds HSIO 2012-08-22 4120 Moved pullups to top level - ISE gets confused otherwise HSIO 2012-08-21 411e bug fixes in watchdog in TWOWIRE, and general tidying of oc_dack function,Added RESET_OCB opcode, not sure if it works yet In general HSIO is less likeky to hang-up. Stavelet build. HSIO 2012-08-17 4119 re-added the P2 Aux(12) TWOWIRE port(!) + 3 more (13,14,15) HSIO 2012-08-16 4118 re-build with makefile HSIO 2012-08-13 4117 moved some code around - new control_top to hide ocb sub-sys HSIO 2012-08-13 4116 22 module (88 stream) build. HSIO 2012-08-13 4115 SM Build HSIO 2012-08-10 4114 Stavelet build HSIO 2012-08-10 4112 added filter on magic_number, fixed watchdog too eager bug,removed 0xF080 opcode. HSIO 2012-08-10 4111 more bug fixing, 2 opcodes in an RX packet works for echo.fyi no streams in this build HSIO 2012-08-09 4110 Fixed some bug in back-to-back opcode handling and multi oc's per rx packet HSIO 2012-08-08 410f Multiple opcodes in an RX packet - untested - Stavelet Build HSIO 2012-08-08 410d Added buffer to TWOWIRE - no more delays, hopefully - Stavelet Build HSIO 2012-08-07 410c Added multi-channel in 1 packet option for TWOWIRE, Stavelet Build HSIO 2012-08-03 4109 Stavelet Build HSIO 2012-08-03 4108 fixed oc_dtack bug - tristates again - seems Z=1 - so now we have oc_dack_n HSIO 2012-08-03 4104 re-added all m_powers (only ones used - all the better for bug spotting) as pkg didn't work HSIO 2012-08-02 4102 removed all m_powers - doing from pkg.... HSIO 2012-08-01 4101 converted t_llsrc. ise just doesn't do well with tristates HSIO 2012-07-31 4100 converted all ll to t_llbus. Removed all set to zero if not in build generates HSIO 2012-07-30 40ff Reworked oc_dtack line to be bussed (pseudo open-collector,even more pseud as XST makes a wide-as-needed OR gate which is what I wanted in the first place) HSIO 2012-07-25 40fe OCSEQ fix - no more gaps - 16TH+8PH HSIO 2012-07-23 40fd Build with Bruces proc DDR pins now attached - 16TH+8PH HSIO 2012-07-23 40fc Another CRC config error fix (not as much hope as before) - 16TH+8PH HSIO 2012-07-23 40fb CRC config error fix - HOPEFULLY. Added Bruces proc wrapper. HSIO 2012-07-18 40fa working TWOWIRE, but no streams (£$%^& CRC says NO on conf problem is back). HSIO 2012-07-17 40f9 changed SHT case handling - just might fix weird bug. Added wdog_clr for each word. HSIO 2012-07-17 40f8 increased bad OC timeout to ~1s to be MUCH longer than serial timeout HSIO 2012-07-17 40f7 fixed missing TWOWIRE word bug HSIO 2012-07-17 40f6 invalid opcode watchdog confirmed working now. HSIO 2012-07-16 40f5 (re)added invalid opcode watchdog, fixed unassigned busys HSIO 2012-07-13 40f4 (16TH,8IH) mode40, robuster header-det, more reset options (netrx/tx),re-added net statwords. fixed TX data MAC address, now not 0x0000. All untested. HSIO 2012-07-05 40ea (16TH,8IH) Display fixed and TWOWIRE now supports SHT and I2C. See twiki. HSIO 2012-06-25 40d8 Work on fixing display. Note slow_ticks_gen.vhd move from utils lib to hsio to allow use of pkg_hsio_globals.vhd HSIO 2012-06-22 40d6 Slightly changed TWOWIRE command format (sorreeee) HSIO 2012-06-18 40d0 Stavelet build (16T+H, 8I+H) with the SHT71 too - see opcode 0x80 HSIO 2012-06-13 40c2 Stavelet build - 16 top + 8 IDC streams with histo -this isn't meant for playing with the SHT71 HSIO 2012-06-13 40c1 fixed SHT71 status reads (the $%^& chip doesn't work like the datasheet says!!!!!) HSIO 2012-06-12 40b8 added ocfifo full checking to rx_packet_decoder.if full incoming packet will not be processed and an ack with oc=0xaaff will be sent. If full during processing rx will hang until it's clear, probably triggering a bark HSIO 2012-06-11 40b6 TWOWIRE: work progresses forwards and backwards. 40b4 worked, 40b5 not ... HSIO 2012-06-08 40ad TWOWIRE: improved fifo handling HSIO 2012-06-08 40ac reverted to matts net_tx_pktfmt16 - bruces version has 2 CRCs HSIO 2012-06-07 40ab New SHT71 block, with possible i2c option HSIO 2012-05-29 40aa added SHT71 control block - opcode 0x80 - much debug trialing HSIO 2012-05-25 40a5 Added pattern sending (see opcode 0x70), enabled in control_reg HSIO 2012-05-24 40a4 Added fifo levels read-back, more stream status words, stream busys,pkt decoder respects size (ECHO is now correct!), reworked rx_packet_decoder_tb HSIO 2012-05-17 40a3 Debug outs rework - P4 moved to P5, P2,3,4 now unused. HSIO 2012-05-16 40a2 SM build - 32 top, 32 bot, 0 IDC, histos a not go. HSIO 2012-05-16 40a1 Stave build - 16 top, 8 IDC, histos a gogo. So far it seems good! HSIO 2012-05-16 40a0 ocrawcom_start set back to 12ns - messed up internals a bit HSIO 2012-05-16 409f ocrawcom_start now syncd and stretched to 25ns HSIO 2012-05-15 409e Seems to work, but ocrawcom_start has a glitch HSIO 2012-05-15 409d Yeeeks- somehow lost dbg_oe. test build with just IDCs, no histos ... HSIO 2012-05-14 409c Rebuild for SM - with 32 top, 32 bot, WITHOUT histo HSIO 2012-05-14 409b Rebuild for Stave - with 16 top, 8 IDC streams, WITH histo HSIO 2012-05-11 409a Yes, ANOTHER packet building bugfix in ro_deser, but this time it's working! HSIO 2012-05-11 4099 ANOTHER packet building bugfix in ro_deser HSIO 2012-05-11 4098 Another packet building bugfix in ro_deser HSIO 2012-05-11 4097 Robusterisation of case where trailers are very close to header (aka while pkt header is being sent) HSIO 2012-05-11 4096 Bug inerror packet sending another error packet and overflowing len fifo fixed HSIO 2012-05-11 4095 added len_fifo full checking (doh! to have missed it) -hopefully we are completely ROBUST now HSIO 2012-05-10 4094 48 streams HSIO 2012-05-10 4093 added ocb bus fifo after packet decoded to decouple net_tx from net_rx HSIO 2012-05-09 408f changed fifo-full tcs16(15 downto0) <= cs(31 downto 16); cs16(63 downto 16) <= (others => '0'); cs16(79 downto 64) <= cs(95 downto 80); cs16(135 downto 80) <= (others => '0'); o send NOTHING, fragments to go no more than 1, and indefinite wait for trailer after TRAILER_TO error HSIO 2012-05-09 408e Re-build for deser-fifo test - very few streams HSIO 2012-05-09 4092 changed to 48 streams, it worked! HSIO 2012-05-09 4091 dropped-packets-count added to second word of stream status packet --WON'T CONFIG - THAT $%^&* CRC ERROR! HSIO 2012-05-09 4090 fixed E/F packet labelling bug HSIO 2012-05-08 408d Re-build for SM mapping with 32 top (0-31) and 32 bottom streams(64-95) (no histos, no IDC) HSIO 2012-05-01 408c Build for Stave with IDCs HSIO 2012-04-20 408b Build for SM mapping with 32 top (0-31) and 32 bottom streams(64-95) (no histos, no IDC) - DIDN'T WORK HSIO 2012-03-08 408a Added external trigger input on LEMO-1, has input enables,synchroniser and prog delay, see in/out/int enable and tdelay registers HSIO 2012-03-08 4088 4086 for supermodule:stream enables (no histos): Top: 0-31, Bottom 8-40, all IDC HSIO 2012-03-05 4087 4086 for supermodule:stream enables (no histos): Top: 0-31, Bottom 16-47, all IDC HSIO 2012-03-02 4086 Found problem with autosmx, reverted to automux HSIO 2012-03-02 4085 Fix totx_pktfmt to remove spurious crc from end of data in short packets HSIO 2012-03-01 4084 Moved to stream block (top, bot, pp) separated modulo 64 HSIO 2012-02-29 4083 Movingto module build enables (was streams),optimised ro_fifo len_fifo - saves a good few FFs HSIO 2012-02-29 4082 Added Toms simulated data generator HSIO 2012-02-28 4081 another go at this. fx60: 16+8+8+histos, fx100: 104, no histos, removed network .ucfs HSIO 2012-02-28 4080 still got resource problems - made ro_unit automux synchro too HSIO 2012-02-27 407f top level of mux now synchro (= 64*20 extra flips flops),but should help reduce LUT usage, timing HSIO 2012-02-27 407e seems to work, re-enabled debug outputs.building 20+20+8, with histo. didn't fit HSIO 2012-02-27 407d NO DEBUG outputs. Added capture start on trigger mode - R_CONTROL, bit 12, 48+8 streams, no histo HSIO 2012-02-24 4078 Added register to output of tx_pkt_format HSIO 2012-02-24 4077 build with no histos 24 and 96 stream HSIO 2012-02-24 4076 removed async resets from histo files HSIO 2012-02-23 4075 removed additional bufg from clk40 chain, building for 32 with histo HSIO 2012-02-23 4074 bugfix- synxmux (the ONLY func change from pre-record versions) broken HSIO 2012-02-23 4073 separated dst_rdy from rest of record - xil don't di bidir records too well HSIO 2012-02-22 4072 reworked some of the ll busses to use records instead, no funcionality is supposed to change HSIO 2012-02-21 4071 Tieredthe resets to each top block via FFs, added "Cross Clock Analysis" XST option,and "Optimised Across Hierachy: Speed" Map option HSIO 2012-02-20 406f Added new networking .ucfs, rebuild with histos HSIO 2012-02-20 406e removed srcrdy fix (see v406c) - xil ll seems to ignore SOF! HSIO 2012-02-20 406d re-added reset command to inidividual streams - was missed out on all except histo, reordered capture mode checking in ro_deser - stops real data being used in capture mode HSIO 2012-02-20 4070 Added seperate resets via ocb_command HSIO 2012-02-17 406c src_rdy bug-fix in txfmt - building with 16 str, no histo HSIO 2012-02-17 406b moved to bram fifos and put IDCs on streams 32-39, always there, always with histo. HSIO 2012-02-16 406a rebuild with 32 streams and 32 histos. failed timing by 260ps! HSIO 2012-02-16 4069 removed eth statmon blocks, pause controller, build 16 str, no histo HSIO 2012-02-15 4068 reverted to newer mux HSIO 2012-02-15 4067 tryinglower speed grade -10 HSIO 2012-02-15 4066 tryingold syncmux from 310d to fix missing packet bug HSIO 2012-02-13 4065 changed spysig stream-id to 0xF0, fixed tb seq_reset stretch bug HSIO 2012-02-13 4064 removed clocks from sink bus - they cause timing foobars, and no need to look at them HSIO 2012-02-10 4063 first build with spysig stream added HSIO 2012-02-01 405e rebuild with fanout=100000 for XST HSIO 2012-01-31 405d same version AGAIN - rebuild for sanity check AGAIN (at UCL cluster) HSIO 2012-01-30 405c same version - rebuild for sanity check (on laptop) HSIO 2012-01-27 405c Fixed trig80 no connected to fake-data gen, removed latches from mux,played with planAhead, tidied st/unix/local/xilinxate machine logic HSIO 2012-01-02 4062 strobe40 not connected to triggertop bugfix, removed redundant BCO DCM - untested! HSIO 2012-01-02 4061 reg order bug-bug-bug fixed with a new reg type HSIO 2012-01-01 405f reg order-bug fixed HSIO 2012-01-01 4060 reg order bug-bug properly fixed HSIO 2012-01-01 4059 Rebuild in 2012. Initially 4 stream, then 32 - Does NOT have CRC error! HSIO 2011-12-14 4058 Added burster counts to status. removed enables for l1/bcid counting.added hsio l1/bcid reset commands HSIO 2011-12-14 4057 added new trigger_top, with burster, and improved signal path. Added oc 0x30 - COMMAND for sending pulses. Remapped dbg pins to be same as per sergio. changed muxs for bce sel to BUFGMUXs. HSIO 2011-12-05 4056 moved STREAMS_EN, HISTOS_EN, BUILD_NO to pkg_hsio_globals.vhd HSIO 2011-12-01 4055 histo trailer len fix HSIO 2011-11-25 4054 removed stream overflow detection -- too painful HSIO 2011-11-24 4053 fixed another oc 0x50/5c bug - reverted sma dbg connections HSIO 2011-11-22 4052 fixed oc 0x5c bugs, incl invalid stream detect HSIO 2011-11-11 4051 same but with version correct, and dbg pins oe reinstated HSIO 2011-11-09 404f moved bot streams from 23-16 to 15-8 HSIO 2011-11-09 4050 added stream debug lines HSIO 2011-11-08 404e fixed bot bco/l1r swap HSIO 2011-10-25 404d Added opcodes Bcast Stream Config/Command HSIO 2011-10-24 404c Extending stream wr/cmd opcodes for multiple streams/packet HSIO 2011-10-06 404b Started to add slow readout mode (using DCLK=40 setting) option for data muxed at 40MHz HSIO 2011-09-22 404a re-mapped enables for EOS-porch too. Signal P4 dbg outs look good on scope/LA now HSIO 2011-09-22 4049 fixed buf (no "lo") in fe_sigs_out HSIO 2011-09-21 4048 added new/consistent debug signals for ST/PP outputs on P4 HSIO 2011-09-19 4047 changed i2c to include channels and longer timeouts HSIO 2011-09-14 4046 reworked (duplicated) COM timing ffs HSIO 2011-09-13 4045 added timeouts to I2C HSIO 2011-09-10 4044 remapped bottom to start from the other side HSIO 2011-09-10 4043 added eos bottom connections for 16+16, added oc 0x42 for bottom temp readout HSIO 2011-08-08 4042 using optimised big mux HSIO 2011-08-08 4041 Improved rst clocking, Tom histo with Toms optimisations HSIO 2011-08-05 4040 Back to Alex's histo, with same fixes as tom's HSIO 2011-08-05 4030 Toms histo with reworked data readout, some reset fixes easier timing, modified automux, more tigs - even on reg_mon_en and reg_control HSIO 2011-08-03 4020 Tom's histogrammer HSIO 2011-08-03 4010 32/32 streams attempt. HSIO 2011-08-03 4000 NEW NUMBERING! HSIO 2011-07-29 2071 Added "automux" in ro_unit HSIO 2011-07-28 2070 Rebuild with renamed mux items HSIO 2011-07-25 2069 Fixed rx_pktfmt16 HSIO 2011-07-25 2068 ISE13.2!! HSIO 2011-07-25 2067 reworked rx_pktfmt16, added debug for rx_data HSIO 2011-07-22 2066 Integrated Errdems 16b Network interface, with pre-ll mux on the sfps HSIO 2011-07-21 2065 rebuilt AGAIN due to file corruption HSIO 2011-07-19 2064 rebuilt twice after some Xilinx Impact CRC errors HSIO 2011-07-19 2062 fixed EVEN ANOTHER ibpp mapping bug HSIO 2011-07-18 2061 fixed ANOTHER ibpp mapping bug, defaulted stream regs to 0 HSIO 2011-07-18 2060 fixed streams_cmd bug HSIO 2011-07-15 205f 4 streams defaulted to enabled, capture mode HSIO 2011-07-15 205e new schema 32 stream build (!!) HSIO 2011-07-14 205d fixed ocb_streams oc_dtack bug, removed all checksum HSIO 2011-07-12 205c modified crc to be at end of data and count type too HSIO 2011-07-08 205b added crc HSIO 2011-07-06 205a fixed ibpp sigs being mapped to nowhere bug HSIO 2011-07-04 2059 tidying, moved ibpps around, no new features HSIO 2011-06-30 2058 moved ack fifo blocks into ocbs HSIO 2011-06-28 2057 simplified clk_main timings, extra TIGs on clk_ready sigs, copper rx_clk HSIO 2011-06-27 2056 streamswap fix HSIO 2011-06-24 2055 secondsfp+ working, added 'leds' onto display HSIO 2011-06-17 204b fixed bco duty cycle, moded temp readback to send early net-ack. HSIO 2011-06-14 2046 fixed reset bug HSIO 2011-06-08 2041 even smarter spiser (no half clk), small echo fix HSIO 2011-06-08 2040 smarter spiser HSIO 2011-06-07 203e fixed minor bug in 0x101, 0x105 init state oc_valid handling HSIO 2011-06-06 203d echo and spi opcodes added, improved but not brilliant deser erroring HSIO 2011-05-25 203c updated ocb handling HSIO 2011-05-25 203b added status and temp readback HSIO 2011-05-23 203a register readout testing HSIO 2011-05-19 2039 added sf/rj45 network autoswitch HSIO 2011-05-17 2038 timeouts on unrecog opcodes HSIO 2011-05-12 2037 start of new opcode schema + confable sf map HSIO 2011-03-02 2036 reworked ro fifos for single clock HSIO 2011-02-22 2035 rebuild with bco_dc improved HSIO 2011-02-14 2033 First of the unified clocks ... HSIO 2011-01-31 2032 Added clk_idelay debug output HSIO 2011-01-27 2031 back to 180Mhz idelay HSIO 2011-01-27 2030 back to 200Mhz - sanity check HSIO 2011-01-27 2029 added better debug, and some streams HSIO 2011-01-26 2028 changed IDELAYCTL clk to 160MHz HSIO 2011-01-26 2027 start of 2011 work build HSIO 2010-11-30 2024 resetsAGAIN + eofin wrong clock fix HSIO 2010-11-29 2023 reverted to FIFO16 in ro_unit_fifo HSIO 2010-11-28 2020 clockssig rename, slight re-org of clk40 HSIO 2010-11-25 201e re-worked resets AGAIN HSIO 2010-11-25 201c re-worked resets AGAIN HSIO 2010-11-24 201b Added reset counters for debug HSIO 2010-11-23 201f 16 stream build HSIO 2010-11-23 201a reset bug fix again HSIO 2010-11-23 2019 reset bug fix HSIO 2010-11-23 2018 rebuild with 16 streams HSIO 2010-11-23 2017 reworked resets and fifos HSIO 2010-11-22 2016 debug en fix HSIO 2010-11-22 2015 capture mode fix, reworked eof det AGAIN HSIO 2010-11-21 2014 using hsio sff(instead of ib), debugs disableable, ibe_oscs inputs. crude noise out en... HSIO 2010-11-19 2013 added switch to PP option HSIO 2010-11-19 2012 remapped PPs to hyb-str 0-3 HSIO 2010-11-19 2011 header/trailer fix, histo fix++ + all the fixes from the non-eos ... HSIO 2010-11-15 2010 new ver numbering 2 in 2010 = C02 with EOS HSIO 2010-11-02 300f reworked capture and histo chomp fix. UNTESTED HSIO 2010-11-01 300e improved order of temp readout packet - may take longer, though. HSIO 2010-10-05 300d rebuild of above, because there may be confusion HSIO 2010-10-03 300c +37.5 MHz clkfx version, use ext_clk_en (hexsw=5) to select HSIO 2010-09-25 1000 added bco duty cycle control, 8 steams, 0 histos HSIO 2010-09-24 3200 32 stream build HSIO 2010-09-24 1500 fixed possible deltaeof overflow. priorised ack stream. HSIO 2010-09-23 2000 re-added ti2c, high hopes HSIO 2010-09-19 1700 16 streams - fixed reset HSIO 2010-09-15 300b unbuilt version with ti2c mods etc. for svn HSIO 2010-09-15 300a fixed ti2c state machine HSIO 2010-09-15 3009 added led flash on ti2c_req, parser fix HSIO 2010-09-15 3008 ti2c rework and more debug HSIO 2010-09-15 3007 ti2c quick fix (or not) with debug HSIO 2010-09-15 3006 histo quick fix (or not) HSIO 2010-09-15 3005 24 channel ti2c HSIO 2010-09-14 3004 ti2c wordstart now on debug output HSIO 2010-09-13 3003 enabled ALL stave streams, doh! HSIO 2010-09-13 3002 fixed pin swaps HSIO 2010-09-13 3001 same with 16st/0his HSIO 2010-09-12 3000 re-worked flow control even more - looks good in sim HSIO 2010-09-11 1200 16 streams - 4 stave hyb, 4 pp hyb HSIO 2010-09-11 1000 removed oc len change, added pullups for i2c sda lines HSIO 2010-09-10 1700 trial with changed oc len. HSIO 2010-09-10 1500 working version. HSIO 2010-09-10 1400 last recompile worked. add(ing/ed) new reset idea. HSIO 2010-09-07 3 re-worked flow control (!) HSIO 2010-09-07 2 empty pkt handling fix HSIO 2010-09-06 1000 first build with new fifo no-overflow, error packets etc HSIO 2010-09-06 1 idelayfixes HSIO 2010-08-10 700 now using stave T for top signals HSIO 2010-08-10 700 insane! HSIO 2010-08-10 700 removed i2c - sanity check HSIO 2010-08-09 1600 moved stave to 0-3, reduced debug lines HSIO 2010-08-09 1400 stave 0-3 added (as 4-7) with own enables etc. HSIO 2010-08-09 940 i2c readback added - untested HSIO 2010-08-05 1000 readback improved HSIO 2010-08-04 2100 64 chan + readback HSIO 2010-08-04 1200 readback re-added, changed muxes on dclk/bco ... HSIO 2010-08-04 1100 readback removed - won't fit ... HSIO 2010-07-26 1600 Rebuild with all mods and in SVN HSIO 2010-07-21 1000 TimingIGnores on IDC debug signals HSIO 2010-07-20 1000 8 streams enabled HSIO 2010-07-15 1000 New EOS IB version HSIO 2010-07-13 1000 reduced histo-fifo to 1 register, corrected 2nd histo packet size problem HSIO 2010-07-07 1000 re-added duty cycle correction, added second datagen HSIO 2010-06-11 0 Rebuild of good firmware (aka 0xedball50) from 08/06/10 HSIO 2010-06-11 1200 removed duty cycle correction from BCO DCM - dclk enable replaced by bco invert option, better defaults - includes fixes from 09/06 tester bug fixes ... GLIB 2017-03-02 9138 GBTBERT tester - e-links 28, 30 NV 2017-02-22 b135 FIB_STD With PMODs enabled GLIB 2017-02-22 9137 G_LCBDG LCB data generator GLIB 2017-02-22 9136 GBTTEST Trying no-mux option for data (getting ready for LCB datagen) GLIB 2017-02-22 9133 GBTTEST Made TX dependent on rxReady - cleans up bad e-links GLIB 2017-02-22 9132 GBTTEST Removed more SC stuff, elinks f000f on both GBTs GLIB 2017-02-21 912f GBTTEST disabled SC1 status - still only link-1 working GLIB 2017-02-21 912e G_ST130 GBT Stave build - L0COM/L1R3 over 160Mb e-links etc - seems good GLIB 2017-02-21 912d GBTTEST Rebuild after tidy + re-enable SC1 control - 1 link working!! :-( GLIB 2017-02-21 9131 GBTTEST Enable both SC status words again (only got 1 GBT :-( ) GLIB 2017-02-21 9130 GBTTEST Disable both SC status words - 2 links working! GLIB 2017-02-20 912c GBTTEST 2 GBT links working NV 2017-02-16 b125 FIB_IDCONLY Added PRNG to fmc_clk1_m2c line (but as output), for use with FMC105 (xil)use sw(7:6) to control freq. NV 2017-02-16 b124 FIB_LOOP Checking to see if this works at 160Mb) NV 2017-02-16 b121 FTCDS_TEST Changed to 160Mb link (from 320) GLIB 2017-02-16 911f GBTTEST Datagen with counters 2x80Mbb GLIB 2017-02-16 9126 GBTTEST Trying all 20 elinks GLIB 2017-02-16 9123 GBTTEST Trying again ... (worked!) GLIB 2017-02-16 9122 GBTTEST ASIC packet datagen 2x80Mb (dead!) NV 2017-02-15 b120 FTCDS_TEST Quick and dirty test rig for TCDS-FMCs NV 2017-02-10 b118 FIB_STD Undid reversed reg init values bug ... ATLYS 2017-02-10 a118 VADAPT Undid reversed reg init values bug ... ATLYS 2017-02-09 a116 VADAPT Added inverts for streams (strm_reg) and outputs (reg INVERTS) ATLYS 2017-01-24 a115 ABCN_TTC ABCN rebuild with SPYSIGS re-added ATLYS 2017-01-24 a114 MAD12 Attempt to get more links for Carlos. Failed on 3 constraints!! ATLYS 2016-12-22 a113 CHS2 re-inverted saci-clk to be correct, as was originally done (sorry :-( ) ATLYS 2016-12-22 a112 CHS2 CHESS-2 SACI loop removed, expected to work with real thing :-) Merry Christmas!! ATLYS 2016-12-22 a111 CHS2 CHESS-2, more SACI logic fixes - saci cmd loop to resp back via internal pipeline ATLYS 2016-12-21 a110 CHS2 CHESS-2, add 40MHz clock to CHESS-2 + SACI logic fixes ATLYS 2016-12-16 a10f CHS2 CHESS-2, first build for testing NV 2016-12-15 b050 FIB_IDCONLY First attempt at IDC only f/w - links 16,17 (streams 32-36) now with Nexys I2C (that includes FMC I2C) on TWOWIRE channel 15 NV 2016-12-15 b04f FIB_LOOP now with triggerrerered datagen NV 2016-12-13 b04c FIB_LOOP J5 out, J6 in, 2x160Mb streams on each output NV 2016-12-13 b04b FIB_STD All connectors included - NOT TESTED NV 2016-12-03 b052 FIB_IDCONLY Below didn't work reverting to orignal TWOWIRE for now NV 2016-12-03 b051 FIB_IDCONLY Changed TWOWIRE operation (removed SCL /pulse at before start) GLIB 2016-11-06 91b0 GBTSTIB_TGRW Back to Widebus RX, 16 links enabled. (No CS) ATLYS 2016-09-26 a10e VADAPT Peters new board, with ATLYS 2016-09-26 a10d IDC_PRNG3 PRNG on D13-15 ATLYS 2016-09-21 a10c IDC_PRNG PRNG D15 ATLYS 2016-08-08 a10b PANEL Fixed D2 to be input for PANEL builds - Tidied "Peter TB mode" to be D2R_I2C_EN (and IDC mode) NV 2016-07-27 b045 F2V2_TTT Added clk160 for ABCx_EMU use NV 2016-07-27 b044 F2V2_TTT Changed to MMCM multiplier of 24 - because coregen said so! NV 2016-07-26 b043 F2V2_TTT rebuild with bank-voltage back to 2V5 - works! (i forget when I set it to 3v3 :-( ) need to investigate this further - may be a sillyness NV 2016-07-26 b042 *F2V2 Added DDR to OSERDES "NV 2016-07-26 b041 *F2V2 rejigged constraints - isolated clk125, clk40, clk40_ext. moved from 640 ISERDES to 320 DDR - 640 is >> Artix-2 spec (which is 400ish !!) - tidied, fixed rgmii constraints - rationalised net_top resets - We now have NO TIMING VIOLATIONS - yeee haaa! - But does it work ... And need to DDR OSERDES now ..." ATLYS 2016-07-26 a10a IDC130_TDC Reworked constraints - to match NexysV work - lots of TIGs to decouple uunrelated clocks NV 2016-07-20 b03d F2V2 removed core_rst - not needed. NV 2016-07-20 b03c F2V2 Coreclks reset fixed - does NOT reset anything else NV 2016-07-20 b03b F2V2 Soft resets working (except rst_coreclks) - fixed 0 payload opcode handling with multi-oc packets (I think) ATLYS 2016-07-20 a105 PANEL Soft resets working (except rst_coreclks) fixed 0 payload opcode handling with multi-oc packets (I think) NV 2016-07-08 b046 F2V_ABCN ATLYS 2016-07-06 a102 IDC130_TTC ATLYS 2016-07-06 a101 ABCN_TTC NV 2016-06-21 b031 F2V_ABCN again NV 2016-06-14 b02f F2V_ABCN (!) The first build with an ABCN option! NV 2016-06-13 b02e F2V_DRV ATLYS 2016-05-27 a100 PANEL_TLU_CS more debugging a non-problem ATLYS 2016-05-26 a0fd ABCN_TLU trying things with event fifo to fix stuck packets ATLYS 2016-05-25 a0fc PANEL_TLU_CS ATLYS 2016-05-24 a0fb ABCN_TLU ATLYS 2016-05-24 a0fa IDC_TLU Improved TLU-TDC handling ATLYS 2016-05-23 a0f9 IDC_TLU TLU i/f waits 4x12.5ns before deciding to keep a trigger (was 2x12.5ns) If trigger is rejected, nothing happens (except maybe a TDC word) Note SVN has this as va0f8, sorreeeeee! ATLYS 2016-05-23 a0f8 IDC_TLU ATLYS 2016-05-20 a0f7 IDC_TTC last trid = 0xffff at reset, busy assert count fix ATLYS 2016-05-20 a0f6 IDC_TTC added last TLU TRID readback - status 27 ATLYS 2016-05-18 a0f5 ABCN_TTC ATLYS 2016-05-18 a0f4 ABCN_TLU ATLYS 2016-05-17 a0f3 IDC_PANEL ATLYS 2016-05-17 a0f2 IDC_TLU Slight change to data handling ATLYS 2016-05-14 a0f0 IDC_TLU_P improved timing for trigger data storage - fixed TDC output inhibit - only 1 TDC work per trig now - Added IDE I2C on RESET pair option (TB_PETER_MODE) This is enabled (hence "_P"). sck=_P, sda=_N. CH10 ATLYS 2016-05-11 a0e7 ABCN_TTC ATLYS 2016-05-11 a0e6 ABCN_TLU ATLYS 2016-05-11 a0e5 IDC_TTC ATLYS 2016-05-11 a0e4 IDC_TLU Delayed duplicate triggers option added Added burst trigs to trigger data (good thing?) Tried to reduce timing errors. Failed. Improved stream fifoing (72-in, 18-out) HSIO 2016-05-06 4442 only HSIO 2016-05-04 443f HSIO 2016-05-04 4441 trying some better timing constraints. HSIO 2016-05-04 4440 Fixed decoder type (doh! was ABCN) ATLYS 2016-05-03 a0d2 IDC_TTC Simulated working TLU as TTC PMOD option (reg 33.0) ATLYS 2016-05-03 a0d1 IDC_TLU Option to turn anti-glitch off (reg 31.3) ATLYS 2016-05-01 a0d0 IDC_TLU TLU inferface demands trigger-in is high for >25ns before progressing with handshake. TRID resets to 0xffff ATLYS 2016-04-30 a0cf IDC_TLU PMOD_TTC inputs can be switched to TLU handler a la Dennis' PMOD_TLUD Added counters for ECRs and BCRs, with "command" resets ATLYS 2016-04-30 a0ce IDC_TLU More options for event data packets: choose TLU word instead of timestamp word at start choose timestamp word after every event word changed event data timestamps to hires mode ATLYS 2016-04-26 a0cd IDC_TTC Added Drv I2C lines (only in IDC/non-TLU builds) ATLYS 2016-04-26 a0cc DRV_TTC rebuild - refresh - no changes ATLYS 2016-03-17 a0ca IDC130_TLU ATLYS 2016-03-17 a0c9 ABCN_TLU ATLYS 2016-03-17 a0c8 IDC130_TLU ATLYS 2016-03-17 a0c7 ABCN_TLU Added tlu_trid=0 debug pin NV 2016-03-03 b02c F2V8 Added datagen - see reg 36, twiki 640Mb capture included (not tested) sysreg/stat working ATLYS 2016-03-03 a0c6 DRV_TLU ATLYS 2016-03-03 a0c5 IDC130_TTC added datagen - controlled by reg 36-39 see twiki ATLYS 2016-02-26 a0c1 IDC130_TLU fixed sysstatrd returned opcode, cap640 work (works in sim) ATLYS 2016-02-24 a0bf IDC130_TTC with untested cap640 too ATLYS 2016-02-17 a0be ABCN_TTC ATLYS 2016-02-12 a0bd Makefile build NV 2016-02-09 b116 FIB_STD Programmable inverts for stream in (via strm reg) and control outputs (reg INVERTS) NV 2016-02-05 b02a makefile build NV 2016-02-05 b029 F2V8 Added System Reg & Stat Wr, Rd (see twiki) Added PMOD_TLU on JB, PMOD_TTC on JC - untested ATLYS 2016-02-05 a0bb NV 2016-01-28 b023 F2V_DRV First attempt at a simple Driver i/f NV 2016-01-27 b022 F2V8 (Net IDELAY=0) - fixed Samtec remap bug NV 2016-01-27 0 -- Note new version number -- the lower 3 nibbles are now common across all boards ---- NV 2016-01-26 b054 FIB_STD Inverted all FMC signals - seems the FMC-IB pinout is swapped :-( NV 2016-01-26 b053 FIB_STD Added INVERTS register (#48) NV 2016-01-16 b021 F2V8 (Net IDELAY=0) NV 2016-01-15 b020 F2V8 (Net IDELAY=7) NV 2016-01-15 b01f Netloop+CS IDELAY=19 NV 2016-01-15 b01d Netloop+CS IDELAY=7 NV 2016-01-15 b01d Netloop+CS IDELAY=0 NV 2016-01-15 b01c Netloop+CS IDELAY=11 NV 2016-01-13 b015 Netloop+CS JA-0: rxc, 1: clk125, 2: clk125_90 NV 2016-01-13 b014 Netloop+CS no timing shift, clk125s on JA NV 2016-01-13 b013 Netloop+CS shifted rx timings 24 steps NV 2016-01-13 b012 Netloop+CS shifted rx timings 8 steps NV 2016-01-13 b011 Netloop+CS shifted rx timings 16 steps NV 2016-01-13 b010 Netloop+CS NV 2016-01-12 b00f F2V2 NV 2016-01-12 b00e Net loopback only ... NV 2016-01-12 b00d F2V2 with chipscope NV 2015-12-22 b00c F2V2 changed default OPHASE NV 2015-12-22 b00b F2V16 more of the same (but a silly ver!) NV 2015-12-21 b00a F2V2 rebuild on laptop after much SVN shenanigans NV 2015-12-21 b009 F2V2 some ABCN (mostly) triggering mods NV 2015-12-18 b008 F2V16 version with 16 links (no PMODs) NV 2015-12-11 b001 1st version with Ethernet, no DIOs yet NV 2015-12-10 b000 Happy birthday to me ATLYS 2015-12-04 a0ba DRV phase control on DXouts - see reg 34 - OPHASE_DX HSIO 2015-12-01 443a slight changes to outsigs HSIO 2015-12-01 4439 updated to latest HSIO build, ALSO, new:- Has the new stream delay option as per '130 (streamconfig 14:12) - BUT BUT IDELAY is not changed ATLYS 2015-10-30 a0b9 IDC130_TLU TLU disables TDC when disabled ATLYS 2015-10-29 a0b8 IDC130_TLU L0ID in data stream timestamps ATLYS 2015-10-23 a0b7 ABCN_TTC ATLYS 2015-10-23 a0b6 ABCN_TLU stream status readback fix ATLYS 2015-10-22 a0b5 ABCN_TLU ATLYS 2015-10-22 a0b4 ABCN_TTC added other ext-triggers to the LED (pre=enables) ATLYS 2015-10-22 a0b3 ABCN_TTC ATLYS 2015-10-22 a0b1 ABCN_TLU * ATLYS 2015-10-22 a0b0 ABCN_TTC * ATLYS 2015-10-21 a0ae IDC130_TLU Timeouts now programmable by reg 32: RO_FIFO_TO. defaults to 50KHz (no change) ATLYS 2015-10-21 a0ad IDC130_TLU reverted back to faster packet fill timeout ATLYS 2015-10-21 a0ac IDC130_TLU reverted oc_dtack_n resolution (no more if 'Z' ...) WORKS! ATLYS 2015-10-21 a0ab IDC130_TLU *data packet fill timeout changed: 10x longer ATLYS 2015-10-21 a0aa IDC130_TLU *has outgoing phase offset compile option (no change, though) ATLYS 2015-10-19 a0a7 ABCN_TLU * ATLYS 2015-10-19 a0a6 ABCN_TTC * HSIO 2015-10-19 4437 added more TLU sigs to debug pins, fixed tlu_trig LED HSIO 2015-10-19 4436 proper phase compensation to match Atlys HSIO 2015-10-19 4435 Inverted BCO on IDCs to match Atlys phase HSIO 2015-10-16 4434 code re-org to match Atlys, added fine delay on IDC outgoing signals too ATLYS 2015-10-15 a0a4 IDC130_TTC * ATLYS 2015-10-15 a0a3 ABCN_TTC * ATLYS 2015-10-15 a0a2 Further fixes for stream config readout, TLU TDC inhibit for trigger number "triggers" ATLYS 2015-10-14 a0a1 Fixes for stream config readout (not) ATLYS 2015-10-14 a09e Added more debug tlu lines ATLYS 2015-10-14 a09d IDC_TLU fixed dropped packet count ATLYS 2015-10-13 a09b CHS1 Jaya John (Oxford) build - well tested and working ATLYS 2015-10-10 a09c IDC_TLU added extra trigger data (TDC etc) - rejigged format a little: see twiki ATLYS 2015-10-10 a09a CHS1 fixed fifo_ack_gen ATLYS 2015-10-08 a099 CHS1 added special functions (e.g. sync reset) ATLYS 2015-10-07 a098 CHS1 Includes Rui's start on SPI on TWOWIRE channels 1,2 ATLYS 2015-10-06 a097 CHS1 first attempt ATLYS 2015-10-06 a096 IDC130 fixed d008 format =2 ( was 1??? :-) ) Updated trigger code to log l0id asap, and added ts to tlu data ATLYS 2015-09-25 a095 IDC130 fixed d008 format =1 (was 2???) ATLYS 2015-09-25 a094 IDC130 fixed dead clock from nor 320_lock bug ATLYS 2015-09-24 a093 IDC130 640mb data deser, fixed 2x160 demux ATLYS 2015-09-22 a092 IDC130 reg/stat bugfixes ATLYS 2015-09-22 a091 IDC130 new 640Mb serialised COM. increased reg, statblock ATLYS 2015-09-21 a090 IDC130 with 10x faster timeout for packet filling ATLYS 2015-09-21 a08f IDC130 (same as 8d below, but not accidently overwritten!) ATLYS 2015-09-18 a08e PANEL ( part of test below - for comparison) ATLYS 2015-09-18 a08d IDC130 (test to check logic utilisation) ATLYS 2015-09-07 a08c ABCN ATLYS 2015-09-07 a08b DRV Fixed OC_ECHO not working ... ATLYS 2015-08-07 a08a DRV Fixed DRV line assign bug (tmu_com_invert) ATLYS 2015-08-06 a089 DRV ATLYS 2015-07-31 a088 IDC with buttons working properly ATLYS 2015-07-17 a083 ABCN ATLYS 2015-07-17 a082 IDC with btnC = send Status, btnU = send regblock ATLYS 2015-07-07 a080 IDC updatd arch version: cx, packet xoff, etc HSIO 2015-07-07 4430 first outing of new CX firmware, packet level xoff, dropped packet counter ATLYS 2015-06-26 a07c ABCN build ATLYS 2015-06-11 a07b IDC build ATLYS 2015-06-11 a07a DRV fixed double counting in PMOD_TTC TRIG_2 ATLYS 2015-06-11 a079 DRV updated pkt detect looking for 65b with 01xxxxxxxx... ATLYS 2015-06-11 a078 DRV rebuild with some some muxing changes reverted ATLYS 2015-06-11 a077 DRV unswapped PMOD_TLU trig and busy outputs ATLYS 2015-06-11 a076 DRV fixed 25ns busy generated when busylen set to 0 (no CX) ATLYS 2015-06-09 a072 Back to clock crossing firmware - better for debugging (oops same ver) ATLYS 2015-06-09 a072 Trial with clock crossing (CX) firmware - better for debugging ATLYS 2015-06-08 a071 DRV build ATLYS 2015-06-03 a06e IDC-PTTC Robusterised the stream fifos against overflow tried to make a smarter passive mux enabled all 1s packet un-detect ATLYS 2015-06-02 a06c IDC-PTTC removed clock crossing logic ATLYS 2015-06-02 a06b IDC PMOD-TTC fixed tdc readout ATLYS 2015-06-02 a06a IDC PMOD-TTC with input trig counters ATLYS 2015-06-01 a066 IDC PMOD-TTC integration - I2C in, rest is still in-progress (there, but ..) ATLYS 2015-05-28 a064 IDC New structure - clock segregation - should function the same ATLYS 2015-05-20 a05d DRV 40MHz readout mode added ATLYS 2015-05-19 a05c ABCN lots of debug outputs added - see twiki HSIO 2015-05-13 4423 fixed TDC no-command bug HSIO 2015-05-07 4421 fixed IDC mapping bug ATLYS 2015-05-06 a059 IDC TLU sigs on VMODIB D12,D13 ATLYS 2015-05-06 a058 IDC rebuild with latest TLU and trigger mods HSIO 2015-05-06 441f refixed TDC data align, killed spurios TLU_tclk HSIO 2015-04-28 441d fixed TDC status register entries HSIO 2015-04-28 441c moved TDC to top level - fixed TDC inputs bug HSIO 2015-04-27 441b moved TDC to top level, updated tlu/tdc ids to be more robust changed trigger paths with delay at end of chain HSIO 2015-04-16 441a TDC included build ATLYS 2015-04-13 a057 DRV fixed header detect bug - MAY work ATLYS 2015-04-09 a056 ABCN shows nice signs of life ... ATLYS 2015-04-08 a055 DRV ATLYS 2015-04-08 a054 ABCN (not working!) ATLYS 2015-04-03 a053 IDC. Modified ISERDES2 generics (MODE=RETIMED, WIDTH=4) Seems to work on new Atlys'!! ATLYS 2015-03-25 a050 IDC. Debug outputs: D4-5=delayed D0-1; D8-11=demuxed D0.0,D0.1,D1.0,D1.1 ATLYS 2015-03-25 a04c IDC Added Driver controls, but they don't quite work ATLYS 2015-03-23 a049 IDC Fixed no OUTSIGs bug. HSIO 2015-03-23 4417 added MAC address filtering on if0 - it was off!! HSIO 2015-03-23 4416 build - added sim lines - disp works (don't know why :-( ) ATLYS 2015-03-20 a047 Driver build of recent FW. Includes TLU, busy etc. as mentioned below HSIO 2015-03-20 4414 build - rebuilt for sanity HSIO 2015-03-14 4413 build - fixed mapping bug ATLYS 2015-03-13 b03d Variable busy length - see reg 10. TLU trigger number recieve control, see reg 31 *** NOTE: TLU controls from reg 19 MOVED to reg 31 *** HSIO 2015-03-13 4412 build Variable busy length - see reg 10. TLU trigger number recieve control, see reg 30*** NOTE: TLU controls from reg 19 MOVED to reg 31 *** ATLYS 2015-03-05 a037 busy changed back, added lu_trig and tlu_clk to MBCSV1 lemos ATLYS 2015-03-05 a036 Busy changed to make sync ATLYS 2015-03-05 a035 TLU sigs inverted (good with PMOD-bodge) ATLYS 2015-03-05 a034 TLU sigs un-inverted ATLYS 2015-03-05 a033 TLU sigs inverted with LEDs ATLYS 2015-03-04 a032 CMOS TLU HSIO 2015-02-13 440f HSIO 2015-02-13 440e Changed packet fifo to not preload opcode HSIO 2015-02-12 443e Makefile build HSIO 2015-02-08 443d Added sysreg ext clock selection HSIO 2015-02-08 443c Added sysreg stuff, with high-level resets HSIO 2015-02-06 440c Increasetimestamp timeout x8 (i.e. "empty" net-packet fills in 3ms, was 400us HSIO 2015-02-06 440b fixed ab c mode capture and mode80 capture HSIO 2015-02-04 440a shifted ABC mode data a by a bit HSIO 2015-02-02 4409 changed HCC-ABC bit mapping - looks good in sim now HSIO 2015-02-02 4408 changed HCC bit mapping HSIO 2015-02-02 4407 fixed dead capture bug HSIO 2015-01-30 4406 remapped HCC data format decoder, fixed capture mode to not be HCC/ABC mode dependent HSIO 2015-01-23 4405 rejigged capture, look good in sim. attemped an HCC data format decoder ...Fixed ABC data offset bug (I think) HSIO 2015-01-20 4404 Added opcode-start signal in P5 HSIO 2015-01-09 4403 Can invert COM on Driver using bit 6, reg_drv_conf HSIO 2015-01-08 4401 HCC option added ... HSIO 2015-01-07 443b Added output signal delay controls via reg 11. 0xdcba d:DCLK c:RESET, b:L1R, a:COM ATLYS 2014-11-14 a02a MBH35 with serout ATLYS 2014-10-28 a029 DRV ATLYS 2014-10-28 a028 MBH35 Err ... now it really works ATLYS 2014-10-28 a027 MBH35 fixed trailing zero bug (again!) ATLYS 2014-10-28 a026 MBH35 modified packet handling (fifo half-empty check) HSIO 2014-10-23 4400 Top + Bot build UNTESTEDanged pinout to Driver, use with driver fw >= d040 ============= ATLYS 2014-10-20 a025 DRV proper decoder this time! even works! ATLYS 2014-10-17 a024 DRV rebuild ATLYS 2014-10-14 a023 MBH35 deser in place, sim says it works ATLYS 2014-10-14 a022 MBH35 fixed rawsigs sync too ATLYS 2014-10-13 a021 MBH35 first attempt at deser ATLYS 2014-10-13 a020 MBH35 20MHz RAWSEQ sync. CKFAST invert option ATLYS 2014-10-09 a01f MBH35 20MHz BCO option (reg16,10) ATLYS 2014-10-09 a01e CMOS aka MBH35 - no packet decoding yet ATLYS 2014-10-07 a018 DRV ATLYS 2014-10-02 a017 CMOSversion – MAC address now e0:dd:cc:bb:0n, n ser by sw(3:0) ATLYS 2014-10-01 a016 At last a log is born HSIO 2014-08-21 438e As perprevious, but with streams this time ;-) HSIO 2014-08-15 438d Added Bottom Driver I2C ATLYS 2014-07-21 a000 birthday! HSIO 2014-07-04 4380 TLU Calib updated HSIO 2014-07-03 437f Added TDC TLU mode (reg 19. bit 14) HSIO 2014-06-27 437e reallyreally fixed no-ts bug HSIO 2014-06-27 437d reallyfixed no-ts bug + better TLU-IB led mapping HSIO 2014-06-27 437c fixed no-timestamp option for packetiser bug HSIO 2014-06-26 437b ABC130streams for top only - should be fine for TB HSIO 2014-06-26 4378 build with usual ABC130 streams, burster in TLU debug added, trigger data stream =144 HSIO 2014-06-26 4376 TLU interface with degug mode added. L0ID works now too (OUTSIGS =0x2222). Only2streams HSIO 2014-06-24 4371 TLU interface in a good state HSIO 2014-06-20 4369 ABC130packet filling with timestamp instead of zeros noteslightly modified data format: link-id is now "block type". see twiki HSIO 2014-05-29 435d Fixed RAWSIGS idle output to not set all others low during signal assert Reinstated old TDC calib, chaged clk switch clock to clk125 lemo_bco_out now uses DDR to regen the clock on the pin HSIO 2014-05-29 435c tdc foobed HSIO 2014-05-29 435b tdc with encoded output too HSIO 2014-05-23 434e tdc test run HSIO 2014-05-23 434d no streams - test for tlu IO HSIO 2014-05-12 434c Added TLU_MODE (CONTROL1, bit 11) - so far send short busy after each trig_ext HSIO 2014-05-09 434b fixed bugs in sigs decoder, encoder and counters. Looks good in sim. HSIO 2014-05-09 434a reworked trigger top layer and more: - no more OC_RAWCOM (0x101) - temporary removal triggered = pattern go option- BCR and ECR decoding from ABC130 CMD stream - OCRAW_START lemo changed to pretrig - ORs ocraw_start and undelayed non-raw/seq trigger source- Pretrigger stretch option added in CONTROL1, bit 9 - Status reg changed to look at 32b L0ID instead of 24b L1ID - Added L0ID_L1 status word - contains the last L0ID sent by l1_autogen HSIO 2014-05-08 4349 Added OC_COMMAND(ECR) as counter reset for l1_autogen HSIO 2014-05-08 4348 (yes, same version, oops!) Automatic L1s from L0s option: reg CONTROL1, bit 10 HSIO 2014-05-06 4348 Idle high option for RAWSIGs/SEQ HSIO 2014-04-29 4345 Added option to stretch trig_out pulse reg CONTROL1, bit 8First build with separate ocb and locallink libs HSIO 2014-03-31 4343 Removed BUFGMUX - it's syncrhonous, DOH DOH DOH! HSIO 2014-03-31 4342 Added DIFF_TERM for P5 ext clock input ... HSIO 2014-03-13 4341 Ready for new Driver schema bit HSIO 2014-03-13 4340 "improved" timing constraints ... functionally the same as 433c HSIO 2014-03-12 433c Fixed cyclic bug in sequencer HSIO 2014-03-10 433a 65MHz BCO capable!! Took >30m to build, so just a proof of principle for when we need it HSIO 2014-03-10 4339 50MHz BCO capable. Stable clock switching in place - see reg 0.Some LEMOs remapped: 1= Busy out, 2 = BCO out, 3=BCO in, 4=Trig inMore DCM status bits in statword 15. HSIO 2014-03-06 4332 External clock on LEMOs added - can select either Clocky via P2, or LEMO HSIO 2014-03-05 4331 Clockyfix - pin swaps on IDC conn. Works! HSIO 2014-03-04 4330 Clockybuild. Clocky didn't work. HSIO 2014-02-24 432f Swapped clock/r3 to Driver - needs updated Driver f/w (>0xd02b) HSIO 2014-02-21 432e Added bottom driver connection HSIO 2014-02-20 432d fixed deser machine for "odd" state HSIO 2014-02-20 432c REALLYChanged header trailer detect to H=0001,0 HSIO 2014-02-20 432b Changed header trailer detect to H=0001,0 HSIO 2014-02-12 432a ISE14!This build with HSIO-A13 HSIO 2014-02-07 4329 added clock board test on P2 pins, incl. ext_clk input HSIO 2014-01-30 4328 moved I2C IO blocks to top level HSIO 2014-01-30 4327 reverted to stave250 version on TWOWIRE HSIO 2014-01-29 4326 Changed ABC130 pkt packing timeout tick from 1KHz to 500kHz! HSIO 2014-01-28 4325 Changed ABC130 pkt packing timeout tick from 10KHz to 1KHz HSIO 2013-12-13 4323 Changed reg 18 mappings - see twiki, tidied some BUFGs to help build HSIO 2013-12-13 4321 Added TMU readback on link 20 (stream 40) HSIO 2013-12-11 4320 Fixed inverted RAWOUT_EN, Capture fixed (broke it when I fixed it last time) HSIO 2013-12-10 431f Fixed missing RAWOUT_EN bugMade capture start when NON in RAWOUT_EN mode and when new SCAN_EN bit rises HSIO 2013-12-09 431e re-worked Driver dx lines and seq to incorp ABC SCAN HSIO 2013-12-06 431c increased capture len to 10b = max 6 packets = 60kb = 7.6kB HSIO 2013-12-05 431b Re-Fixed Capture 60b bug - it's not a bug :-( HSIO 2013-12-05 431b Fixed Capture 60b bug, increased SEQ ram to 16kx16 HSIO 2013-12-05 431a Added capture_start on SCAN_EN HSIO 2013-11-29 4313 smarter header-trailer det - looks for 01 head and 0 trail - i.e 00FFFFFFFFFFFFFF isn't data! HSIO 2013-11-27 430f reverted to old tx_packet_format an tried a new ddr block for HSIO-A13 HSIO 2013-11-26 430e tryingto fix HSIO-A13 - failed HSIO 2013-11-24 430d Atlys single-chip version: Fixed channel stream assignments to match driver: 2=left, 14=right (or did I get that backwards) HSIO 2013-11-21 430b changed abc pkt head det to 01 (from 1) HSIO 2013-11-18 4307 8IH+HSIO-A13 + 4T. Moved IDELAY blocks to pins, reworked output blocks HSIO 2013-10-23 4303 8IH+HSIO-A13 - new sequencer and improved spy (see rawsigs option). Changes to some opcode handler mechanics - might be buggy Also noticed some incorrect packet lens - still looking ... HSIO 2013-10-11 41f2 16TH16BH possible tx CRC fix HSIO 2013-10-11 4300 Version jump - v42nn is being used by the stave250 branch HSIO 2013-09-30 41ed fixed CAL_EN register missing bug HSIO 2013-09-27 41ec moved the final ABC130 verilog. HSIO-A13, 1T A13+ FCF on B28-29 (120,122) - not seeming to work! HSIO 2013-09-19 41ea changed rx_packet_decoder to comply better with LL on the input - look out for CHOMPs!! HSIO 2013-09-18 41e9 HSIO-A13, 1T A13 HSIO 2013-09-17 41e8 HSIO-A13 only - now only stores source MAC when ethtype=0x876X - good for switch operation when more broadcast packets are expected HSIO 2013-09-13 41e5 16TH8IH - stavelet build HSIO 2013-09-13 41e4 ABC130test build HSIO 2013-09-11 41e1 *16TH16BH rebuild for Carlos with histos on top and bottom (NO IDC) HSIO 2013-09-07 41f0 16TH16BH - fixed short packet padding bug HSIO 2013-09-07 41ef 16TH16BH - hope it works Carlos - I've not tried it at all :-) HSIO 2013-09-06 41e0 *16TH8IH with external clock input on LEMO-J3. reg 0 = 0x100 to enable. HSIO 2013-09-05 41d9 *16TH8IH stavelet version with mutiple eth type support. Some opcodes may not work. Please report. HSIO 2013-08-29 41d8 fixed spy bug. ABC130 only version HSIO 2013-07-31 41d4 Fixed mux bug HSIO 2013-07-26 41cd same as 41cc, but with the muxed signals driving the HSIO-A13 - more realistic Works if mux_sel_inv is set - reg 23, bit 1 HSIO 2013-07-25 41cc 16T8I-A13 + HSIO-A13 -- with new mux and a mux sel invert bit (see control reg) HSIO 2013-07-25 41cb 16 Topstreams, 8 IDC streams, all ABC130 (16T8I-A13) + HSIO-ABC130FORGOT TO ADD THE COMLO and L1R3 muxes - fairly useless! HSIO 2013-07-24 41ca HSIO-ABC130 only HSIO 2013-07-22 41c9 +48T16B8IH - Everyone happy? HSIO 2013-07-21 41c8 16T16B8I - better for Carlos? HSIO 2013-07-21 41c7 48T8I - 1-wire for the stave HSIO 2013-07-21 41c6 16T16B- 1-wire for Sergio and Carlos too HSIO 2013-07-15 41c3 16TH8IH - Added I2C/1-wire controller on TWOWIRE ports 3,7 HSIO 2013-07-10 41be 2xABC130 only (on 124,126) 160MHz readout option - set reg 23 bit 2 HSIO 2013-07-09 41bb 16TH8IH - new option for sending DCS opcodes (TWOWIRE) on Eth-Type 0x8766 - reg 23,3 HSIO 2013-07-04 41b5 2xABC130 only (on 124,126) running at 80MHz readout. incl. single hit generator HSIO 2013-07-02 41b3 48T8I (no histo) - Go Peter go! HSIO 2013-07-02 41b2 1ABC130+8IH - chain of 2 abc130s on stream 124. abc130_test.cpp updated too. bug: no hits reported HSIO 2013-05-30 41ac 16TH8IHCleaned up SVN, added missing files and changed RAWSIGS to allow sending stave signals HSIO 2013-05-14 41ab 16TH8IHPlaying with compiling the ABC130 block and the readout block independently and including them as cores. HSIO 2013-05-14 41a8 added ext-trig debug outs HSIO 2013-05-01 41a7 16 top+ IDC (incl. histo) - added/moved some debug mappings HSIO 2013-04-26 41a6 16 top+ IDC (incl. histo) - fixed mode40 bug but there may be more ... HSIO 2013-04-24 41a4 16 top+ IDC (incl. histo) - fixed status and register readback bug HSIO 2013-04-05 419e 16 top, 16 bot (incl. histo) NO IDC HSIO 2013-04-05 419d 16 top, all IDC (incl. histo) fixed ext trigger bugs (>1!) - reworked ext trig edge detector, added more sync. Slight mod to status readback - might fix missing words bug. HSIO 2013-03-27 4194 16 top, 16 bot (incl. histo) NO IDC with added stream output debugs on P3 HSIO 2013-03-26 4192 16 top, 16 bot (incl. histo) NO IDC HSIO 2013-03-25 4191 fixed IDC BCO/DCLK swap. 16 top, 4 IDC (incl. histo) HSIO 2013-03-14 418d readout130 build for 12 modules double sided stave (no histo) HSIO 2013-03-14 418c fx100 build. top: all 48.idc: all HSIO 2013-03-11 4189 top: 16 raw, 48 histo. idc: all HSIO 2013-03-11 4188 top: 1raw, 2 histo. Added stream id in data correction HSIO 2013-03-11 4187 top: 16 raw, 32 histo. Use stream src 1 to switch to second raw set HSIO 2013-03-11 4186 First test with RAW multi stream mode HSIO 2013-03-11 4185 48 tophisto only, 0 bot, 4 IDC (with histo) HSIO 2013-03-11 4184 48 top(no histo), 0 bot, 4 IDC (with histo) HSIO 2013-03-08 4182 16 top, 16 bot, 2 IDC (incl. histo) HSIO 2013-03-08 4181 16 top, 4 IDC (incl. histo) HSIO 2013-02-28 417c Stavelet top and bottom + 1 IDC (the second one) HSIO 2013-02-28 4180 Stavelet + IDCs - has optimally phased trigger window option HSIO 2013-02-27 417a Moved output block to top level BCO/DCLK output drivers changed - now using DDR buffers Added primative trigger window - enable reg 23.9, adjust using 10:0 of reg 15 moved noise_en bit in control reg (now 23.13) HSIO 2013-02-08 416d 2 ABC130-chips HSIO 2013-02-05 416c ABC130-chip sending data HSIO 2013-01-29 4162 First iteration with ABC130 chip inside HSIO (stream 64)New opcode - RAWSIGs - for driving L0/L1/R3/COM signals HSIO 2013-01-02 4151 ABC130pkt formatting tidy, length optimised HSIO 2012-12-21 414b ABC130proto version. Readout for modules of ABC130 or ABCN type. Specify at build time.Only 1 data stream per ABC130 Module. Raw and capture modes. data gen works too,but needs enable via bit 5 in CONTROL reg HSIO 2012-11-29 413b fixed hysteresis code typo, added RAWCOM pattern go (which may not really work) HSIO 2012-11-12 4136 Added programmable busy_delta hi and low levels (aka hysterisis) - see reg 17Tidyied readout_top and ro_unit a little HSIO 2012-11-09 4135 changed structure to allow histos to be built without rawfifo option HSIO 2012-11-02 4132 busy bugfix HSIO 2012-11-01 4131 updated trig_decoder to skip over BCC headers - no more spurios trigger counts?? HSIO 2012-10-30 4130 fixed hd_delta stuck at max bug, added vbusy, added harder seq_reset HSIO 2012-10-29 412f REALLYreverted histo header change (for now) HSIO 2012-10-29 412e reverted histo header change (for now) HSIO 2012-10-29 412d changed deser (and ht_delta)header det from "12zero+11101" to 15zero+"111010" to try stop wrong counting. Added no-en reset to delta HSIO 2012-10-26 412c changed histo header det from "11101" to "000000000000011101" HSIO 2012-10-22 412b added lemo_trig_i invert option (See reg 3) HSIO 2012-10-02 412a improved ro_deser, fixed busy_en HSIO 2012-09-14 4129 fixed some timing inconsistencies with BCO vs DCLK. Removed EOS porch remapping option - it was broken anyway. HSIO 2012-08-23 4123 Rebuild using makefile generated .mcs (and .bit with CCLK) HSIO 2012-08-22 411f Added pullups to TWOWIRE ports HSIO 2012-08-22 4121 Added timestamp for make builds HSIO 2012-08-22 4120 Moved pullups to top level - ISE gets confused otherwise HSIO 2012-08-21 411e bug fixes in watchdog in TWOWIRE, and general tidying of oc_dack function,Added RESET_OCB opcode, not sure if it works yet In general HSIO is less likeky to hang-up. Stavelet build. HSIO 2012-08-17 4119 re-added the P2 Aux(12) TWOWIRE port(!) + 3 more (13,14,15) HSIO 2012-08-16 4118 re-build with makefile HSIO 2012-08-13 4117 moved some code around - new control_top to hide ocb sub-sys HSIO 2012-08-13 4116 22 module (88 stream) build. HSIO 2012-08-13 4115 SM Build HSIO 2012-08-10 4114 Stavelet build HSIO 2012-08-10 4112 added filter on magic_number, fixed watchdog too eager bug,removed 0xF080 opcode. HSIO 2012-08-10 4111 more bug fixing, 2 opcodes in an RX packet works for echo.fyi no streams in this build HSIO 2012-08-09 4110 Fixed some bug in back-to-back opcode handling and multi oc's per rx packet HSIO 2012-08-08 410f Multiple opcodes in an RX packet - untested - Stavelet Build HSIO 2012-08-08 410d Added buffer to TWOWIRE - no more delays, hopefully - Stavelet Build HSIO 2012-08-07 410c Added multi-channel in 1 packet option for TWOWIRE, Stavelet Build HSIO 2012-08-03 4109 Stavelet Build HSIO 2012-08-03 4108 fixed oc_dtack bug - tristates again - seems Z=1 - so now we have oc_dack_n HSIO 2012-08-03 4104 re-added all m_powers (only ones used - all the better for bug spotting) as pkg didn't work HSIO 2012-08-02 4102 removed all m_powers - doing from pkg.... HSIO 2012-08-01 4101 converted t_llsrc. ise just doesn't do well with tristates HSIO 2012-07-31 4100 converted all ll to t_llbus. Removed all set to zero if not in build generates HSIO 2012-07-30 40ff Reworked oc_dtack line to be bussed (pseudo open-collector,even more pseud as XST makes a wide-as-needed OR gate which is what I wanted in the first place) HSIO 2012-07-25 40fe OCSEQ fix - no more gaps - 16TH+8PH HSIO 2012-07-23 40fd Build with Bruces proc DDR pins now attached - 16TH+8PH HSIO 2012-07-23 40fc Another CRC config error fix (not as much hope as before) - 16TH+8PH HSIO 2012-07-23 40fb CRC config error fix - HOPEFULLY. Added Bruces proc wrapper. HSIO 2012-07-18 40fa working TWOWIRE, but no streams (£$%^& CRC says NO on conf problem is back). HSIO 2012-07-17 40f9 changed SHT case handling - just might fix weird bug. Added wdog_clr for each word. HSIO 2012-07-17 40f8 increased bad OC timeout to ~1s to be MUCH longer than serial timeout HSIO 2012-07-17 40f7 fixed missing TWOWIRE word bug HSIO 2012-07-17 40f6 invalid opcode watchdog confirmed working now. HSIO 2012-07-16 40f5 (re)added invalid opcode watchdog, fixed unassigned busys HSIO 2012-07-13 40f4 (16TH,8IH) mode40, robuster header-det, more reset options (netrx/tx),re-added net statwords. fixed TX data MAC address, now not 0x0000. All untested. HSIO 2012-07-05 40ea (16TH,8IH) Display fixed and TWOWIRE now supports SHT and I2C. See twiki. HSIO 2012-06-25 40d8 Work on fixing display. Note slow_ticks_gen.vhd move from utils lib to hsio to allow use of pkg_hsio_globals.vhd HSIO 2012-06-22 40d6 Slightly changed TWOWIRE command format (sorreeee) HSIO 2012-06-18 40d0 Stavelet build (16T+H, 8I+H) with the SHT71 too - see opcode 0x80 HSIO 2012-06-13 40c2 Stavelet build - 16 top + 8 IDC streams with histo -this isn't meant for playing with the SHT71 HSIO 2012-06-13 40c1 fixed SHT71 status reads (the $%^& chip doesn't work like the datasheet says!!!!!) HSIO 2012-06-12 40b8 added ocfifo full checking to rx_packet_decoder.if full incoming packet will not be processed and an ack with oc=0xaaff will be sent. If full during processing rx will hang until it's clear, probably triggering a bark HSIO 2012-06-11 40b6 TWOWIRE: work progresses forwards and backwards. 40b4 worked, 40b5 not ... HSIO 2012-06-08 40ad TWOWIRE: improved fifo handling HSIO 2012-06-08 40ac reverted to matts net_tx_pktfmt16 - bruces version has 2 CRCs HSIO 2012-06-07 40ab New SHT71 block, with possible i2c option HSIO 2012-05-29 40aa added SHT71 control block - opcode 0x80 - much debug trialing HSIO 2012-05-25 40a5 Added pattern sending (see opcode 0x70), enabled in control_reg HSIO 2012-05-24 40a4 Added fifo levels read-back, more stream status words, stream busys,pkt decoder respects size (ECHO is now correct!), reworked rx_packet_decoder_tb HSIO 2012-05-17 40a3 Debug outs rework - P4 moved to P5, P2,3,4 now unused. HSIO 2012-05-16 40a2 SM build - 32 top, 32 bot, 0 IDC, histos a not go. HSIO 2012-05-16 40a1 Stave build - 16 top, 8 IDC, histos a gogo. So far it seems good! HSIO 2012-05-16 40a0 ocrawcom_start set back to 12ns - messed up internals a bit HSIO 2012-05-16 409f ocrawcom_start now syncd and stretched to 25ns HSIO 2012-05-15 409e Seems to work, but ocrawcom_start has a glitch HSIO 2012-05-15 409d Yeeeks- somehow lost dbg_oe. test build with just IDCs, no histos ... HSIO 2012-05-14 409c Rebuild for SM - with 32 top, 32 bot, WITHOUT histo HSIO 2012-05-14 409b Rebuild for Stave - with 16 top, 8 IDC streams, WITH histo HSIO 2012-05-11 409a Yes, ANOTHER packet building bugfix in ro_deser, but this time it's working! HSIO 2012-05-11 4099 ANOTHER packet building bugfix in ro_deser HSIO 2012-05-11 4098 Another packet building bugfix in ro_deser HSIO 2012-05-11 4097 Robusterisation of case where trailers are very close to header (aka while pkt header is being sent) HSIO 2012-05-11 4096 Bug inerror packet sending another error packet and overflowing len fifo fixed HSIO 2012-05-11 4095 added len_fifo full checking (doh! to have missed it) -hopefully we are completely ROBUST now HSIO 2012-05-10 4094 48 streams HSIO 2012-05-10 4093 added ocb bus fifo after packet decoded to decouple net_tx from net_rx HSIO 2012-05-09 408f changed fifo-full tcs16(15 downto0) <= cs(31 downto 16); cs16(63 downto 16) <= (others => '0'); cs16(79 downto 64) <= cs(95 downto 80); cs16(135 downto 80) <= (others => '0'); o send NOTHING, fragments to go no more than 1, and indefinite wait for trailer after TRAILER_TO error HSIO 2012-05-09 408e Re-build for deser-fifo test - very few streams HSIO 2012-05-09 4092 changed to 48 streams, it worked! HSIO 2012-05-09 4091 dropped-packets-count added to second word of stream status packet --WON'T CONFIG - THAT $%^&* CRC ERROR! HSIO 2012-05-09 4090 fixed E/F packet labelling bug HSIO 2012-05-08 408d Re-build for SM mapping with 32 top (0-31) and 32 bottom streams(64-95) (no histos, no IDC) HSIO 2012-05-01 408c Build for Stave with IDCs HSIO 2012-04-20 408b Build for SM mapping with 32 top (0-31) and 32 bottom streams(64-95) (no histos, no IDC) - DIDN'T WORK HSIO 2012-03-08 408a Added external trigger input on LEMO-1, has input enables,synchroniser and prog delay, see in/out/int enable and tdelay registers HSIO 2012-03-08 4088 4086 for supermodule:stream enables (no histos): Top: 0-31, Bottom 8-40, all IDC HSIO 2012-03-05 4087 4086 for supermodule:stream enables (no histos): Top: 0-31, Bottom 16-47, all IDC HSIO 2012-03-02 4086 Found problem with autosmx, reverted to automux HSIO 2012-03-02 4085 Fix totx_pktfmt to remove spurious crc from end of data in short packets HSIO 2012-03-01 4084 Moved to stream block (top, bot, pp) separated modulo 64 HSIO 2012-02-29 4083 Movingto module build enables (was streams),optimised ro_fifo len_fifo - saves a good few FFs HSIO 2012-02-29 4082 Added Toms simulated data generator HSIO 2012-02-28 4081 another go at this. fx60: 16+8+8+histos, fx100: 104, no histos, removed network .ucfs HSIO 2012-02-28 4080 still got resource problems - made ro_unit automux synchro too HSIO 2012-02-27 407f top level of mux now synchro (= 64*20 extra flips flops),but should help reduce LUT usage, timing HSIO 2012-02-27 407e seems to work, re-enabled debug outputs.building 20+20+8, with histo. didn't fit HSIO 2012-02-27 407d NO DEBUG outputs. Added capture start on trigger mode - R_CONTROL, bit 12, 48+8 streams, no histo HSIO 2012-02-24 4078 Added register to output of tx_pkt_format HSIO 2012-02-24 4077 build with no histos 24 and 96 stream HSIO 2012-02-24 4076 removed async resets from histo files HSIO 2012-02-23 4075 removed additional bufg from clk40 chain, building for 32 with histo HSIO 2012-02-23 4074 bugfix- synxmux (the ONLY func change from pre-record versions) broken HSIO 2012-02-23 4073 separated dst_rdy from rest of record - xil don't di bidir records too well HSIO 2012-02-22 4072 reworked some of the ll busses to use records instead, no funcionality is supposed to change HSIO 2012-02-21 4071 Tieredthe resets to each top block via FFs, added "Cross Clock Analysis" XST option,and "Optimised Across Hierachy: Speed" Map option HSIO 2012-02-20 406f Added new networking .ucfs, rebuild with histos HSIO 2012-02-20 406e removed srcrdy fix (see v406c) - xil ll seems to ignore SOF! HSIO 2012-02-20 406d re-added reset command to inidividual streams - was missed out on all except histo, reordered capture mode checking in ro_deser - stops real data being used in capture mode HSIO 2012-02-20 4070 Added seperate resets via ocb_command HSIO 2012-02-17 406c src_rdy bug-fix in txfmt - building with 16 str, no histo HSIO 2012-02-17 406b moved to bram fifos and put IDCs on streams 32-39, always there, always with histo. HSIO 2012-02-16 406a rebuild with 32 streams and 32 histos. failed timing by 260ps! HSIO 2012-02-16 4069 removed eth statmon blocks, pause controller, build 16 str, no histo HSIO 2012-02-15 4068 reverted to newer mux HSIO 2012-02-15 4067 tryinglower speed grade -10 HSIO 2012-02-15 4066 tryingold syncmux from 310d to fix missing packet bug HSIO 2012-02-13 4065 changed spysig stream-id to 0xF0, fixed tb seq_reset stretch bug HSIO 2012-02-13 4064 removed clocks from sink bus - they cause timing foobars, and no need to look at them HSIO 2012-02-10 4063 first build with spysig stream added HSIO 2012-02-01 405e rebuild with fanout=100000 for XST HSIO 2012-01-31 405d same version AGAIN - rebuild for sanity check AGAIN (at UCL cluster) HSIO 2012-01-30 405c same version - rebuild for sanity check (on laptop) HSIO 2012-01-27 405c Fixed trig80 no connected to fake-data gen, removed latches from mux,played with planAhead, tidied st/unix/local/xilinxate machine logic HSIO 2012-01-02 4062 strobe40 not connected to triggertop bugfix, removed redundant BCO DCM - untested! HSIO 2012-01-02 4061 reg order bug-bug-bug fixed with a new reg type HSIO 2012-01-01 405f reg order-bug fixed HSIO 2012-01-01 4060 reg order bug-bug properly fixed HSIO 2012-01-01 4059 Rebuild in 2012. Initially 4 stream, then 32 - Does NOT have CRC error! HSIO 2011-12-14 4058 Added burster counts to status. removed enables for l1/bcid counting.added hsio l1/bcid reset commands HSIO 2011-12-14 4057 added new trigger_top, with burster, and improved signal path. Added oc 0x30 - COMMAND for sending pulses. Remapped dbg pins to be same as per sergio. changed muxs for bce sel to BUFGMUXs. HSIO 2011-12-05 4056 moved STREAMS_EN, HISTOS_EN, BUILD_NO to pkg_hsio_globals.vhd HSIO 2011-12-01 4055 histo trailer len fix HSIO 2011-11-25 4054 removed stream overflow detection -- too painful HSIO 2011-11-24 4053 fixed another oc 0x50/5c bug - reverted sma dbg connections HSIO 2011-11-22 4052 fixed oc 0x5c bugs, incl invalid stream detect HSIO 2011-11-11 4051 same but with version correct, and dbg pins oe reinstated HSIO 2011-11-09 404f moved bot streams from 23-16 to 15-8 HSIO 2011-11-09 4050 added stream debug lines HSIO 2011-11-08 404e fixed bot bco/l1r swap HSIO 2011-10-25 404d Added opcodes Bcast Stream Config/Command HSIO 2011-10-24 404c Extending stream wr/cmd opcodes for multiple streams/packet HSIO 2011-10-06 404b Started to add slow readout mode (using DCLK=40 setting) option for data muxed at 40MHz HSIO 2011-09-22 404a re-mapped enables for EOS-porch too. Signal P4 dbg outs look good on scope/LA now HSIO 2011-09-22 4049 fixed buf (no "lo") in fe_sigs_out HSIO 2011-09-21 4048 added new/consistent debug signals for ST/PP outputs on P4 HSIO 2011-09-19 4047 changed i2c to include channels and longer timeouts HSIO 2011-09-14 4046 reworked (duplicated) COM timing ffs HSIO 2011-09-13 4045 added timeouts to I2C HSIO 2011-09-10 4044 remapped bottom to start from the other side HSIO 2011-09-10 4043 added eos bottom connections for 16+16, added oc 0x42 for bottom temp readout HSIO 2011-08-08 4042 using optimised big mux HSIO 2011-08-08 4041 Improved rst clocking, Tom histo with Toms optimisations HSIO 2011-08-05 4040 Back to Alex's histo, with same fixes as tom's HSIO 2011-08-05 4030 Toms histo with reworked data readout, some reset fixes easier timing, modified automux, more tigs - even on reg_mon_en and reg_control HSIO 2011-08-03 4020 Tom's histogrammer HSIO 2011-08-03 4010 32/32 streams attempt. HSIO 2011-08-03 4000 NEW NUMBERING! HSIO 2011-07-29 2071 Added "automux" in ro_unit HSIO 2011-07-28 2070 Rebuild with renamed mux items HSIO 2011-07-25 2069 Fixed rx_pktfmt16 HSIO 2011-07-25 2068 ISE13.2!! HSIO 2011-07-25 2067 reworked rx_pktfmt16, added debug for rx_data HSIO 2011-07-22 2066 Integrated Errdems 16b Network interface, with pre-ll mux on the sfps HSIO 2011-07-21 2065 rebuilt AGAIN due to file corruption HSIO 2011-07-19 2064 rebuilt twice after some Xilinx Impact CRC errors HSIO 2011-07-19 2062 fixed EVEN ANOTHER ibpp mapping bug HSIO 2011-07-18 2061 fixed ANOTHER ibpp mapping bug, defaulted stream regs to 0 HSIO 2011-07-18 2060 fixed streams_cmd bug HSIO 2011-07-15 205f 4 streams defaulted to enabled, capture mode HSIO 2011-07-15 205e new schema 32 stream build (!!) HSIO 2011-07-14 205d fixed ocb_streams oc_dtack bug, removed all checksum HSIO 2011-07-12 205c modified crc to be at end of data and count type too HSIO 2011-07-08 205b added crc HSIO 2011-07-06 205a fixed ibpp sigs being mapped to nowhere bug HSIO 2011-07-04 2059 tidying, moved ibpps around, no new features HSIO 2011-06-30 2058 moved ack fifo blocks into ocbs HSIO 2011-06-28 2057 simplified clk_main timings, extra TIGs on clk_ready sigs, copper rx_clk HSIO 2011-06-27 2056 streamswap fix HSIO 2011-06-24 2055 secondsfp+ working, added 'leds' onto display HSIO 2011-06-17 204b fixed bco duty cycle, moded temp readback to send early net-ack. HSIO 2011-06-14 2046 fixed reset bug HSIO 2011-06-08 2041 even smarter spiser (no half clk), small echo fix HSIO 2011-06-08 2040 smarter spiser HSIO 2011-06-07 203e fixed minor bug in 0x101, 0x105 init state oc_valid handling HSIO 2011-06-06 203d echo and spi opcodes added, improved but not brilliant deser erroring HSIO 2011-05-25 203c updated ocb handling HSIO 2011-05-25 203b added status and temp readback HSIO 2011-05-23 203a register readout testing HSIO 2011-05-19 2039 added sf/rj45 network autoswitch HSIO 2011-05-17 2038 timeouts on unrecog opcodes HSIO 2011-05-12 2037 start of new opcode schema + confable sf map HSIO 2011-03-02 2036 reworked ro fifos for single clock HSIO 2011-02-22 2035 rebuild with bco_dc improved HSIO 2011-02-14 2033 First of the unified clocks ... HSIO 2011-01-31 2032 Added clk_idelay debug output HSIO 2011-01-27 2031 back to 180Mhz idelay HSIO 2011-01-27 2030 back to 200Mhz - sanity check HSIO 2011-01-27 2029 added better debug, and some streams HSIO 2011-01-26 2028 changed IDELAYCTL clk to 160MHz HSIO 2011-01-26 2027 start of 2011 work build HSIO 2010-11-30 2024 resetsAGAIN + eofin wrong clock fix HSIO 2010-11-29 2023 reverted to FIFO16 in ro_unit_fifo HSIO 2010-11-28 2020 clockssig rename, slight re-org of clk40 HSIO 2010-11-25 201e re-worked resets AGAIN HSIO 2010-11-25 201c re-worked resets AGAIN HSIO 2010-11-24 201b Added reset counters for debug HSIO 2010-11-23 201f 16 stream build HSIO 2010-11-23 201a reset bug fix again HSIO 2010-11-23 2019 reset bug fix HSIO 2010-11-23 2018 rebuild with 16 streams HSIO 2010-11-23 2017 reworked resets and fifos HSIO 2010-11-22 2016 debug en fix HSIO 2010-11-22 2015 capture mode fix, reworked eof det AGAIN HSIO 2010-11-21 2014 using hsio sff(instead of ib), debugs disableable, ibe_oscs inputs. crude noise out en... HSIO 2010-11-19 2013 added switch to PP option HSIO 2010-11-19 2012 remapped PPs to hyb-str 0-3 HSIO 2010-11-19 2011 header/trailer fix, histo fix++ + all the fixes from the non-eos ... HSIO 2010-11-15 2010 new ver numbering 2 in 2010 = C02 with EOS HSIO 2010-11-02 300f reworked capture and histo chomp fix. UNTESTED HSIO 2010-11-01 300e improved order of temp readout packet - may take longer, though. HSIO 2010-10-05 300d rebuild of above, because there may be confusion HSIO 2010-10-03 300c +37.5 MHz clkfx version, use ext_clk_en (hexsw=5) to select HSIO 2010-09-25 1000 added bco duty cycle control, 8 steams, 0 histos HSIO 2010-09-24 3200 32 stream build HSIO 2010-09-24 1500 fixed possible deltaeof overflow. priorised ack stream. HSIO 2010-09-23 2000 re-added ti2c, high hopes HSIO 2010-09-19 1700 16 streams - fixed reset HSIO 2010-09-15 300b unbuilt version with ti2c mods etc. for svn HSIO 2010-09-15 300a fixed ti2c state machine HSIO 2010-09-15 3009 added led flash on ti2c_req, parser fix HSIO 2010-09-15 3008 ti2c rework and more debug HSIO 2010-09-15 3007 ti2c quick fix (or not) with debug HSIO 2010-09-15 3006 histo quick fix (or not) HSIO 2010-09-15 3005 24 channel ti2c HSIO 2010-09-14 3004 ti2c wordstart now on debug output HSIO 2010-09-13 3003 enabled ALL stave streams, doh! HSIO 2010-09-13 3002 fixed pin swaps HSIO 2010-09-13 3001 same with 16st/0his HSIO 2010-09-12 3000 re-worked flow control even more - looks good in sim HSIO 2010-09-11 1200 16 streams - 4 stave hyb, 4 pp hyb HSIO 2010-09-11 1000 removed oc len change, added pullups for i2c sda lines HSIO 2010-09-10 1700 trial with changed oc len. HSIO 2010-09-10 1500 working version. HSIO 2010-09-10 1400 last recompile worked. add(ing/ed) new reset idea. HSIO 2010-09-07 3 re-worked flow control (!) HSIO 2010-09-07 2 empty pkt handling fix HSIO 2010-09-06 1000 first build with new fifo no-overflow, error packets etc HSIO 2010-09-06 1 idelayfixes HSIO 2010-08-10 700 now using stave T for top signals HSIO 2010-08-10 700 insane! HSIO 2010-08-10 700 removed i2c - sanity check HSIO 2010-08-09 1600 moved stave to 0-3, reduced debug lines HSIO 2010-08-09 1400 stave 0-3 added (as 4-7) with own enables etc. HSIO 2010-08-09 940 i2c readback added - untested HSIO 2010-08-05 1000 readback improved HSIO 2010-08-04 2100 64 chan + readback HSIO 2010-08-04 1200 readback re-added, changed muxes on dclk/bco ... HSIO 2010-08-04 1100 readback removed - won't fit ... HSIO 2010-07-26 1600 Rebuild with all mods and in SVN HSIO 2010-07-21 1000 TimingIGnores on IDC debug signals HSIO 2010-07-20 1000 8 streams enabled HSIO 2010-07-15 1000 New EOS IB version HSIO 2010-07-13 1000 reduced histo-fifo to 1 register, corrected 2nd histo packet size problem HSIO 2010-07-07 1000 re-added duty cycle correction, added second datagen HSIO 2010-06-11 0 Rebuild of good firmware (aka 0xedball50) from 08/06/10 HSIO 2010-06-11 1200 removed duty cycle correction from BCO DCM - dclk enable replaced by bco invert option, better defaults - includes fixes from 09/06