Atlys Changelog - Covers Atlys specific changes Note: _H denotes histogrammer in the build ... * = Broken! (otherwise it only might be broken ;-) ) 11/12/2017 (va1df) CHESS2B_TLU Special version for Luigi again 24/01/2018 (va1de) IDC130_TLU_H MAC routing build 11/12/2017 (va1c9) CHESS2B_TLU Special version for Luigi with TLU enabled by default - And signals echoed on VMOD-CHESS2 debug outs 6/11/2017 (va1b1) VADAPT_TTC 25/10/2017 (va1a9) ABCN_TTC_PTRGO Down button sends a PAUSE packet. Hopefully ... 20/10/2017 (va1a5) ABCN_TTC_PTRGO Removed RAWCOM from com_decoder 20/10/2017 (va1a4) ABCN_TTC_PTRGO Added abcn command decoder to extract trigs from RAWSIGS and RAWCOM 12/10/2017 (va1a3) ABCN_TTC_PTRGO Improved CMDTRIG timing when DELAY=0 12/10/2017 (va1a2) ABCN_TTC_PTRGO ABCN PTrigOut 12/10/2017 (va1a1) IDC130_TTC_PTRGO_H Special build for Dennis to play with shortish pulses out of PMOD-TTC 3/10/2017 (va19f) IDC130_TTC_H Added build info to status 36: (15:8) RO_TYPE, (7:0) DIO_TYPE 8/09/2017 (va19e) IDC130_TTC_H Refresh 21/07/2017 (va193) DRV_TTC Refresh 19/07/2017 (va191) VADAPT_TTC Refresh 30/05/2017 (va17d) IDC130_TLU_H ROTOHRO mode added 16/05/2017 (va17a) IDC130_TLU_H Fixed bug in com/l1r output 15/05/2017 (va179) VADAPT_TLU_H * 15/05/2017 (va178) IDC130_TLU_H *Histos on! 27/04/2017 (va16a) VADAPT_TLU TLU build, no other changes ... 10/02/2017 (va118) VADAPT Undid reversed reg init values bug ... 9/02/2017 (va116) VADAPT Added inverts for streams (strm_reg) and outputs (reg INVERTS) 24/01/2017 (va115) ABCN_TTC ABCN rebuild with SPYSIGS re-added 24/01/2017 (va114) MAD12 Attempt to get more links for Carlos. Failed on 3 constraints!! 22/12/2016 (va113) CHS2 re-inverted saci-clk to be correct, as was originally done (sorry :-( ) 22/12/2016 (va112) CHS2 CHESS-2 SACI loop removed, expected to work with real thing :-) Merry Christmas!! 22/12/2016 (va111) CHS2 CHESS-2, more SACI logic fixes - saci cmd loop to resp back via internal pipeline 21/12/2016 (va110) CHS2 CHESS-2, add 40MHz clock to CHESS-2 + SACI logic fixes 16/12/2016 (va10f) CHS2 CHESS-2, first build for testing 26/ 9/2016 (va10e) VADAPT Peters new board, with 26/ 9/2016 (va10d) IDC_PRNG3 PRNG on D13-15 21/ 9/2016 (va10c) IDC_PRNG PRNG D15 8/ 8/2016 (va10b) PANEL Fixed D2 to be input for PANEL builds - Tidied "Peter TB mode" to be D2R_I2C_EN (and IDC mode) 26/07/2016 (va10a) IDC130_TDC Reworked constraints - to match NexysV work - lots of TIGs to decouple uunrelated clocks 20/ 7/2016 (va105) PANEL Soft resets working (except rst_coreclks) fixed 0 payload opcode handling with multi-oc packets (I think) 6/ 7/2016 (va102) IDC130_TTC 6/ 7/2016 (va101) ABCN_TTC 27/ 5/2016 (va100) PANEL_TLU_CS more debugging a non-problem 26/ 5/2016 (va0fd) ABCN_TLU trying things with event fifo to fix stuck packets 25/ 5/2016 (va0fc) PANEL_TLU_CS 24/ 5/2016 (va0fb) ABCN_TLU 24/ 5/2016 (va0fa) IDC_TLU Improved TLU-TDC handling 23/ 5/2016 (va0f9) IDC_TLU TLU i/f waits 4x12.5ns before deciding to keep a trigger (was 2x12.5ns) If trigger is rejected, nothing happens (except maybe a TDC word) Note SVN has this as va0f8, sorreeeeee! 23/ 5/2016 (va0f8) IDC_TLU 20/ 5/2016 (va0f7) IDC_TTC last trid = 0xffff at reset, busy assert count fix 20/ 5/2016 (va0f6) IDC_TTC added last TLU TRID readback - status 27 18/ 5/2016 (va0f5) ABCN_TTC 18/ 5/2016 (va0f4) ABCN_TLU 17/ 5/2016 (va0f3) IDC_PANEL 17/ 5/2016 (va0f2) IDC_TLU Slight change to data handling 14/ 5/2016 (va0f0) IDC_TLU_P improved timing for trigger data storage - fixed TDC output inhibit - only 1 TDC work per trig now - Added IDE I2C on RESET pair option (TB_PETER_MODE) This is enabled (hence "_P"). sck=_P, sda=_N. CH10 11/ 5/2016 (va0e7) ABCN_TTC 11/ 5/2016 (va0e6) ABCN_TLU 11/ 5/2016 (va0e5) IDC_TTC 11/ 5/2016 (va0e4) IDC_TLU Delayed duplicate triggers option added Added burst trigs to trigger data (good thing?) Tried to reduce timing errors. Failed. Improved stream fifoing (72-in, 18-out) 3/ 5/2016 (va0d2) IDC_TTC Simulated working TLU as TTC PMOD option (reg 33.0) 3/ 5/2016 (va0d1) IDC_TLU Option to turn anti-glitch off (reg 31.3) 1/ 5/2016 (va0d0) IDC_TLU TLU inferface demands trigger-in is high for >25ns before progressing with handshake. TRID resets to 0xffff 30/ 4/2016 (va0cf) IDC_TLU PMOD_TTC inputs can be switched to TLU handler a la Dennis' PMOD_TLUD Added counters for ECRs and BCRs, with "command" resets 30/ 4/2016 (va0ce) IDC_TLU More options for event data packets: choose TLU word instead of timestamp word at start choose timestamp word after every event word changed event data timestamps to hires mode 26/ 4/2016 (va0cd) IDC_TTC Added Drv I2C lines (only in IDC/non-TLU builds) 26/ 4/2016 (va0cc) DRV_TTC rebuild - refresh - no changes 17/ 3/2016 (va0ca) IDC130_TLU 17/ 3/2016 (va0c9) ABCN_TLU 17/ 3/2016 (va0c8) IDC130_TLU 17/ 3/2016 (va0c7) ABCN_TLU Added tlu_trid=0 debug pin 3/ 3/2016 (va0c6) DRV_TLU 3/ 3/2016 (va0c5) IDC130_TTC added datagen - controlled by reg 36-39 see twiki 26/ 2/2016 (va0c1) IDC130_TLU fixed sysstatrd returned opcode, cap640 work (works in sim) 24/ 2/2016 (va0bf) IDC130_TTC with untested cap640 too 17/ 2/2016 (va0be) ABCN_TTC 12/ 2/2016 (va0bd) Makefile build / 2/2016 (va0bb) 4/12/2015 (va0ba) DRV phase control on DXouts - see reg 34 - OPHASE_DX 30/10/2015 (va0b9) IDC130_TLU TLU disables TDC when disabled 29/10/2015 (va0b8) IDC130_TLU L0ID in data stream timestamps 23/10/2015 (va0b7) ABCN_TTC 23/10/2015 (va0b6) ABCN_TLU stream status readback fix 22/10/2015 (va0b5) ABCN_TLU 22/10/2015 (va0b4) ABCN_TTC added other ext-triggers to the LED (pre=enables) 22/10/2015 (va0b3) ABCN_TTC 22/10/2015*(va0b1) ABCN_TLU * 22/10/2015*(va0b0) ABCN_TTC * 21/10/2015 (va0ae) IDC130_TLU Timeouts now programmable by reg 32: RO_FIFO_TO. defaults to 50KHz (no change) 21/10/2015 (va0ad) IDC130_TLU reverted back to faster packet fill timeout 21/10/2015 (va0ac) IDC130_TLU reverted oc_dtack_n resolution (no more if 'Z' ...) WORKS! 21/10/2015*(va0ab) IDC130_TLU *data packet fill timeout changed: 10x longer 21/10/2015*(va0aa) IDC130_TLU *has outgoing phase offset compile option (no change, though) 19/10/2015*(va0a7) ABCN_TLU * 19/10/2015*(va0a6) ABCN_TTC * 15/10/2015*(va0a4) IDC130_TTC * 15/10/2015*(va0a3) ABCN_TTC * 15/10/2015 (va0a2) Further fixes for stream config readout, TLU TDC inhibit for trigger number "triggers" 14/10/2015 (va0a1) Fixes for stream config readout (not) 14/10/2015 (va09e) Added more debug tlu lines 14/10/2015 (va09d) IDC_TLU fixed dropped packet count 10/10/2015 (va09c) IDC_TLU added extra trigger data (TDC etc) - rejigged format a little: see twiki 13/10/2015 (va09b) CHS1 Jaya John (Oxford) build - well tested and working 10/10/2015 (va09a) CHS1 fixed fifo_ack_gen 8/10/2015 (va099) CHS1 added special functions (e.g. sync reset) 7/10/2015 (va098) CHS1 Includes Rui's start on SPI on TWOWIRE channels 1,2 6/10/2015 (va097) CHS1 first attempt 6/10/2015 (va096) IDC130 fixed d008 format =2 ( was 1??? :-) ) Updated trigger code to log l0id asap, and added ts to tlu data 25/09/2015 (va095) IDC130 fixed d008 format =1 (was 2???) 25/09/2015 (va094) IDC130 fixed dead clock from nor 320_lock bug 24/09/2015*(va093) IDC130 640mb data deser, fixed 2x160 demux 22/09/2015 (va092) IDC130 reg/stat bugfixes 22/09/2015 (va091) IDC130 new 640Mb serialised COM. increased reg, statblock 21/09/2015 (va090) IDC130 with 10x faster timeout for packet filling 21/09/2015 (va08f) IDC130 (same as 8d below, but not accidently overwritten!) 18/09/2015 (va08e) PANEL ( part of test below - for comparison) 18/09/2015 (va08d) IDC130 (test to check logic utilisation) 7/09/2015 (va08c) ABCN 7/09/2015 (va08b) DRV Fixed OC_ECHO not working ... 7/08/2015 (va08a) DRV Fixed DRV line assign bug (tmu_com_invert) 6/08/2015 (va089) DRV 31/07/2015 (va088) IDC with buttons working properly 17/07/2015*(va083) ABCN 17/07/2015 (va082) IDC with btnC = send Status, btnU = send regblock 7/07/2015 (va080) IDC updatd arch version: cx, packet xoff, etc 26/06/2015 (va07c) ABCN build 11/06/2015 (va07b) IDC build 11/06/2015 (va07a) DRV fixed double counting in PMOD_TTC TRIG_2 11/06/2015 (va079) DRV updated pkt detect looking for 65b with 01xxxxxxxx... 11/06/2015 (va078) DRV rebuild with some some muxing changes reverted 11/06/2015 (va077) DRV unswapped PMOD_TLU trig and busy outputs 11/06/2015 (va076) DRV fixed 25ns busy generated when busylen set to 0 (no CX) 9/06/2015 (va072) Back to clock crossing firmware - better for debugging (oops same ver) 9/06/2015 (va072) Trial with clock crossing (CX) firmware - better for debugging 8/06/2015 (va071) DRV build 3/06/2015 (va06e) IDC-PTTC Robusterised the stream fifos against overflow tried to make a smarter passive mux enabled all 1s packet un-detect 2/06/2015 (va06c) IDC-PTTC removed clock crossing logic 2/06/2015 (va06b) IDC PMOD-TTC fixed tdc readout 2/06/2015 (va06a) IDC PMOD-TTC with input trig counters 1/06/2015 (va066) IDC PMOD-TTC integration - I2C in, rest is still in-progress (there, but ..) 28/05/2015 (va064) IDC New structure - clock segregation - should function the same 20/05/2015 (va05d) DRV 40MHz readout mode added 19/05/2015 (va05c) ABCN lots of debug outputs added - see twiki 6/05/2015 (va059) IDC TLU sigs on VMODIB D12,D13 6/05/2015 (va058) IDC rebuild with latest TLU and trigger mods 13/04/2015 (va057) DRV fixed header detect bug - MAY work 9/04/2015 (va056) ABCN shows nice signs of life ... 8/04/2015 (va055) DRV 8/04/2015 (va054) ABCN (not working!) 3/04/2015 (va053) IDC. Modified ISERDES2 generics (MODE=RETIMED, WIDTH=4) Seems to work on new Atlys'!! 25/03/2015 (va050) IDC. Debug outputs: D4-5=delayed D0-1; D8-11=demuxed D0.0,D0.1,D1.0,D1.1 25/03/2015 (va04c) IDC Added Driver controls, but they don't quite work 23/03/2015 (va049) IDC Fixed no OUTSIGs bug. 20/03/2015 (va047) Driver build of recent FW. Includes TLU, busy etc. as mentioned below 13/03/2015 (vb03d) Variable busy length - see reg 10. TLU trigger number recieve control, see reg 31 *** NOTE: TLU controls from reg 19 MOVED to reg 31 *** 5/03/2015 (va037) busy changed back, added lu_trig and tlu_clk to MBCSV1 lemos 5/03/2015 (va036) Busy changed to make sync 5/03/2015 (va035) TLU sigs inverted (good with PMOD-bodge) 5/03/2015 (va034) TLU sigs un-inverted 5/03/2015 (va033) TLU sigs inverted with LEDs 4/03/2015 (va032) CMOS TLU 14/11/2014 (va02a) MBH35 with serout 28/10/2014 (va029) DRV 28/10/2014 (va028) MBH35 Err ... now it really works 28/10/2014 (va027) MBH35 fixed trailing zero bug (again!) 28/10/2014 (va026) MBH35 modified packet handling (fifo half-empty check) 20/10/2014 (va025) DRV proper decoder this time! even works! 17/10/2014 (va024) DRV rebuild 14/10/2014 (va023) MBH35 deser in place, sim says it works 14/10/2014 (va022) MBH35 fixed rawsigs sync too 13/10/2014 (va021) MBH35 first attempt at deser 13/10/2014 (va020) MBH35 20MHz RAWSEQ sync. CKFAST invert option 9/10/2014 (va01f) MBH35 20MHz BCO option (reg16,10) 9/10/2014 (va01e) CMOS version - aka MBH35 - no packet decoding yet 7/10/2014 (va018) DRV version - 2/10/2014 (va017) CMOS version - MAC address now e0:dd:cc:bb:0n, n ser by sw(3:0) 1/10/2014 (va016) At last a log is born 21/07/2014 (va000) birthday!