GLIB Build log
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2017-12-01 91bc GBTSTIB_TGRW_CS Changed bitgen StartUpClk to JtagClk for djtgcfg use
2017-11-27 91b8 GBTSTIB_TGRW_CS More chipscope signals and more depth
2017-11-06 91b0 GBTSTIB_TGRW Back to Widebus RX, 16 links enabled. (No CS)
2017-11-02 91af GBTSTIB_TGRG_CS Added chipscope on SC signals
2017-11-02 91ae GBTSTIB_TGRG Set to FEC mode on both RX and TX
2017-11-01 91ad GBTBERT_TGRW  
2017-11-01 91ac GBTSTIB_TGRW Fixed reg/stat read missing last word bug 
2017-10-24 91a9 GBTSTIB Moved build dir and project to trunk/ise/glib_itsdaq
                        Lots of path, softlink etc changes for rational building
								Also enabled histo
2017-10-23 91a8 GBTSTIB Refresh build to check all still works (in my head too!) 
2017-04-10 9166 GBTSTIB Fixed reversed SC registers bug
2017-04-10 9165 GBTSTIB Rebuild for sanity
2017-03-22 9160 GBTSTIB Reconnected SC registers
2017-03-21 915f GBTSTIB Rebuild with 16 GBT1 links only
2017-03-20 915e GBTSTIB First go at Peter Staves Interposer (8 + 8 links)
2017-03-14 9156 GBTBERT TGRW - debug - bert 360 sends count + added ophase :-)
                                    ++ added longer bert start delay and 1024 match to lock
2017-03-13 9155 GBTBERT TGRW - debug - bert 360 sends count
2017-03-13 9154 GBTBERT TGRW - More Fixes for 320Mb capture, 
                                    BERT more careful not to lock onto zeros now
2017-03-10 9153 GBTBERT TGRW - Fixes for 320Mb deser (cap only)
2017-03-10 9152 GBTBERT TGRW - Fixes for 320Mb mode
2017-03-10 9151 GBTBERT TGRW - reworked with independent 160 and 320 modes
2017-03-09 9150 GBTBERT TGRW - Extended BERT pattern - 16B long series of K0,K1 - makes for easier 
                        capture decoding
2017-03-09 914f GBTBERT TGRW - TX=GBT_FRAME, RX=WIDEBUS
2017-03-08 914e GBTBERT TGRG - TX and RX = GBT_FRAME (aka not WIDE)
2017-03-08 914d GBTBERT Bug fix - GBTCORE_CTL0 was also GBTCORE_CTL1
2017-03-07 914c GBTBERT with 20+20 e-links captured
2017-03-07 914b GBTBERT playing with GBT core config options, more BERT registers
								BERT and GBT reg bits MOVED - check wiki.
2017-03-06 9149 GBTBERT Fixed delay tracking changing data in BERT pipeline
2017-03-06 9148 GBTBERT GBT TX AND RX to both be WIDEBUS MODE - DOH!
2017-03-06 9147 GBTBERT Set all TX data to 0xac - more edges
2017-03-06 9146 GBTBERT Set all TX data to 0x4f - lets see what capt. sees ...
2017-03-04 9145 GBTBERT fix 5
2017-03-04 9144 GBTBERT fixed data pattern
2017-03-04 9143 GBTBERT Nuther BERT fix
2017-03-03 9141 GBTBERT Capt fix and new BERT algo
2017-03-03 9141 GBTBERT Added reg controlled GBT1-TX inversion
2017-03-03 9140 GBTBERT All 4 bert lock/delay status at once 
2017-03-03 913f GBTBERT Fixed no-timeout bug (but still no capture)
                        Offset each TX stream, so distuishable
2017-03-03 913e GBTBERT Switchable BERT. see GBT_CONTROL reg 
2017-03-02 913d GBTBERT Switched bert to GBT2, turned TX wide-bus mode off
2017-03-02 913b GBTBERT GBT1 (of GBT1 and GBT2) polarity flipped
2017-03-02 913a GBTBERT tester bug fixes ...
2017-03-02 9138 GBTBERT tester - e-links 28, 30
2017-02-22 9137 G_LCBDG LCB data generator
2017-02-22 9136 GBTTEST Trying no-mux option for data (getting ready for LCB datagen)
2017-02-22 9133 GBTTEST Made TX dependent on rxReady - cleans up bad e-links
2017-02-22 9132 GBTTEST Removed more SC stuff, elinks f000f on both GBTs
2017-02-21 9131 GBTTEST Enable both SC status words again (only got 1 GBT :-( )
2017-02-21 9130 GBTTEST Disable both SC status words - 2 links working!
2017-02-21 912f GBTTEST disabled SC1 status - still only link-1 working
2017-02-21 912e G_ST130 GBT Stave build - L0COM/L1R3 over 160Mb e-links etc - seems good
2017-02-21 912d GBTTEST Rebuild after tidy + re-enable SC1 control - 1 link working!! :-( 
2017-02-20 912c GBTTEST 2 GBT links working

2017-02-16 9126 GBTTEST Trying all 20 elinks
2017-02-16 9123 GBTTEST Trying again ... (worked!)
2017-02-16 9122 GBTTEST ASIC packet datagen 2x80Mb (dead!)
2017-02-16 911f GBTTEST Datagen with counters 2x80Mbb