NexysV Changelog =========================================================================== * = Broken! (otherwise it only might be broken ;-) ) 13/12/2017 vb1cc FDM_DECAL ISE build - added frmclockperiph + enables in reg 8/12/2017 vb1c8 FDM_DECAL Added debug outputs on PMOD JC, Viv build 4/12/2017 vb1bf FIB_STD_H Trying less complicated constraints 1/12/2017 vb1bd FIB_STD_H Build after moving all fmc files to own lib 29/11/2017 vb1bb FIB_STD_H VIVADO BUILD! And it seems to work (only the net connect checked tho) 28/11/2017 vb1ba FDM_DECAL Clock really changed to 20MHz SQUARE WAVE!!, frmclk = 40MHz now 27/11/2017 vb1b7 FDM_DECAL Clock changed to 20MHz, added frameclock at same freq too 10/11/2017 vb1b4 FDM_DECAL Auto phase operational 10/11/2017 vb1b3 FDM_DECAL Capture mode operational 8/11/2017 vb1b2 FDM_DECAL First DECAL build 23/10/2017 vb1a7 FIB_LOOP_640_SPECIAL Rebuild with ONLY 1 link in the build 20/10/2017 vb1a6 FIB_LOOP_640_SPECIAL Only has a 640 counter on ser 0 5/10/2017 vb1a0 F2V_STD2_H (+TLU) Build for James to see ... 30/08/2017 vb19d FIB_SOIE_H SOIE version with the extra TTC 29/08/2017 vb19c FIB_STD_H More TTC ports, via OUTSIGS: J5: STT, J6:STB, J0:ID0 (note OPHASE is still common to all) 18/08/2017 vb19b FIB_STD_H Refresh with histo 27/07/2017 vb199 FIB_STD Refresh for FIB_STD. Good build! 27/07/2017 vb198 FIB_IDCONLY Added reset stream seqid command 26/07/2017 vb197 FIB_IDCONLY IDC L0COM/L1R3 o/ps un-inverted, IDC o/ps now port 7 - matches SOIE 26/07/2017 vb196 FIB_STD J6 on streams 64-79 (and unchanged J5 0-15, IDC 128-131) 26/07/2017 vb195 FIB_IDCONLY IDC datas un-inverted (bug fix), and 160 removed 21/07/2017 vb194 FIB_IDCONLY_H 160MHz clock on "fmc_clk1_m2c" LVDS line (but as output) - for use with FMC105 19/07/2017 vb192 FIB_SOIE_H Another TWOWIRE fix 19/07/2017 vb190 FIB_SOIE_H SOIE build with all the greatest and latest 18/07/2017 vb18f FIB_IDCONLY_H Fixed bug introduced by 18d 17/07/2017*vb18d FIB_SOIE_H Added more clocking the ack_gen (aka reply packet gen) 16/07/2017 vb18c FIB_SOIE_H Alternative iserdes clk_div trial 15/07/2017 vb18b FIB_SOIE_H Improved twowire (for I2C at least, other modes may be worse :-( ) 13/07/2017 vb189 FIB_IDCONLY Fixed histo packet len bug 12/07/2017 vb188 FIB_IDCONLY Raw packet filter option added (see histo reg) 12/07/2017 vb187 FIB_STD_H Added "all packets" count to v1 histo data 11/07/2017 vb186 FIB_IDCONLY_H Histogrammer upgrade - data format v1 counters added: num hits, num pkts, pkts dropped etc readout on bin full mode 10/07/2017 vb185 FIB_STD - Build for this hardware - good luck BNL :-) (and Seqnum fix re-applied) 21/06/2017 vb184 FIB_SOIE - Unfixed SeqNum = 0 bug - Causing too much s/w havoc Also turned off histo to make it build faster 20/06/2017 vb183 FIB_SOIE_H - Moved to OPHASEB for individual phases output busses See reg 40-43 Also fixed data packet SeqNum = 0 20/06/2017 vb182 FIB_IDCONLY - Quick test - fixed deadness (missed reset) 20/06/2017 vb181 FIB_SOIE_H - Dead 20/06/2017 vb180 F2V_STD8 - Removed strm_reset from FIFO/sender block 19/06/2017 vb17f F2V_STD8 - Changed strm_reset command to be much softer: Will only work if streams are already disabled (or Idle) 9/06/2017 vb17e F2V_STD8 - 16/05/2017 vb17c FIB_SOIE_H - Histo autoreadout mode when data stops flowing > 30us 16/05/2017 vb17b FIB_SOIE_H - com/l1r com output delay control bug fix 13/05/2017*vb177 FIB_SOIE_H - rebuild 13/05/2017*vb176 FIB_IDCONLY_H changed IDC stream numbers to their proper home: 128-131 13/05/2017*vb175 FIB_IDCONLY_H Fixed histo rollover bug, added ramplet mode to datagen 12/05/2017*vb174 FIB_SOIE_H - Fixed datagen 1BC and histo 1BC and 3BC bugs 12/05/2017*vb173 FIB_SOIE_H - Removed latches and some unneeded features from clocks gen (Series 7 MMCMs have nice reset inputs) 11/05/2017*vb172 FIB_SOIE_H - changed to synchro data mux in rouadout block (worse for FF usage, but we only use 10%!!) 09/05/2017 vb170 F2V_STD8 - Making sure this works for Dennis 09/05/2017 vb16f F2V_STD2 - Making sure this works for Dennis 08/05/2017 vb16e FIB_SOIE_H - Fixed datagen to include chipis in counters 08/05/2017 vb16d FIB_SOIE_H - Added 3BC to histo, fixed datagen to have internal counter - better at high rates 04/05/2017 vb16b FIB_SOIE_H - Fixed raw needed by histo bug and histoto readout on reset bug 04/05/2017 vb16b FIB_SOIE_H - Histo test - only streams on J6 25/04/2017 vb169 FIB_SOIE_H - Unswapped SAMTEC I2Cs (for test), Unswap I2C on IDC (because it was wrong) 21/04/2017 vb168 FIB_SOIE_H - Added I2C on FMC-IB J0 (IDC) 20/04/2017 vb167 FIB_SOIE_H - First SOIE build - I2C on 10,11 (Sam J5, J6) - Links: Sam J5 19-26, J6 51-58, IDC J0 64-64 10/04/2017 vb164 FIB_IDCONLY_H- Fixed little datagen bug 10/04/2017 vb163 FIB_IDCONLY_H- INCLUDES basic ABC130 Histogrammer!! 16/03/2017 vb15c FIB_STAVE - Switched SE lines to p side of Samtec (FMC-IB backwards) 16/03/2017 vb15b FIB_STAVE - Tidies some inferred latches in the code - builds faster! (I hope it still works ;-) !) 16/03/2017 vb15a FIB_STAVE - RAL stave with Data 14-26 on J6, with PMODs, I2C on chan 0 22/02/2017 vb135 FIB_STD - With PMODs enabled 16/02/2017 vb125 FIB_IDCONLY - Added PRNG to fmc_clk1_m2c line (but as output), for use with FMC105 (xil) - use sw(7:6) to control freq. 16/02/2017 vb124 FIB_LOOP - Checking to see if this works at 160Mb) 16/02/2017 vb121 FTCDS_TEST - Changed to 160Mb link (from 320) 15/02/2017 vb120 FTCDS_TEST - Quick and dirty test rig for TCDS-FMCs 10/02/2017 vb118 FIB_STD - Undid reversed reg init values bug ... 09/02/2016 vb116 FIB_STD - Programmable inverts for stream in (via strm reg) and control outputs (reg INVERTS) ------ Note new version number -- the lower 3 nibbles are now common across all boards ---- 26/01/2016 vb054 FIB_STD - Inverted all FMC signals - seems the FMC-IB pinout is swapped :-( 26/01/2016 vb053 FIB_STD - Added INVERTS register (#48) 3/12/2016 vb052 FIB_IDCONLY - Below didn't work reverting to orignal TWOWIRE for now 3/12/2016 vb051 FIB_IDCONLY - Changed TWOWIRE operation (removed SCL /pulse at before start) ###################################### 2 0 1 7 ########################################### 15/12/2016 (vb050) FIB_IDCONLY - first attempt at IDC only f/w - links 16,17 (streams 32-36) now with Nexys I2C (that includes FMC I2C) on TWOWIRE channel 15 15/12/2016 (vb04f) FIB_LOOP - now with triggerrerered datagen 13/12/2016 (vb04c) FIB_LOOP - J5 out, J6 in, 2x160Mb streams on each output 13/12/2016 (vb04b) FIB_STD - All connectors included - NOT TESTED 08/07/2016 (vb046) F2V_ABCN 27/07/2016 (vb045) F2V2_TTT - Added clk160 for ABCx_EMU use 27/07/2016 (vb044) F2V2_TTT - Changed to MMCM multiplier of 24 - because coregen said so! 26/07/2016 (vb043) F2V2_TTT - rebuild with bank-voltage back to 2V5 - works! (i forget when I set it to 3v3 :-( ) - need to investigate this further - may be a sillyness 26/07/2016 (vb042)* F2V2 - Added DDR to OSERDES 26/07/2016 (vb041)* F2V2 - rejigged constraints - isolated clk125, clk40, clk40_ext. - moved from 640 ISERDES to 320 DDR - 640 is >> Artix-2 spec (which is 400ish !!) - tidied, fixed rgmii constraints - rationalised net_top resets - We now have NO TIMING VIOLATIONS - yeee haaa! - But does it work ... And need to DDR OSERDES now ... 20/07/2016 (vb03d) F2V2 - removed core_rst - not needed. 20/07/2016 (vb03c) F2V2 - Coreclks reset fixed - does NOT reset anything else 20/07/2016 (vb03b) F2V2 - Soft resets working (except rst_coreclks) - fixed 0 payload opcode handling with multi-oc packets (I think) 21/06/2016 (vb031) F2V_ABCN again 14/06/2016 (vb02f) F2V_ABCN (!) The first build with an ABCN option! 13/06/2016 (vb02e) F2V_DRV 3 /03/2016 (vb02c) F2V8 - Added datagen - see reg 36, twiki 640Mb capture included (not tested) sysreg/stat working 5/02/2016 (vb02a) makefile build 5/02/2016 (vb029) F2V8 - Added System Reg & Stat Wr, Rd (see twiki) Added PMOD_TLU on JB, PMOD_TTC on JC - untested 28/01/2016 (vb023) F2V_DRV - First attempt at a simple Driver i/f 27/01/2016 (vb022) F2V8 (Net IDELAY=0) - fixed Samtec remap bug 16/01/2016 (vb021) F2V8 (Net IDELAY=0) 15/01/2016 (vb020) F2V8 (Net IDELAY=7) 15/01/2016 (vb01f) Netloop + CS: IDELAY=19 15/01/2016 (vb01d) Netloop + CS: IDELAY=7 15/01/2016 (vb01d) Netloop + CS: IDELAY=0 15/01/2016 (vb01c) Netloop + CS: IDELAY=11 13/01/2016 (vb015) Netloop + CS, JA-0: rxc, 1: clk125, 2: clk125_90 13/01/2016 (vb014) Netloop + CS, no timing shift, clk125s on JA 13/01/2016 (vb013) Netloop + CS, shifted rx timings 24 steps 13/01/2016 (vb012) Netloop + CS, shifted rx timings 8 steps 13/01/2016 (vb011) Netloop + CS, shifted rx timings 16 steps 13/01/2016 (vb010) Netloop + CS 12/01/2016 (vb00f) F2V2 - 12/01/2016 (vb00e) Net loopback only ... 12/01/2016 (vb00d) F2V2 - with chipscope 22/12/2015 (vb00c) F2V2 changed default OPHASE 22/12/2015 (vb00b) F2V16 - more of the same (but a silly ver!) 21/12/2015 (vb00a) F2V2 - rebuild on laptop after much SVN shenanigans 21/12/2015 (vb009) F2V2 - some ABCN (mostly) triggering mods 18/12/2015 (vb008) F2V16 - version with 16 links (no PMODs) 11/12/2015 (vb001) 1st version with Ethernet, no DIOs yet 10/12/2015 (vb000) Happy birthday to me