ABC130 Driver Changelog

11/09/2016 (vd05e) - ABC - SPECIALv3 - same a v1 but with L1R3 signal inverted
11/09/2016 (vd05d) - ABC - SPECIALv2 Peter pinout rotated the other way
10/09/2016 (vd05c) - ABC - SPECIALv1 Peter pinout again, just in case
10/09/2016 (vd05b) - ABC - SPECIALv1 Peter pinout! 
13/06/2016 (vd05a) - ABC only version, dut type reported in 31:16 of version
 2/04/2016 (vd058) - Added clk320 to the DXout options
29/04/2016 (vd057) - Added clk40,80,160 to DXouts - set reg77 to all 4s,5s or 6s.
29/04/2016 (vd055) - Removed the changes added in vd053 (but leaving those from 54)
28/04/2016 (vd054) - Register defaults changed to match those needed for HCC
26/04/2016 (vd053) - Asserting external reset (ITSDAQ reg 18, b8) tristates D1
                     allowing I2C use in conjunction with IDC16 on VMOD-IB
26/04/2016 (vd052) - Rebuilt again
 7/08/2015 (vd051) - Rebuilt
 9/07/2015 (vd050) - Added 320MHz clock and output clock on FCLK option 
15/02/2015 (vd04f) - Packet generator functional - see Drv registers 0x7a, 0x7b 
22/01/2015 (vd048) - added readback TLU_COM option on HSIO lines
09/01/2015 (vd047) - Made REG_EN_D, REG_EN_A, AND ABCUP dir depend on hccmode
09/01/2015 (vd046) - Added COM invert input from HSIO REG, bit 6
08/01/2015 (vd045) - Added HCCMode with DRC used as input
08/01/2015 (vd044) - Removed wait for clock before configure option
12/12/2014 (vd043) - added I2C disable bit (CONFIG)(21)
17/11/2014 (vd043) - added DUT_MODE and this is mode 1, where DRC is an input
*** The above details two modes for the same version - CHECK THIS ***

20/09/2014 (vd042) - rebuild to be sure
 9/09/2014 (vd041) - Added TMU test send packet when coml0_swap is changed
 3/09/2014 (vd040) - copied TMU readback to D15 - NOT proper LVDS, but might work
                   - I2C now SOURCED from Driver FPGA - driven uni-dir using spare signals
                     ========= moved signals around, must use new HSIO FW >= v4400 ========= 
 1/09/2014 (vd035) - Added optional invert of sigs to HSIO - reg 0x79(3:0)
23/03/2014 (vd033) - Fixed SCMODE=SHUNTCTL and mode c,d swapped bugs
21/03/2014 (vd031) - Reworked completely for FIB hybrid readout. must use HSIO fw >v4030
24/02/2014 (vd02c) - Swapped BCO and R3 lines - must use HSIO fw >0x432e
06/01/2014 (vd02b) - Changed chip address to be 0-3
06/01/2014 (vd02a) - Added high-z all ABC facing buffers option. DRV_CONF reg, bit 6
13/12/2013 (vd029) - possible fix to possible tmu lockup
13/12/2013 (vd027) - Added TMU  ABCID=30, HCCID=1, returns on HSIO strm 40
10/12/2013 (vd026) - Reworked a few things, added loopback mode, see DRV_CONF decription

 6/12/2013 (vd025) - 40Mb toggle on scan inputs!
 6/12/2013 (vd024) - not(respective clock) on scan_bus inputs 
 6/12/2013 (vd023) - xoff set bit reg 18.6
 6/12/2013 (vd022) - ~4ns phase shift between BCO and DRC
 5/12/2013 (vd021) - added DRC mode for all clocks, moved some bits (see 7,8,14)!
 5/12/2013 (vd020) - clk40/80 option on drc
 
 4/12/2013 (vd01f) - HI-Z on all xoff and dat outs
 4/12/2013 (vd01e) - clk/2, clk/3 on dat_o's
 4/12/2013 (vd01d) - clk/16 on xoff_o's
 4/12/2013 (vd01c) - wired up FC clock too (same as DRC)
 4/12/2013 (vd01b) - Removed LVDS on Xoff_o - back to normal
 4/12/2013 (vd01a) - DRC inv option added
 4/12/2013 (vd019) - LDVS buffers on Xoff_o
 4/12/2013 (vd018) - back to normal
 4/12/2013 (vd017) - clk on xoff_o and dat_o
 3/12/2013 (vd016) - DUFF? 
 3/12/2013 (vd015) - added drc160 selectable option
 3/12/2013 (vd014) - back to normal with bco and drc enable
 3/12/2013 (vd013) - clk40 on bco, drc, coml0, l1r3
 3/12/2013 (vd012) - drc=160 with enable
 
 3/12/2013 (vd008) Regen DCM - changed to include reset logic and make DONE wait LOCK
                    also needed bitgen option "LCK_cycle" set - I randomed 4
 3/12/2013  Born! (a little late - needed to be induced)