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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[116]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[114]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[112]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[111]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[110]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[108]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[107]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[106]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[105]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[103]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[102]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[101]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[100]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[99]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[98]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[97]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[96]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[95]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[94]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[93]"
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                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[92]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[91]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[90]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[89]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[88]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[87]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[86]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[85]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[84]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[83]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[82]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[81]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[80]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[79]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[78]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[77]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[76]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[75]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[74]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[73]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[72]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[71]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[70]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[69]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[68]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[67]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[66]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[65]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[64]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[63]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[62]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[61]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[60]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[59]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[58]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[57]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[56]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[55]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[54]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[53]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[52]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[51]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[50]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[49]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[48]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[47]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[46]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[45]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[44]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[43]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[42]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[41]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[40]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[39]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[38]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[37]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[36]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[35]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[34]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[33]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[32]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[31]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[30]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[29]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[28]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[27]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[26]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[25]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[24]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[23]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[22]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[21]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[20]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[19]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[18]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[17]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[16]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[15]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[14]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[13]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[12]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[11]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[10]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[9]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[8]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[7]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[6]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[5]"
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                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[4]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[3]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[2]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[1]"
                                            },
                                            {
                                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_i[0]"
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                                        ]
                                    }
                                ]
                            },
                            {
                                "name": "probe1",
                                "id": 1,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 1,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/cnter_uns[0]_i_1_n_0",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe2",
                                "id": 2,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 2,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/cnter_uns[1]_i_1_n_0",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe3",
                                "id": 3,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 3,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/cnter_uns[2]_i_1_n_0",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe4",
                                "id": 4,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 4,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/dnlink_reset_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe5",
                                "id": 5,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 5,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/fec5_error_seen_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe6",
                                "id": 6,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 6,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/fec5_error_seen_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe7",
                                "id": 7,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 7,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/gtx_qplllock_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe8",
                                "id": 8,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 8,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/gtx_qpllrefclklost_o",
                                        "isBus": false
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                                ]
                            },
                            {
                                "name": "probe9",
                                "id": 9,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 9,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf1_dnlink_ready_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe10",
                                "id": 10,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 10,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf1_dnlink_reset_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe11",
                                "id": 11,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 11,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf1_mgt_rxpolarity_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe12",
                                "id": 12,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 12,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf1_mgt_txpolarity_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe13",
                                "id": 13,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 13,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf1_uplink_ready_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe14",
                                "id": 14,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 14,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf1_uplink_reset_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe15",
                                "id": 15,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 15,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf_dnlink_ready_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe16",
                                "id": 16,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 16,
                                "nets": [
                                    {
                                        "name": "reg[56]",
                                        "isBus": true,
                                        "subnets": [
                                            {
                                                "name": "reg[56][12]"
                                            }
                                        ]
                                    }
                                ]
                            },
                            {
                                "name": "probe17",
                                "id": 17,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 17,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf_mgt_rxpolarity_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe18",
                                "id": 18,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 18,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf_mgt_txpolarity_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe19",
                                "id": 19,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 19,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgf_uplink_ready_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe20",
                                "id": 20,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 20,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgm0_dnlink_ready_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe21",
                                "id": 21,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 21,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgm0_dnlink_reset_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe22",
                                "id": 22,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 22,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgm0_uplink_ready_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe23",
                                "id": 23,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 23,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgm0_uplink_reset_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe24",
                                "id": 24,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 24,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgm1_dnlink_ready_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe25",
                                "id": 25,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 25,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgm1_dnlink_reset_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe26",
                                "id": 26,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 26,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgm1_uplink_ready_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe27",
                                "id": 27,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 27,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/lgm1_uplink_reset_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe28",
                                "id": 28,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 28,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/mgtq_rx_reset_i",
                                        "isBus": false,
                                        "parentNetId": 280
                                    }
                                ]
                            },
                            {
                                "name": "probe29",
                                "id": 29,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 29,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/mgtq_tx_reset_i",
                                        "isBus": false,
                                        "parentNetId": 281
                                    }
                                ]
                            },
                            {
                                "name": "probe30",
                                "id": 30,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 30,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/rst_uplinkInitDone_s",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe31",
                                "id": 31,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 31,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/tog40",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe32",
                                "id": 32,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 32,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/txclk_lock_out",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe33",
                                "id": 33,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 33,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/uplink_reset_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe34",
                                "id": 34,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 34,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkClkInEn_i",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe35",
                                "id": 35,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 35,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkClkOutEn_s_reg_n_0",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe36",
                                "id": 36,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 36,
                                "nets": [
                                    {
                                        "name": "u_ila_0_uplinkReady_1_s",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe37",
                                "id": 37,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 37,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkReady_o",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe38",
                                "id": 38,
                                "type": "DATA_TRIGGER",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 38,
                                "nets": [
                                    {
                                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkRst_i",
                                        "isBus": false,
                                        "parentNetId": 290
                                    }
                                ]
                            }
                        ]
                    }
                ],
                "parent_nets": [
                    {
                        "id": 280,
                        "name": "Umain/Uctltop/Uocbregblock/reg_o[56][14]",
                        "state_reg": [
                            {
                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits0/path_mgt_inst/mgt_core_inst/U0/gt0_rxresetfsm_i/FSM_sequential_rx_state_reg[0]",
                                "states": [
                                    {
                                        "name": "release_pll_reset",
                                        "val": "0011"
                                    },
                                    {
                                        "name": "verify_recclk_stable",
                                        "val": "0100"
                                    },
                                    {
                                        "name": "wait_for_pll_lock",
                                        "val": "0010"
                                    },
                                    {
                                        "name": "fsm_done",
                                        "val": "1010"
                                    },
                                    {
                                        "name": "assert_all_resets",
                                        "val": "0001"
                                    },
                                    {
                                        "name": "init",
                                        "val": "0000"
                                    },
                                    {
                                        "name": "wait_reset_done",
                                        "val": "0111"
                                    },
                                    {
                                        "name": "monitor_data_valid",
                                        "val": "1001"
                                    },
                                    {
                                        "name": "wait_for_rxusrclk",
                                        "val": "0110"
                                    },
                                    {
                                        "name": "do_phase_alignment",
                                        "val": "1000"
                                    },
                                    {
                                        "name": "release_mmcm_reset",
                                        "val": "0101"
                                    }
                                ]
                            }
                        ]
                    },
                    {
                        "id": 281,
                        "name": "Umain/Uctltop/Uocbregblock/reg_o[56][15]",
                        "state_reg": [
                            {
                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits0/path_mgt_inst/mgt_core_inst/U0/gt0_txresetfsm_i/FSM_sequential_tx_state_reg[0]",
                                "states": [
                                    {
                                        "name": "wait_for_txoutclk",
                                        "val": "0100"
                                    },
                                    {
                                        "name": "release_pll_reset",
                                        "val": "0011"
                                    },
                                    {
                                        "name": "wait_for_pll_lock",
                                        "val": "0010"
                                    },
                                    {
                                        "name": "assert_all_resets",
                                        "val": "0001"
                                    },
                                    {
                                        "name": "init",
                                        "val": "0000"
                                    },
                                    {
                                        "name": "wait_reset_done",
                                        "val": "0111"
                                    },
                                    {
                                        "name": "reset_fsm_done",
                                        "val": "1001"
                                    },
                                    {
                                        "name": "wait_for_txusrclk",
                                        "val": "0110"
                                    },
                                    {
                                        "name": "do_phase_alignment",
                                        "val": "1000"
                                    },
                                    {
                                        "name": "release_mmcm_reset",
                                        "val": "0101"
                                    }
                                ]
                            }
                        ]
                    },
                    {
                        "id": 290,
                        "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/uplink_reset_sync",
                        "state_reg": [
                            {
                                "name": "g_lpgbt.g_build_s2_pp2.Ulpgbt2fpga2model/Upathlpgbtfpgaits1/lpgbt_fpga_inst/mgt_frame_receiver_inst/mgt_frame_aligner_inst/FSM_onehot_bs_state_reg[1]",
                                "states": [
                                    {
                                        "name": "bs_SLIDE",
                                        "val": "010"
                                    },
                                    {
                                        "name": "bs_IDLE",
                                        "val": "001"
                                    },
                                    {
                                        "name": "bs_DELAY",
                                        "val": "100"
                                    }
                                ]
                            }
                        ]
                    }
                ]
            }
        ]
    }
}