diff --git a/Sources/Payload/GCI/hdl/outputs/tx_channel.vhd b/Sources/Payload/GCI/hdl/outputs/tx_channel.vhd
index e76b674c1..eb1d238ab 100644
--- a/Sources/Payload/GCI/hdl/outputs/tx_channel.vhd
+++ b/Sources/Payload/GCI/hdl/outputs/tx_channel.vhd
@@ -29,6 +29,8 @@ use ieee.numeric_std.all;
 library ipbus;
 use ipbus.ipbus.all;
 
+library payload_lib;
+use payload_lib.pkg_crc16_d32.all;
 
 entity tx_channel is
   generic (
@@ -141,6 +143,7 @@ architecture rtl of tx_channel is
   signal tx_bcn_del_2 : std_logic_vector(11 downto 0);
   signal trailer_bcn  : std_logic_vector(11 downto 0);
   signal new_bcn_del  : std_logic;
+  signal data_crc     : std_logic_vector(15 downto 0);
 
   signal armed_play_bcn    : std_logic;
   signal armed_play_once   : std_logic;
@@ -275,7 +278,7 @@ begin
 
 --             31       28   27 26   25           12   11        0
   trailer_0 <= CTP_LINK_ID & "00" & "00000000000000" & trailer_bcn;  --tx_bcn 
-  trailer_1 <= x"ffff" & x"50bc";
+  trailer_1 <= data_crc & x"50bc";
 --idle_output <= x"000050BC";
 
 
@@ -290,7 +293,7 @@ begin
       elsif (zero_sel = '1') and (pattern_en_i = '0') then
         output_reg <= x"00000000";
       elsif (word_sel(0) = '1') then
-        output_reg <= data_word(31 downto 0);
+        output_reg <= data_word(31 downto 0); --TODO idea:  when (zero_sel = '0') else x"00000000";
       elsif (word_sel(1) = '1') then
         output_reg <= data_word(63 downto 32);
       elsif (word_sel(2) = '1') then
@@ -306,6 +309,10 @@ begin
       end if;
     --MRMWend if;
   end process;
+  
+  
+  
+  
 
   process (tx_clk)
   begin
diff --git a/Sources/Payload/GCI/hdl/pkg_crc16_d32.vhd b/Sources/Payload/GCI/hdl/pkg_crc16_d32.vhd
index b6ab9fbb6..bcabd3d84 100644
--- a/Sources/Payload/GCI/hdl/pkg_crc16_d32.vhd
+++ b/Sources/Payload/GCI/hdl/pkg_crc16_d32.vhd
@@ -19,7 +19,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-package PCK_CRC16_D32 is
+package pkg_crc16_d32 is
   -- polynomial: x^16 + x^15 + x^2 + 1
   -- data width: 32
   -- convention: the first serial bit is D[31]
@@ -27,10 +27,10 @@ package PCK_CRC16_D32 is
     (Data: std_logic_vector(31 downto 0);
      crc:  std_logic_vector(15 downto 0))
     return std_logic_vector;
-end PCK_CRC16_D32;
+end pkg_crc16_d32;
 
 
-package body PCK_CRC16_D32 is
+package body pkg_crc16_d32 is
 
   -- polynomial: x^16 + x^15 + x^2 + 1
   -- data width: 32
