diff --git a/Sources/Infra/GCM/GCM415/2024.2/ip/transceiver_versal_interlaken/transceiver_versal_interlaken.xci b/Sources/Infra/GCM/GCM415/2024.2/ip/transceiver_versal_interlaken/transceiver_versal_interlaken.xci
index 716d09b03..83906c310 100644
--- a/Sources/Infra/GCM/GCM415/2024.2/ip/transceiver_versal_interlaken/transceiver_versal_interlaken.xci
+++ b/Sources/Infra/GCM/GCM415/2024.2/ip/transceiver_versal_interlaken/transceiver_versal_interlaken.xci
@@ -1125,15 +1125,15 @@
         "ENABLE_NORTHOUT_SOUTHIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "ENABLE_NORTHIN_SOUTHOUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
         "INTF0_TXRX_OPTIONAL_PORTS": [ { "value": [
-            "GT_TYPE GTYP GT_DIRECTION DUPLEX ch_txdata true ch_txbufstatus false ch_txdccdone false ch_gttxreset false ch_txdebugpcsout false ch_txpmaresetdone false ch_txprogdivresetdone false ch_txresetdone false ch_txmstresetdone false ch_txinhibit false ch_txlatclk false ch_txmaincursor false ch_txpcsresetmask false ch_txpd false ch_txpisopd false ch_txpmaresetmask false ch_txpolarity false ch_txpostcursor false ch_txprbsforceerr false ch_txprbssel false ch_txprecursor false ch_txprecursor2 false ch_txprecursor3 false ch_txprogdivreset false ch_txrate true ch_txresetmode false ch_txmstreset false ch_txmstdatapathreset false ch_txuserrdy false ch_txrsv0 false ch_txrsv1 false ch_txperst false ch_txqprbsen false ch_txheader false ch_txsequence false ch_txphalignresetmask false ch_txcominit false ch_txcomsas false ch_txcomwake false ch_txdapicodeovrden false ch_txdapicodereset false ch_txdetectrx false ch_txphdlytstclk false ch_txdlyalignreq false ch_txelecidle false ch_txmldchaindone false ch_tx",
-            "mldchainreq false ch_txoneszeros false ch_txpausedelayalign false ch_txphalignreq false ch_txphdlypd false ch_txphdlyreset false ch_txphsetinitreq false ch_txphshift180 false ch_txpicodeovrden false ch_txpicodereset false ch_txpippmen false ch_txswing false ch_txsyncallin false ch_tx10gstat false ch_txcomfinish false ch_txdlyalignerr false ch_txdlyalignprog false ch_txphaligndone false ch_txphalignerr false ch_txphalignoutrsvd false ch_txphdlyresetdone false ch_txphsetinitdone false ch_txphshift180done false ch_txsyncdone false ch_txctrl0 true ch_txctrl1 true ch_txctrl2 true ch_txdeemph false ch_txmargin false ch_txdiffctrl false ch_txpippmstepsize false ch_txdataextendrsvd false ch_txdapiresetdone false ch_txqpisenn false ch_txqpisenp false ch_txswingouthigh false ch_txswingoutlow false ch_txdapireset false ch_txdapiresetmask false ch_txqpibiasen false ch_txqpiweakpu false ch_txsimplexphystatus false ch_rxbufstatus false ch_rxcdrlock false ch_rxdebugpcsout false ch_rxpmaresetdone fal",
-            "se ch_rxprbserr false ch_rxprbslocked false ch_rxcdrhold false ch_rxcdrovrden false ch_rxlatclk false ch_rxpcsresetmask false ch_rxpd false ch_rxperst false ch_rxpmaresetmask false ch_rxpolarity false ch_rxprbscntreset false ch_rxqprbsen false ch_rxrate true ch_rxmstresetdone false ch_rxresetmode false ch_rxmstreset false ch_rxmstdatapathreset false ch_rxrsv0 false ch_rxrsv1 false ch_rxrsv2 false ch_rxuserrdy false ch_rxdata true ch_rx10gstat false ch_rxdatavalid false ch_rxheader false ch_rxchanisaligned false ch_rxchanrealign false ch_rxchbondi false ch_rxchbondo false ch_rxclkcorcnt false ch_rxcominitdet false ch_rxcommadet false ch_rxbyteisaligned false ch_rxbyterealign false ch_rxcomsasdet false ch_rxcomwakedet false ch_rxctrl0 false ch_rxctrl1 false ch_rxctrl2 false ch_rxctrl3 false ch_rxdapicodeovrden false ch_rxdapicodereset false ch_rxdlyalignerr false ch_rxdlyalignprog false ch_rxdlyalignreq false ch_rxelecidle false ch_rxeqtraining false ch_rxfinealigndone false ch_rxgearbo",
-            "xslip false ch_rxheadervalid false ch_rxlpmen false ch_rxmldchaindone false ch_rxmldchainreq false ch_rxmlfinealignreq false ch_rxoobreset false ch_rxosintdone false ch_rxphaligndone false ch_rxphalignerr false ch_rxphalignreq false ch_rxphalignresetmask false ch_rxphdlypd false ch_rxphdlyreset false ch_rxphdlyresetdone false ch_rxphsetinitreq false ch_rxphshift180 false ch_rxphshift180done false ch_rxphsetinitdone false ch_rxslide false ch_rxsliderdy false ch_rxstartofseq false ch_rxstatus false ch_rxsyncallin false ch_rxsyncdone false ch_rxtermination false ch_rxvalid false ch_rxchanbondseq false ch_rxchanbond_busy false ch_rxchanbond_en false ch_rxchanbond_master false ch_rxchanbond_slave false ch_rxchanbond_level false ch_cdrbmcdrreq false ch_cdrfreqos false ch_cdrincpctrl false ch_cdrstepdir false ch_cdrstepsq false ch_cdrstepsx false ch_eyescanreset false ch_eyescantrigger false ch_eyescandataerror false ch_cfokovrdrdy0 false ch_cfokovrdrdy1 false ch_rxdataextendrsvd false ch_rx",
-            "dccdone false ch_rxosintstarted false ch_rxosintstrobedone false ch_cfokovrdfinish false ch_cfokovrdpulse false ch_cfokovrdstart false ch_refdebugout false ch_rxdapiresetdone false ch_rxpkdet false ch_rxqpisenn false ch_rxqpisenp false ch_rxsimplexphystatus false ch_rxslipdone false ch_dfehold false ch_dfeovrd false ch_rxdapireset false ch_rxdapiresetmask false ch_rxqpien false ch_rxcdrphdone false ch_gtrxreset false ch_rxprogdivresetdone false ch_rxresetdone false ch_rxcdrreset false ch_rxprbscntstop false ch_rxprbssel false ch_rxprogdivreset false ch_rxosintstrobestarted false INTF_LR_SETTINGS {LR0_SETTINGS {GT_DIRECTION DUPLEX GT_TYPE GTYP INS_LOSS_NYQ 20 INTERNAL_PRESET None OOB_ENABLE false PCIE_ENABLE false PCIE_USERCLK2_FREQ 250 PCIE_USERCLK_FREQ 250 PRESET None RESET_SEQUENCE_INTERVAL 0 RXPROGDIV_FREQ_ENABLE true RXPROGDIV_FREQ_SOURCE LCPLL RXPROGDIV_FREQ_VAL 402.832 RXRECCLK_FREQ_ENABLE true RXRECCLK_FREQ_VAL 805.664 RX_64B66B_CRC false RX_64B66B_DECODER false RX_64B66B_DESCR",
-            "AMBLER false RX_ACTUAL_REFCLK_FREQUENCY 156.250000000000 RX_BUFFER_BYPASS_MODE Fast_Sync RX_BUFFER_BYPASS_MODE_LANE MULTI RX_BUFFER_MODE 1 RX_BUFFER_RESET_ON_CB_CHANGE ENABLE RX_BUFFER_RESET_ON_COMMAALIGN DISABLE RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE RX_CB_DISP_0_0 false RX_CB_DISP_0_1 false RX_CB_DISP_0_2 false RX_CB_DISP_0_3 false RX_CB_DISP_1_0 false RX_CB_DISP_1_1 false RX_CB_DISP_1_2 false RX_CB_DISP_1_3 false RX_CB_K_0_0 false RX_CB_K_0_1 false RX_CB_K_0_2 false RX_CB_K_0_3 false RX_CB_K_1_0 false RX_CB_K_1_1 false RX_CB_K_1_2 false RX_CB_K_1_3 false RX_CB_LEN_SEQ 1 RX_CB_MASK_0_0 false RX_CB_MASK_0_1 false RX_CB_MASK_0_2 false RX_CB_MASK_0_3 false RX_CB_MASK_1_0 false RX_CB_MASK_1_1 false RX_CB_MASK_1_2 false RX_CB_MASK_1_3 false RX_CB_MAX_LEVEL 1 RX_CB_MAX_SKEW 1 RX_CB_NUM_SEQ 0 RX_CB_VAL_0_0 00000000 RX_CB_VAL_0_1 00000000 RX_CB_VAL_0_2 00000000 RX_CB_VAL_0_3 00000000 RX_CB_VAL_1_0 00000000 RX_CB_VAL_1_1 00000000 RX_CB_VAL_1_2 00000000 RX_CB_VAL_1_3 00000000 RX_CC_DISP_0_0 fa",
-            "lse RX_CC_DISP_0_1 false RX_CC_DISP_0_2 false RX_CC_DISP_0_3 false RX_CC_DISP_1_0 false RX_CC_DISP_1_1 false RX_CC_DISP_1_2 false RX_CC_DISP_1_3 false RX_CC_KEEP_IDLE DISABLE RX_CC_K_0_0 false RX_CC_K_0_1 false RX_CC_K_0_2 false RX_CC_K_0_3 false RX_CC_K_1_0 false RX_CC_K_1_1 false RX_CC_K_1_2 false RX_CC_K_1_3 false RX_CC_LEN_SEQ 1 RX_CC_MASK_0_0 false RX_CC_MASK_0_1 false RX_CC_MASK_0_2 false RX_CC_MASK_0_3 false RX_CC_MASK_1_0 false RX_CC_MASK_1_1 false RX_CC_MASK_1_2 false RX_CC_MASK_1_3 false RX_CC_NUM_SEQ 0 RX_CC_PERIODICITY 5000 RX_CC_PRECEDENCE ENABLE RX_CC_REPEAT_WAIT 0 RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 RX_CC_VAL_0_0 00000000 RX_CC_VAL_0_1 00000000 RX_CC_VAL_0_2 00000000 RX_CC_VAL_0_3 00000000 RX_CC_VAL_1_0 00000000 RX_CC_VAL_1_1 00000000 RX_CC_VAL_1_2 00000000 RX_CC_VAL_1_3 00000000 RX_COMMA_ALIGN_WORD 1 RX_COMMA_DOUBLE_ENABLE false RX_COMMA_MASK 0000000000 RX_COMMA_M_ENABLE false RX_COMMA_M_VAL 1010000011 RX_COMMA_PRE",
-            "SET NONE RX_COMMA_P_ENABLE false RX_COMMA_P_VAL 0101111100 RX_COMMA_SHOW_REALIGN_ENABLE true RX_COMMA_VALID_ONLY 0 RX_COUPLING AC RX_DATA_DECODING RAW RX_EQ_MODE AUTO RX_FRACN_ENABLED true RX_FRACN_NUMERATOR 0 RX_FRACN_OVRD false RX_GRAY_BYP true RX_GRAY_LITTLEENDIAN true RX_HD_EN 0 RX_INT_DATA_WIDTH 64 RX_JTOL_FC 10 RX_JTOL_LF_SLOPE -20 RX_LINE_RATE 25.78125 RX_OUTCLK_SOURCE RXPROGDIVCLK RX_PAM_SEL NRZ RX_PLL_TYPE LCPLL RX_PPM_OFFSET 0 RX_PRECODE_BYP true RX_PRECODE_LITTLEENDIAN false RX_RATE_GROUP A RX_REFCLK_FREQUENCY 156.25 RX_REFCLK_SOURCE R1 RX_SLIDE_MODE OFF RX_SSC_PPM 0 RX_TERMINATION PROGRAMMABLE RX_TERMINATION_PROG_VALUE 800 RX_USER_DATA_WIDTH 64 TXPROGDIV_FREQ_ENABLE true TXPROGDIV_FREQ_SOURCE RPLL TXPROGDIV_FREQ_VAL 240.474 TX_64B66B_CRC false TX_64B66B_ENCODER false TX_64B66B_SCRAMBLER false TX_ACTUAL_REFCLK_FREQUENCY 240.474000000000 TX_BUFFER_BYPASS_MODE Fast_Sync TX_BUFFER_MODE 1 TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE TX_DATA_ENCODING 8B10B TX_DIFF_SWING_EMPH_MODE CUSTO",
-            "M TX_FRACN_ENABLED false TX_FRACN_NUMERATOR 0 TX_FRACN_OVRD false TX_GRAY_BYP true TX_GRAY_LITTLEENDIAN true TX_HD_EN 0 TX_INT_DATA_WIDTH 40 TX_LANE_DESKEW_HDMI_ENABLE false TX_LINE_RATE 9.61896 TX_OUTCLK_SOURCE TXPROGDIVCLK TX_PAM_SEL NRZ TX_PIPM_ENABLE false TX_PLL_TYPE RPLL TX_PRECODE_BYP true TX_PRECODE_LITTLEENDIAN false TX_RATE_GROUP A TX_REFCLK_FREQUENCY 240.474 TX_REFCLK_SOURCE R0 TX_USER_DATA_WIDTH 32} LR1_SETTINGS { } LR2_SETTINGS { } LR3_SETTINGS { } LR4_SETTINGS { } LR5_SETTINGS { } LR6_SETTINGS { } LR7_SETTINGS { } LR8_SETTINGS { } LR9_SETTINGS { } LR10_SETTINGS { } LR11_SETTINGS { } LR12_SETTINGS { } LR13_SETTINGS { } LR14_SETTINGS { } LR15_SETTINGS { }} LOCATE_RESETIP CORE CHANNEL_BONDING false ALL_PORTS false"
+            "GT_TYPE GTYP GT_DIRECTION DUPLEX ch_txdata true ch_txbufstatus true ch_txdccdone false ch_gttxreset false ch_txdebugpcsout false ch_txpmaresetdone false ch_txprogdivresetdone false ch_txresetdone false ch_txmstresetdone false ch_txinhibit false ch_txlatclk false ch_txmaincursor false ch_txpcsresetmask false ch_txpd false ch_txpisopd false ch_txpmaresetmask false ch_txpolarity true ch_txpostcursor false ch_txprbsforceerr false ch_txprbssel false ch_txprecursor false ch_txprecursor2 false ch_txprecursor3 false ch_txprogdivreset false ch_txrate true ch_txresetmode false ch_txmstreset false ch_txmstdatapathreset false ch_txuserrdy false ch_txrsv0 false ch_txrsv1 false ch_txperst false ch_txqprbsen false ch_txheader false ch_txsequence false ch_txphalignresetmask false ch_txcominit false ch_txcomsas false ch_txcomwake false ch_txdapicodeovrden false ch_txdapicodereset false ch_txdetectrx false ch_txphdlytstclk false ch_txdlyalignreq false ch_txelecidle false ch_txmldchaindone false ch_txml",
+            "dchainreq false ch_txoneszeros false ch_txpausedelayalign false ch_txphalignreq false ch_txphdlypd false ch_txphdlyreset false ch_txphsetinitreq false ch_txphshift180 false ch_txpicodeovrden false ch_txpicodereset false ch_txpippmen true ch_txswing false ch_txsyncallin false ch_tx10gstat false ch_txcomfinish false ch_txdlyalignerr false ch_txdlyalignprog false ch_txphaligndone false ch_txphalignerr false ch_txphalignoutrsvd false ch_txphdlyresetdone false ch_txphsetinitdone false ch_txphshift180done false ch_txsyncdone false ch_txctrl0 true ch_txctrl1 true ch_txctrl2 true ch_txdeemph false ch_txmargin false ch_txdiffctrl false ch_txpippmstepsize true ch_txdataextendrsvd false ch_txdapiresetdone false ch_txqpisenn false ch_txqpisenp false ch_txswingouthigh false ch_txswingoutlow false ch_txdapireset false ch_txdapiresetmask false ch_txqpibiasen false ch_txqpiweakpu false ch_txsimplexphystatus false ch_rxbufstatus false ch_rxcdrlock false ch_rxdebugpcsout false ch_rxpmaresetdone false c",
+            "h_rxprbserr false ch_rxprbslocked false ch_rxcdrhold false ch_rxcdrovrden false ch_rxlatclk false ch_rxpcsresetmask false ch_rxpd false ch_rxperst false ch_rxpmaresetmask false ch_rxpolarity true ch_rxprbscntreset false ch_rxqprbsen false ch_rxrate true ch_rxmstresetdone false ch_rxresetmode false ch_rxmstreset false ch_rxmstdatapathreset false ch_rxrsv0 false ch_rxrsv1 false ch_rxrsv2 false ch_rxuserrdy false ch_rxdata true ch_rx10gstat false ch_rxdatavalid false ch_rxheader false ch_rxchanisaligned false ch_rxchanrealign false ch_rxchbondi false ch_rxchbondo false ch_rxclkcorcnt false ch_rxcominitdet false ch_rxcommadet false ch_rxbyteisaligned false ch_rxbyterealign false ch_rxcomsasdet false ch_rxcomwakedet false ch_rxctrl0 false ch_rxctrl1 false ch_rxctrl2 false ch_rxctrl3 false ch_rxdapicodeovrden false ch_rxdapicodereset false ch_rxdlyalignerr false ch_rxdlyalignprog false ch_rxdlyalignreq false ch_rxelecidle false ch_rxeqtraining false ch_rxfinealigndone false ch_rxgearboxslip",
+            " false ch_rxheadervalid false ch_rxlpmen false ch_rxmldchaindone false ch_rxmldchainreq false ch_rxmlfinealignreq false ch_rxoobreset false ch_rxosintdone false ch_rxphaligndone false ch_rxphalignerr false ch_rxphalignreq false ch_rxphalignresetmask false ch_rxphdlypd false ch_rxphdlyreset false ch_rxphdlyresetdone false ch_rxphsetinitreq false ch_rxphshift180 false ch_rxphshift180done false ch_rxphsetinitdone false ch_rxslide false ch_rxsliderdy false ch_rxstartofseq false ch_rxstatus false ch_rxsyncallin false ch_rxsyncdone false ch_rxtermination false ch_rxvalid false ch_rxchanbondseq false ch_rxchanbond_busy false ch_rxchanbond_en false ch_rxchanbond_master false ch_rxchanbond_slave false ch_rxchanbond_level false ch_cdrbmcdrreq false ch_cdrfreqos false ch_cdrincpctrl false ch_cdrstepdir false ch_cdrstepsq false ch_cdrstepsx false ch_eyescanreset false ch_eyescantrigger false ch_eyescandataerror false ch_cfokovrdrdy0 false ch_cfokovrdrdy1 false ch_rxdataextendrsvd false ch_rxdccdo",
+            "ne false ch_rxosintstarted false ch_rxosintstrobedone false ch_cfokovrdfinish false ch_cfokovrdpulse false ch_cfokovrdstart false ch_refdebugout false ch_rxdapiresetdone false ch_rxpkdet false ch_rxqpisenn false ch_rxqpisenp false ch_rxsimplexphystatus false ch_rxslipdone false ch_dfehold false ch_dfeovrd false ch_rxdapireset false ch_rxdapiresetmask false ch_rxqpien false ch_rxcdrphdone false ch_gtrxreset false ch_rxprogdivresetdone false ch_rxresetdone false ch_rxcdrreset false ch_rxprbscntstop false ch_rxprbssel false ch_rxprogdivreset false ch_rxosintstrobestarted false INTF_LR_SETTINGS {LR0_SETTINGS {GT_DIRECTION DUPLEX GT_TYPE GTYP INS_LOSS_NYQ 20 INTERNAL_PRESET None OOB_ENABLE false PCIE_ENABLE false PCIE_USERCLK2_FREQ 250 PCIE_USERCLK_FREQ 250 PRESET None RESET_SEQUENCE_INTERVAL 0 RXPROGDIV_FREQ_ENABLE true RXPROGDIV_FREQ_SOURCE LCPLL RXPROGDIV_FREQ_VAL 402.832 RXRECCLK_FREQ_ENABLE true RXRECCLK_FREQ_VAL 805.664 RX_64B66B_CRC false RX_64B66B_DECODER false RX_64B66B_DESCRAMBLE",
+            "R false RX_ACTUAL_REFCLK_FREQUENCY 156.250000000000 RX_BUFFER_BYPASS_MODE Fast_Sync RX_BUFFER_BYPASS_MODE_LANE MULTI RX_BUFFER_MODE 1 RX_BUFFER_RESET_ON_CB_CHANGE ENABLE RX_BUFFER_RESET_ON_COMMAALIGN DISABLE RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE RX_CB_DISP_0_0 false RX_CB_DISP_0_1 false RX_CB_DISP_0_2 false RX_CB_DISP_0_3 false RX_CB_DISP_1_0 false RX_CB_DISP_1_1 false RX_CB_DISP_1_2 false RX_CB_DISP_1_3 false RX_CB_K_0_0 false RX_CB_K_0_1 false RX_CB_K_0_2 false RX_CB_K_0_3 false RX_CB_K_1_0 false RX_CB_K_1_1 false RX_CB_K_1_2 false RX_CB_K_1_3 false RX_CB_LEN_SEQ 1 RX_CB_MASK_0_0 false RX_CB_MASK_0_1 false RX_CB_MASK_0_2 false RX_CB_MASK_0_3 false RX_CB_MASK_1_0 false RX_CB_MASK_1_1 false RX_CB_MASK_1_2 false RX_CB_MASK_1_3 false RX_CB_MAX_LEVEL 1 RX_CB_MAX_SKEW 1 RX_CB_NUM_SEQ 0 RX_CB_VAL_0_0 00000000 RX_CB_VAL_0_1 00000000 RX_CB_VAL_0_2 00000000 RX_CB_VAL_0_3 00000000 RX_CB_VAL_1_0 00000000 RX_CB_VAL_1_1 00000000 RX_CB_VAL_1_2 00000000 RX_CB_VAL_1_3 00000000 RX_CC_DISP_0_0 false R",
+            "X_CC_DISP_0_1 false RX_CC_DISP_0_2 false RX_CC_DISP_0_3 false RX_CC_DISP_1_0 false RX_CC_DISP_1_1 false RX_CC_DISP_1_2 false RX_CC_DISP_1_3 false RX_CC_KEEP_IDLE DISABLE RX_CC_K_0_0 false RX_CC_K_0_1 false RX_CC_K_0_2 false RX_CC_K_0_3 false RX_CC_K_1_0 false RX_CC_K_1_1 false RX_CC_K_1_2 false RX_CC_K_1_3 false RX_CC_LEN_SEQ 1 RX_CC_MASK_0_0 false RX_CC_MASK_0_1 false RX_CC_MASK_0_2 false RX_CC_MASK_0_3 false RX_CC_MASK_1_0 false RX_CC_MASK_1_1 false RX_CC_MASK_1_2 false RX_CC_MASK_1_3 false RX_CC_NUM_SEQ 0 RX_CC_PERIODICITY 5000 RX_CC_PRECEDENCE ENABLE RX_CC_REPEAT_WAIT 0 RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 RX_CC_VAL_0_0 00000000 RX_CC_VAL_0_1 00000000 RX_CC_VAL_0_2 00000000 RX_CC_VAL_0_3 00000000 RX_CC_VAL_1_0 00000000 RX_CC_VAL_1_1 00000000 RX_CC_VAL_1_2 00000000 RX_CC_VAL_1_3 00000000 RX_COMMA_ALIGN_WORD 1 RX_COMMA_DOUBLE_ENABLE false RX_COMMA_MASK 0000000000 RX_COMMA_M_ENABLE false RX_COMMA_M_VAL 1010000011 RX_COMMA_PRESET N",
+            "ONE RX_COMMA_P_ENABLE false RX_COMMA_P_VAL 0101111100 RX_COMMA_SHOW_REALIGN_ENABLE true RX_COMMA_VALID_ONLY 0 RX_COUPLING AC RX_DATA_DECODING RAW RX_EQ_MODE AUTO RX_FRACN_ENABLED true RX_FRACN_NUMERATOR 0 RX_FRACN_OVRD false RX_GRAY_BYP true RX_GRAY_LITTLEENDIAN true RX_HD_EN 0 RX_INT_DATA_WIDTH 64 RX_JTOL_FC 10 RX_JTOL_LF_SLOPE -20 RX_LINE_RATE 25.78125 RX_OUTCLK_SOURCE RXPROGDIVCLK RX_PAM_SEL NRZ RX_PLL_TYPE LCPLL RX_PPM_OFFSET 0 RX_PRECODE_BYP true RX_PRECODE_LITTLEENDIAN false RX_RATE_GROUP A RX_REFCLK_FREQUENCY 156.25 RX_REFCLK_SOURCE R1 RX_SLIDE_MODE OFF RX_SSC_PPM 0 RX_TERMINATION PROGRAMMABLE RX_TERMINATION_PROG_VALUE 800 RX_USER_DATA_WIDTH 64 TXPROGDIV_FREQ_ENABLE true TXPROGDIV_FREQ_SOURCE RPLL TXPROGDIV_FREQ_VAL 240.474 TX_64B66B_CRC false TX_64B66B_ENCODER false TX_64B66B_SCRAMBLER false TX_ACTUAL_REFCLK_FREQUENCY 240.474000000000 TX_BUFFER_BYPASS_MODE Fast_Sync TX_BUFFER_MODE 1 TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE TX_DATA_ENCODING 8B10B TX_DIFF_SWING_EMPH_MODE CUSTOM TX_",
+            "FRACN_ENABLED false TX_FRACN_NUMERATOR 0 TX_FRACN_OVRD false TX_GRAY_BYP true TX_GRAY_LITTLEENDIAN true TX_HD_EN 0 TX_INT_DATA_WIDTH 40 TX_LANE_DESKEW_HDMI_ENABLE false TX_LINE_RATE 9.61896 TX_OUTCLK_SOURCE TXPROGDIVCLK TX_PAM_SEL NRZ TX_PIPM_ENABLE false TX_PLL_TYPE RPLL TX_PRECODE_BYP true TX_PRECODE_LITTLEENDIAN false TX_RATE_GROUP A TX_REFCLK_FREQUENCY 240.474 TX_REFCLK_SOURCE R0 TX_USER_DATA_WIDTH 32} LR1_SETTINGS { } LR2_SETTINGS { } LR3_SETTINGS { } LR4_SETTINGS { } LR5_SETTINGS { } LR6_SETTINGS { } LR7_SETTINGS { } LR8_SETTINGS { } LR9_SETTINGS { } LR10_SETTINGS { } LR11_SETTINGS { } LR12_SETTINGS { } LR13_SETTINGS { } LR14_SETTINGS { } LR15_SETTINGS { }} LOCATE_RESETIP CORE CHANNEL_BONDING false ALL_PORTS false"
             ], "resolve_type": "user", "usage": "all", "data_type": "tcldict:internal" } ],
         "INTF1_TXRX_OPTIONAL_PORTS": [ { "value": [
             "GT_TYPE GTYP GT_DIRECTION DUPLEX ch_txdata true ch_txbufstatus false ch_txdccdone false ch_gttxreset false ch_txdebugpcsout false ch_txpmaresetdone false ch_txprogdivresetdone false ch_txresetdone false ch_txmstresetdone false ch_txinhibit false ch_txlatclk false ch_txmaincursor false ch_txpcsresetmask false ch_txpd false ch_txpisopd false ch_txpmaresetmask false ch_txpolarity false ch_txpostcursor false ch_txprbsforceerr false ch_txprbssel false ch_txprecursor false ch_txprecursor2 false ch_txprecursor3 false ch_txprogdivreset false ch_txrate true ch_txresetmode false ch_txmstreset false ch_txmstdatapathreset false ch_txuserrdy false ch_txrsv0 false ch_txrsv1 false ch_txperst false ch_txqprbsen false ch_txheader false ch_txsequence false ch_txphalignresetmask false ch_txcominit false ch_txcomsas false ch_txcomwake false ch_txdapicodeovrden false ch_txdapicodereset false ch_txdetectrx false ch_txphdlytstclk false ch_txdlyalignreq false ch_txelecidle false ch_txmldchaindone false ch_tx",
@@ -1212,7 +1212,7 @@
             "RESET NONE RX_COMMA_P_ENABLE false RX_COMMA_P_VAL 0101111100 RX_COMMA_SHOW_REALIGN_ENABLE true RX_COMMA_VALID_ONLY 0 RX_COUPLING AC RX_DATA_DECODING RAW RX_EQ_MODE AUTO RX_FRACN_ENABLED false RX_FRACN_NUMERATOR 0 RX_FRACN_OVRD false RX_GRAY_BYP true RX_GRAY_LITTLEENDIAN true RX_HD_EN 0 RX_INT_DATA_WIDTH 32 RX_JTOL_FC 6.1862627 RX_JTOL_LF_SLOPE -20 RX_LINE_RATE 10.3125 RX_OUTCLK_SOURCE RXOUTCLKPMA RX_PAM_SEL NRZ RX_PLL_TYPE LCPLL RX_PPM_OFFSET 0 RX_PRECODE_BYP true RX_PRECODE_LITTLEENDIAN false RX_RATE_GROUP A RX_REFCLK_FREQUENCY 156.25 RX_REFCLK_SOURCE R0 RX_SLIDE_MODE OFF RX_SSC_PPM 0 RX_TERMINATION PROGRAMMABLE RX_TERMINATION_PROG_VALUE 800 RX_USER_DATA_WIDTH 32 TXPROGDIV_FREQ_ENABLE false TXPROGDIV_FREQ_SOURCE LCPLL TXPROGDIV_FREQ_VAL 322.265625 TX_64B66B_CRC false TX_64B66B_ENCODER false TX_64B66B_SCRAMBLER false TX_ACTUAL_REFCLK_FREQUENCY 156.250000000000 TX_BUFFER_BYPASS_MODE Fast_Sync TX_BUFFER_MODE 1 TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE TX_DATA_ENCODING RAW TX_DIFF_SWING_EMPH",
             "_MODE CUSTOM TX_FRACN_ENABLED false TX_FRACN_NUMERATOR 0 TX_FRACN_OVRD false TX_GRAY_BYP true TX_GRAY_LITTLEENDIAN true TX_HD_EN 0 TX_INT_DATA_WIDTH 32 TX_LANE_DESKEW_HDMI_ENABLE false TX_LINE_RATE 10.3125 TX_OUTCLK_SOURCE TXOUTCLKPMA TX_PAM_SEL NRZ TX_PIPM_ENABLE false TX_PLL_TYPE LCPLL TX_PRECODE_BYP true TX_PRECODE_LITTLEENDIAN false TX_RATE_GROUP A TX_REFCLK_FREQUENCY 156.25 TX_REFCLK_SOURCE R0 TX_USER_DATA_WIDTH 32} LR1_SETTINGS { } LR2_SETTINGS { } LR3_SETTINGS { } LR4_SETTINGS { } LR5_SETTINGS { } LR6_SETTINGS { } LR7_SETTINGS { } LR8_SETTINGS { } LR9_SETTINGS { } LR10_SETTINGS { } LR11_SETTINGS { } LR12_SETTINGS { } LR13_SETTINGS { } LR14_SETTINGS { } LR15_SETTINGS { }} LOCATE_RESETIP CORE CHANNEL_BONDING false ALL_PORTS false"
             ], "resolve_type": "user", "usage": "all", "data_type": "tcldict:internal" } ],
-        "INTF0_OPTIONAL_PORTS": [ { "value": "", "resolve_type": "user", "usage": "all", "data_type": "tcldict" } ],
+        "INTF0_OPTIONAL_PORTS": [ { "value": "ch_rxpolarity true ch_txbufstatus true ch_txpippmen true ch_txpippmstepsize true ch_txpolarity true", "value_src": "user", "resolve_type": "user", "usage": "all", "data_type": "tcldict" } ],
         "INTF1_OPTIONAL_PORTS": [ { "value": "", "resolve_type": "user", "usage": "all", "data_type": "tcldict" } ],
         "INTF2_OPTIONAL_PORTS": [ { "value": "", "resolve_type": "user", "usage": "all", "data_type": "tcldict" } ],
         "INTF3_OPTIONAL_PORTS": [ { "value": "", "resolve_type": "user", "usage": "all", "data_type": "tcldict" } ],
@@ -1724,31 +1724,51 @@
         "QUAD0_RX2_usrclk": [ { "direction": "in", "driver_value": "0" } ],
         "QUAD0_RX3_usrclk": [ { "direction": "in", "driver_value": "0" } ],
         "INTF0_TX0_ch_txdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX0_ch_txbufstatus": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "INTF0_TX0_ch_txpolarity": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX0_ch_txrate": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX0_ch_txpippmen": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX0_ch_txctrl0": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX0_ch_txctrl1": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX0_ch_txctrl2": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX0_ch_txpippmstepsize": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX1_ch_txdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX1_ch_txbufstatus": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "INTF0_TX1_ch_txpolarity": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX1_ch_txrate": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX1_ch_txpippmen": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX1_ch_txctrl0": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX1_ch_txctrl1": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX1_ch_txctrl2": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX1_ch_txpippmstepsize": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX2_ch_txdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX2_ch_txbufstatus": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "INTF0_TX2_ch_txpolarity": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX2_ch_txrate": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX2_ch_txpippmen": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX2_ch_txctrl0": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX2_ch_txctrl1": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX2_ch_txctrl2": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX2_ch_txpippmstepsize": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX3_ch_txdata": [ { "direction": "in", "size_left": "127", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX3_ch_txbufstatus": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "INTF0_TX3_ch_txpolarity": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX3_ch_txrate": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX3_ch_txpippmen": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX3_ch_txctrl0": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX3_ch_txctrl1": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
         "INTF0_TX3_ch_txctrl2": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_TX3_ch_txpippmstepsize": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0" } ],
+        "INTF0_RX0_ch_rxpolarity": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_RX0_ch_rxrate": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
         "INTF0_RX0_ch_rxdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ],
+        "INTF0_RX1_ch_rxpolarity": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_RX1_ch_rxrate": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
         "INTF0_RX1_ch_rxdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ],
+        "INTF0_RX2_ch_rxpolarity": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_RX2_ch_rxrate": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
         "INTF0_RX2_ch_rxdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ],
+        "INTF0_RX3_ch_rxpolarity": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "INTF0_RX3_ch_rxrate": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
         "INTF0_RX3_ch_rxdata": [ { "direction": "out", "size_left": "127", "size_right": "0" } ],
         "INTF0_TX_clr_out": [ { "direction": "out" } ],
@@ -2096,10 +2116,14 @@
           },
           "port_maps": {
             "ch_txdata": [ { "physical_name": "INTF0_TX0_ch_txdata" } ],
+            "ch_txbufstatus": [ { "physical_name": "INTF0_TX0_ch_txbufstatus" } ],
+            "ch_txpolarity": [ { "physical_name": "INTF0_TX0_ch_txpolarity" } ],
             "ch_txrate": [ { "physical_name": "INTF0_TX0_ch_txrate" } ],
+            "ch_txpippmen": [ { "physical_name": "INTF0_TX0_ch_txpippmen" } ],
             "ch_txctrl0": [ { "physical_name": "INTF0_TX0_ch_txctrl0" } ],
             "ch_txctrl1": [ { "physical_name": "INTF0_TX0_ch_txctrl1" } ],
-            "ch_txctrl2": [ { "physical_name": "INTF0_TX0_ch_txctrl2" } ]
+            "ch_txctrl2": [ { "physical_name": "INTF0_TX0_ch_txctrl2" } ],
+            "ch_txpippmstepsize": [ { "physical_name": "INTF0_TX0_ch_txpippmstepsize" } ]
           }
         },
         "INTF0_TX1_GT_IP_Interface": {
@@ -2118,10 +2142,14 @@
           },
           "port_maps": {
             "ch_txdata": [ { "physical_name": "INTF0_TX1_ch_txdata" } ],
+            "ch_txbufstatus": [ { "physical_name": "INTF0_TX1_ch_txbufstatus" } ],
+            "ch_txpolarity": [ { "physical_name": "INTF0_TX1_ch_txpolarity" } ],
             "ch_txrate": [ { "physical_name": "INTF0_TX1_ch_txrate" } ],
+            "ch_txpippmen": [ { "physical_name": "INTF0_TX1_ch_txpippmen" } ],
             "ch_txctrl0": [ { "physical_name": "INTF0_TX1_ch_txctrl0" } ],
             "ch_txctrl1": [ { "physical_name": "INTF0_TX1_ch_txctrl1" } ],
-            "ch_txctrl2": [ { "physical_name": "INTF0_TX1_ch_txctrl2" } ]
+            "ch_txctrl2": [ { "physical_name": "INTF0_TX1_ch_txctrl2" } ],
+            "ch_txpippmstepsize": [ { "physical_name": "INTF0_TX1_ch_txpippmstepsize" } ]
           }
         },
         "INTF0_TX2_GT_IP_Interface": {
@@ -2140,10 +2168,14 @@
           },
           "port_maps": {
             "ch_txdata": [ { "physical_name": "INTF0_TX2_ch_txdata" } ],
+            "ch_txbufstatus": [ { "physical_name": "INTF0_TX2_ch_txbufstatus" } ],
+            "ch_txpolarity": [ { "physical_name": "INTF0_TX2_ch_txpolarity" } ],
             "ch_txrate": [ { "physical_name": "INTF0_TX2_ch_txrate" } ],
+            "ch_txpippmen": [ { "physical_name": "INTF0_TX2_ch_txpippmen" } ],
             "ch_txctrl0": [ { "physical_name": "INTF0_TX2_ch_txctrl0" } ],
             "ch_txctrl1": [ { "physical_name": "INTF0_TX2_ch_txctrl1" } ],
-            "ch_txctrl2": [ { "physical_name": "INTF0_TX2_ch_txctrl2" } ]
+            "ch_txctrl2": [ { "physical_name": "INTF0_TX2_ch_txctrl2" } ],
+            "ch_txpippmstepsize": [ { "physical_name": "INTF0_TX2_ch_txpippmstepsize" } ]
           }
         },
         "INTF0_TX3_GT_IP_Interface": {
@@ -2162,10 +2194,14 @@
           },
           "port_maps": {
             "ch_txdata": [ { "physical_name": "INTF0_TX3_ch_txdata" } ],
+            "ch_txbufstatus": [ { "physical_name": "INTF0_TX3_ch_txbufstatus" } ],
+            "ch_txpolarity": [ { "physical_name": "INTF0_TX3_ch_txpolarity" } ],
             "ch_txrate": [ { "physical_name": "INTF0_TX3_ch_txrate" } ],
+            "ch_txpippmen": [ { "physical_name": "INTF0_TX3_ch_txpippmen" } ],
             "ch_txctrl0": [ { "physical_name": "INTF0_TX3_ch_txctrl0" } ],
             "ch_txctrl1": [ { "physical_name": "INTF0_TX3_ch_txctrl1" } ],
-            "ch_txctrl2": [ { "physical_name": "INTF0_TX3_ch_txctrl2" } ]
+            "ch_txctrl2": [ { "physical_name": "INTF0_TX3_ch_txctrl2" } ],
+            "ch_txpippmstepsize": [ { "physical_name": "INTF0_TX3_ch_txpippmstepsize" } ]
           }
         },
         "INTF0_RX0_GT_IP_Interface": {
@@ -2183,6 +2219,7 @@
             "ADDITIONAL_CONFIG_ENABLE": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
+            "ch_rxpolarity": [ { "physical_name": "INTF0_RX0_ch_rxpolarity" } ],
             "ch_rxrate": [ { "physical_name": "INTF0_RX0_ch_rxrate" } ],
             "ch_rxdata": [ { "physical_name": "INTF0_RX0_ch_rxdata" } ]
           }
@@ -2202,6 +2239,7 @@
             "ADDITIONAL_CONFIG_ENABLE": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
+            "ch_rxpolarity": [ { "physical_name": "INTF0_RX1_ch_rxpolarity" } ],
             "ch_rxrate": [ { "physical_name": "INTF0_RX1_ch_rxrate" } ],
             "ch_rxdata": [ { "physical_name": "INTF0_RX1_ch_rxdata" } ]
           }
@@ -2221,6 +2259,7 @@
             "ADDITIONAL_CONFIG_ENABLE": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
+            "ch_rxpolarity": [ { "physical_name": "INTF0_RX2_ch_rxpolarity" } ],
             "ch_rxrate": [ { "physical_name": "INTF0_RX2_ch_rxrate" } ],
             "ch_rxdata": [ { "physical_name": "INTF0_RX2_ch_rxdata" } ]
           }
@@ -2240,6 +2279,7 @@
             "ADDITIONAL_CONFIG_ENABLE": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
+            "ch_rxpolarity": [ { "physical_name": "INTF0_RX3_ch_rxpolarity" } ],
             "ch_rxrate": [ { "physical_name": "INTF0_RX3_ch_rxrate" } ],
             "ch_rxdata": [ { "physical_name": "INTF0_RX3_ch_rxdata" } ]
           }
