Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024
| Date         : Sun May 11 22:24:20 2025
| Host         : daq11.hep.ucl.ac.uk running 64-bit AlmaLinux 9.5 (Teal Serval)
| Command      : report_utilization -hierarchical -hierarchical_percentages -file /opt/scratch/warren/gitclones_while_nfs11_dead/gep-fw/bin/MainProject/MainProject_VPK180-v0.107.0-407189A/reports/hierarchical_utilization.txt
| Design       : GEP_top
| Device       : xcvp1802-lsvc4072-2MP-e-S
| Speed File   : -2MP
| Design State : Routed
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Utilization Design Information

Table of Contents
-----------------
1. Utilization by Hierarchy

1. Utilization by Hierarchy
---------------------------

+---------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+---------------+---------------+----------+-------------+---------------+-------------+-----------+----------+------------+
|                                           Instance                                          |                                           Module                                           |   Total LUTs  |   Logic LUTs  |  LUTRAMs |     SRLs    |      FFs      |    RAMB36   |   RAMB18  |   URAM   | DSP Blocks |
+---------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+---------------+---------------+----------+-------------+---------------+-------------+-----------+----------+------------+
| GEP_top                                                                                     |                                                                                      (top) | 129568(3.86%) | 128504(3.82%) | 0(0.00%) | 1064(0.06%) | 276092(4.11%) | 735(14.88%) | 11(0.11%) | 0(0.00%) |   0(0.00%) |
|   CLOCK_WIZARD                                                                              |                                                                                  clk_wiz_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     inst                                                                                    |                                                                      clk_wiz_0_clk_wiz_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       clock_primitive_inst                                                                  |                                                               clk_wiz_0_clocking_structure |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|   U_ipbus_infra                                                                             |                                                                                ipbus_infra |   8113(0.24%) |   8113(0.24%) | 0(0.00%) |    0(0.00%) |   3720(0.06%) |   64(1.30%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ipb_axi_inst_IN_SLR0                                                                    |                                                          ipbus_transport_axi_if__xdcDup__1 |    471(0.01%) |    471(0.01%) | 0(0.00%) |    0(0.00%) |    516(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (ipb_axi_inst_IN_SLR0)                                                                |                                                          ipbus_transport_axi_if__xdcDup__1 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       ram_to_trans                                                                          |                                                                ipbus_transport_ram_if_3179 |    138(0.01%) |    138(0.01%) | 0(0.00%) |    0(0.00%) |    121(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (ram_to_trans)                                                                      |                                                                ipbus_transport_ram_if_3179 |     41(0.01%) |     41(0.01%) | 0(0.00%) |    0(0.00%) |     79(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         multibuffer_if                                                                      |                                                        ipbus_transport_multibuffer_if_3180 |     97(0.01%) |     97(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (multibuffer_if)                                                                  |                                                        ipbus_transport_multibuffer_if_3180 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |     24(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cdc                                                                               |                                                       ipbus_transport_multibuffer_cdc_3181 |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rx_ram                                                                            |                                                  ipbus_transport_multibuffer_rx_dpram_3182 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    8(0.16%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           tx_ram                                                                            |                                                  ipbus_transport_multibuffer_tx_dpram_3183 |     48(0.01%) |     48(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    8(0.16%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       versal_decl_test.axi_bram_ctrl_versal                                                 |                                                                     axi_bram_ctrl_versal_0 |    330(0.01%) |    330(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (versal_decl_test.axi_bram_ctrl_versal)                                             |                                                                     axi_bram_ctrl_versal_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                       axi_bram_ctrl_versal_0_axi_bram_ctrl |    330(0.01%) |    330(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gext_inst.abcv4_0_ext_inst                                                        |                                                   axi_bram_ctrl_versal_0_axi_bram_ctrl_top |    330(0.01%) |    330(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             GEN_AXI4.I_FULL_AXI                                                             |                                                            axi_bram_ctrl_versal_0_full_axi |    330(0.01%) |    330(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_RD_CHNL                                                                     |                                                             axi_bram_ctrl_versal_0_rd_chnl |    199(0.01%) |    199(0.01%) | 0(0.00%) |    0(0.00%) |    240(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_RD_CHNL)                                                                 |                                                             axi_bram_ctrl_versal_0_rd_chnl |    155(0.01%) |    155(0.01%) | 0(0.00%) |    0(0.00%) |    225(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 GEN_NO_RD_CMD_OPT.I_WRAP_BRST                                               |                                                         axi_bram_ctrl_versal_0_wrap_brst_0 |     47(0.01%) |     47(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_WR_CHNL                                                                     |                                                             axi_bram_ctrl_versal_0_wr_chnl |    131(0.01%) |    131(0.01%) | 0(0.00%) |    0(0.00%) |    155(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_WR_CHNL)                                                                 |                                                             axi_bram_ctrl_versal_0_wr_chnl |     87(0.01%) |     87(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 BID_FIFO                                                                    |                                                            axi_bram_ctrl_versal_0_SRL_FIFO |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 I_WRAP_BRST                                                                 |                                                           axi_bram_ctrl_versal_0_wrap_brst |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ipb_axi_inst_IN_SLR1                                                                    |                                                          ipbus_transport_axi_if__xdcDup__2 |    466(0.01%) |    466(0.01%) | 0(0.00%) |    0(0.00%) |    515(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (ipb_axi_inst_IN_SLR1)                                                                |                                                          ipbus_transport_axi_if__xdcDup__2 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       ram_to_trans                                                                          |                                                                ipbus_transport_ram_if_3174 |    134(0.01%) |    134(0.01%) | 0(0.00%) |    0(0.00%) |    120(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (ram_to_trans)                                                                      |                                                                ipbus_transport_ram_if_3174 |     42(0.01%) |     42(0.01%) | 0(0.00%) |    0(0.00%) |     79(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         multibuffer_if                                                                      |                                                        ipbus_transport_multibuffer_if_3175 |     92(0.01%) |     92(0.01%) | 0(0.00%) |    0(0.00%) |     41(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (multibuffer_if)                                                                  |                                                        ipbus_transport_multibuffer_if_3175 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     23(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cdc                                                                               |                                                       ipbus_transport_multibuffer_cdc_3176 |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rx_ram                                                                            |                                                  ipbus_transport_multibuffer_rx_dpram_3177 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    8(0.16%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           tx_ram                                                                            |                                                  ipbus_transport_multibuffer_tx_dpram_3178 |     47(0.01%) |     47(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    8(0.16%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       versal_decl_test.axi_bram_ctrl_versal                                                 |                                                                 axi_bram_ctrl_versal_0_HD3 |    329(0.01%) |    329(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                   axi_bram_ctrl_versal_0_axi_bram_ctrl_HD4 |    329(0.01%) |    329(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gext_inst.abcv4_0_ext_inst                                                        |                                               axi_bram_ctrl_versal_0_axi_bram_ctrl_top_HD5 |    329(0.01%) |    329(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             GEN_AXI4.I_FULL_AXI                                                             |                                                        axi_bram_ctrl_versal_0_full_axi_HD6 |    329(0.01%) |    329(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_RD_CHNL                                                                     |                                                         axi_bram_ctrl_versal_0_rd_chnl_HD7 |    200(0.01%) |    200(0.01%) | 0(0.00%) |    0(0.00%) |    240(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_RD_CHNL)                                                                 |                                                         axi_bram_ctrl_versal_0_rd_chnl_HD7 |    155(0.01%) |    155(0.01%) | 0(0.00%) |    0(0.00%) |    225(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 GEN_NO_RD_CMD_OPT.I_WRAP_BRST                                               |                                                     axi_bram_ctrl_versal_0_wrap_brst_0_HD8 |     47(0.01%) |     47(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_WR_CHNL                                                                     |                                                         axi_bram_ctrl_versal_0_wr_chnl_HD9 |    129(0.01%) |    129(0.01%) | 0(0.00%) |    0(0.00%) |    155(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_WR_CHNL)                                                                 |                                                         axi_bram_ctrl_versal_0_wr_chnl_HD9 |     87(0.01%) |     87(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 BID_FIFO                                                                    |                                                       axi_bram_ctrl_versal_0_SRL_FIFO_HD10 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 I_WRAP_BRST                                                                 |                                                      axi_bram_ctrl_versal_0_wrap_brst_HD11 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ipb_axi_inst_IN_SLR2                                                                    |                                                          ipbus_transport_axi_if__xdcDup__3 |    464(0.01%) |    464(0.01%) | 0(0.00%) |    0(0.00%) |    515(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (ipb_axi_inst_IN_SLR2)                                                                |                                                          ipbus_transport_axi_if__xdcDup__3 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       ram_to_trans                                                                          |                                                                ipbus_transport_ram_if_3169 |    134(0.01%) |    134(0.01%) | 0(0.00%) |    0(0.00%) |    120(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (ram_to_trans)                                                                      |                                                                ipbus_transport_ram_if_3169 |     42(0.01%) |     42(0.01%) | 0(0.00%) |    0(0.00%) |     79(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         multibuffer_if                                                                      |                                                        ipbus_transport_multibuffer_if_3170 |     92(0.01%) |     92(0.01%) | 0(0.00%) |    0(0.00%) |     41(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (multibuffer_if)                                                                  |                                                        ipbus_transport_multibuffer_if_3170 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     23(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cdc                                                                               |                                                       ipbus_transport_multibuffer_cdc_3171 |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rx_ram                                                                            |                                                  ipbus_transport_multibuffer_rx_dpram_3172 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    8(0.16%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           tx_ram                                                                            |                                                  ipbus_transport_multibuffer_tx_dpram_3173 |     47(0.01%) |     47(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    8(0.16%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       versal_decl_test.axi_bram_ctrl_versal                                                 |                                                                axi_bram_ctrl_versal_0_HD12 |    327(0.01%) |    327(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                  axi_bram_ctrl_versal_0_axi_bram_ctrl_HD13 |    327(0.01%) |    327(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gext_inst.abcv4_0_ext_inst                                                        |                                              axi_bram_ctrl_versal_0_axi_bram_ctrl_top_HD14 |    327(0.01%) |    327(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             GEN_AXI4.I_FULL_AXI                                                             |                                                       axi_bram_ctrl_versal_0_full_axi_HD15 |    327(0.01%) |    327(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_RD_CHNL                                                                     |                                                        axi_bram_ctrl_versal_0_rd_chnl_HD16 |    198(0.01%) |    198(0.01%) | 0(0.00%) |    0(0.00%) |    240(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_RD_CHNL)                                                                 |                                                        axi_bram_ctrl_versal_0_rd_chnl_HD16 |    155(0.01%) |    155(0.01%) | 0(0.00%) |    0(0.00%) |    225(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 GEN_NO_RD_CMD_OPT.I_WRAP_BRST                                               |                                                    axi_bram_ctrl_versal_0_wrap_brst_0_HD17 |     46(0.01%) |     46(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_WR_CHNL                                                                     |                                                        axi_bram_ctrl_versal_0_wr_chnl_HD18 |    129(0.01%) |    129(0.01%) | 0(0.00%) |    0(0.00%) |    155(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_WR_CHNL)                                                                 |                                                        axi_bram_ctrl_versal_0_wr_chnl_HD18 |     87(0.01%) |     87(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 BID_FIFO                                                                    |                                                       axi_bram_ctrl_versal_0_SRL_FIFO_HD19 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 I_WRAP_BRST                                                                 |                                                      axi_bram_ctrl_versal_0_wrap_brst_HD20 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ipb_axi_inst_IN_SLR3                                                                    |                                                                     ipbus_transport_axi_if |    467(0.01%) |    467(0.01%) | 0(0.00%) |    0(0.00%) |    515(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (ipb_axi_inst_IN_SLR3)                                                                |                                                                     ipbus_transport_axi_if |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       ram_to_trans                                                                          |                                                                     ipbus_transport_ram_if |    134(0.01%) |    134(0.01%) | 0(0.00%) |    0(0.00%) |    120(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (ram_to_trans)                                                                      |                                                                     ipbus_transport_ram_if |     42(0.01%) |     42(0.01%) | 0(0.00%) |    0(0.00%) |     79(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         multibuffer_if                                                                      |                                                             ipbus_transport_multibuffer_if |     92(0.01%) |     92(0.01%) | 0(0.00%) |    0(0.00%) |     41(0.01%) |   16(0.32%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (multibuffer_if)                                                                  |                                                             ipbus_transport_multibuffer_if |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     23(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cdc                                                                               |                                                            ipbus_transport_multibuffer_cdc |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rx_ram                                                                            |                                                       ipbus_transport_multibuffer_rx_dpram |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    8(0.16%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           tx_ram                                                                            |                                                       ipbus_transport_multibuffer_tx_dpram |     47(0.01%) |     47(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    8(0.16%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       versal_decl_test.axi_bram_ctrl_versal                                                 |                                                                     axi_bram_ctrl_versal_0 |    330(0.01%) |    330(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (versal_decl_test.axi_bram_ctrl_versal)                                             |                                                                     axi_bram_ctrl_versal_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                       axi_bram_ctrl_versal_0_axi_bram_ctrl |    330(0.01%) |    330(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gext_inst.abcv4_0_ext_inst                                                        |                                                   axi_bram_ctrl_versal_0_axi_bram_ctrl_top |    330(0.01%) |    330(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             GEN_AXI4.I_FULL_AXI                                                             |                                                            axi_bram_ctrl_versal_0_full_axi |    330(0.01%) |    330(0.01%) | 0(0.00%) |    0(0.00%) |    395(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_RD_CHNL                                                                     |                                                             axi_bram_ctrl_versal_0_rd_chnl |    201(0.01%) |    201(0.01%) | 0(0.00%) |    0(0.00%) |    240(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_RD_CHNL)                                                                 |                                                             axi_bram_ctrl_versal_0_rd_chnl |    155(0.01%) |    155(0.01%) | 0(0.00%) |    0(0.00%) |    225(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 GEN_NO_RD_CMD_OPT.I_WRAP_BRST                                               |                                                         axi_bram_ctrl_versal_0_wrap_brst_0 |     46(0.01%) |     46(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_WR_CHNL                                                                     |                                                             axi_bram_ctrl_versal_0_wr_chnl |    129(0.01%) |    129(0.01%) | 0(0.00%) |    0(0.00%) |    155(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_WR_CHNL)                                                                 |                                                             axi_bram_ctrl_versal_0_wr_chnl |     87(0.01%) |     87(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 BID_FIFO                                                                    |                                                            axi_bram_ctrl_versal_0_SRL_FIFO |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 I_WRAP_BRST                                                                 |                                                           axi_bram_ctrl_versal_0_wrap_brst |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ipb_trans_inst_IN_SLR0                                                                  |                                                                                 transactor |   1066(0.03%) |   1066(0.03%) | 0(0.00%) |    0(0.00%) |    429(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       iface                                                                                 |                                                                         transactor_if_3167 |    222(0.01%) |    222(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sm                                                                                    |                                                                         transactor_sm_3168 |    845(0.03%) |    845(0.03%) | 0(0.00%) |    0(0.00%) |    288(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ipb_trans_inst_IN_SLR1                                                                  |                                                                            transactor_3160 |   1217(0.04%) |   1217(0.04%) | 0(0.00%) |    0(0.00%) |    429(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       iface                                                                                 |                                                                         transactor_if_3165 |    222(0.01%) |    222(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sm                                                                                    |                                                                         transactor_sm_3166 |    997(0.03%) |    997(0.03%) | 0(0.00%) |    0(0.00%) |    288(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ipb_trans_inst_IN_SLR2                                                                  |                                                                            transactor_3161 |    875(0.03%) |    875(0.03%) | 0(0.00%) |    0(0.00%) |    386(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       iface                                                                                 |                                                                         transactor_if_3163 |    223(0.01%) |    223(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sm                                                                                    |                                                                         transactor_sm_3164 |    653(0.02%) |    653(0.02%) | 0(0.00%) |    0(0.00%) |    245(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ipb_trans_inst_IN_SLR3                                                                  |                                                                            transactor_3162 |   3089(0.09%) |   3089(0.09%) | 0(0.00%) |    0(0.00%) |    415(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       iface                                                                                 |                                                                              transactor_if |    223(0.01%) |    223(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sm                                                                                    |                                                                              transactor_sm |   2867(0.09%) |   2867(0.09%) | 0(0.00%) |    0(0.00%) |    274(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|   U_payload                                                                                 |                                                                                    payload | 105566(3.14%) | 105566(3.14%) | 0(0.00%) |    0(0.00%) | 243165(3.62%) | 627(12.69%) | 11(0.11%) | 0(0.00%) |   0(0.00%) |
|     (U_payload)                                                                             |                                                                                    payload |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     80(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ANTIKT_CONEJET1_APP_IN_SLR1                                                             |                                                                        app__parameterized7 |   1825(0.05%) |   1825(0.05%) | 0(0.00%) |    0(0.00%) |   4590(0.07%) |   16(0.32%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       (ANTIKT_CONEJET1_APP_IN_SLR1)                                                         |                                                                        app__parameterized7 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                   pipeline__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    264(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                     logger__parameterized5 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |    145(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                     logger__parameterized5 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     80(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                     ipbus_ram_wrapper_3150 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                     ipbus_ram_wrapper_3150 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_3156 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                     ipbus_ram_wrapper_3151 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                     ipbus_ram_wrapper_3151 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_3155 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                     ipbus_ram_wrapper__parameterized0_3152 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                     ipbus_ram_wrapper__parameterized0_3152 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized3_3154 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized2_3153 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                       ipbus_ctrlreg_v__parameterized1_3077 |   1119(0.03%) |   1119(0.03%) | 0(0.00%) |    0(0.00%) |   2053(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__72 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    432(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_3078 |    236(0.01%) |    236(0.01%) | 0(0.00%) |    0(0.00%) |    309(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_3078 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_3121 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     45(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_3121 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_3144 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_3145 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_3146 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_3147 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_3148 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_3149 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_3122 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     45(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_3122 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_3138 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_3139 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_3140 |     41(0.01%) |     41(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_3141 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_3142 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_3143 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_3123 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     45(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_3123 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_3132 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_3133 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_3134 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_3135 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_3136 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_3137 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_3124 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     45(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_3124 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_3126 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_3127 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_3128 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_3129 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_3130 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_3131 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_3125 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                        sync_bcid_rxtx_3079 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                 mux41__parameterized2_3116 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                             reg_array__parameterized0_3117 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                             reg_array__parameterized0_3118 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                             reg_array__parameterized0_3119 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                             reg_array__parameterized0_3120 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                             sync_sr2g_3080 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__73 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    792(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized2_3081 |    288(0.01%) |    288(0.01%) | 0(0.00%) |    0(0.00%) |    468(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized2_3081 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    257(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_3087 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_3087 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3110 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3111 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3112 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3113 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3114 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3115 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_3088 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_3088 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3104 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3105 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3106 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3107 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3108 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3109 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_3089 |     62(0.01%) |     62(0.01%) | 0(0.00%) |    0(0.00%) |     51(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_3089 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3098 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3099 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3100 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3101 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3102 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3103 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_3090 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_3090 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3092 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3093 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3094 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3095 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3096 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3097 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized0_3091 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                             sync_sr2g_3082 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                             pulse_cdc_3084 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                             pulse_cdc_3084 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_3086 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                           sync_fsm_v4_3085 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     ANTIKT_CONEJET1_APU_IN_SLR1                                                             |                                                       dummy_apu_with_ipbus__parameterized4 |    250(0.01%) |    250(0.01%) | 0(0.00%) |    0(0.00%) |    336(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (ANTIKT_CONEJET1_APU_IN_SLR1)                                                         |                                                       dummy_apu_with_ipbus__parameterized4 |     84(0.01%) |     84(0.01%) | 0(0.00%) |    0(0.00%) |    176(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                       ipbus_ctrlreg_v__parameterized3_3076 |    167(0.01%) |    167(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     CLUSTER_MET_APP_IN_SLR1                                                                 |                                                                        app__parameterized8 |   1477(0.04%) |   1477(0.04%) | 0(0.00%) |    0(0.00%) |   3824(0.06%) |   12(0.24%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       (CLUSTER_MET_APP_IN_SLR1)                                                             |                                                                        app__parameterized8 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     41(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__186 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                logger__parameterized6_3026 |    126(0.01%) |    126(0.01%) | 0(0.00%) |    0(0.00%) |    140(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                logger__parameterized6_3026 |     66(0.01%) |     66(0.01%) | 0(0.00%) |    0(0.00%) |     75(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                     ipbus_ram_wrapper_3069 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                     ipbus_ram_wrapper_3069 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_3075 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                     ipbus_ram_wrapper_3070 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                     ipbus_ram_wrapper_3070 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_3074 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                     ipbus_ram_wrapper__parameterized0_3071 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                     ipbus_ram_wrapper__parameterized0_3071 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized3_3073 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized2_3072 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                       ipbus_ctrlreg_v__parameterized1_3027 |   1054(0.03%) |   1054(0.03%) | 0(0.00%) |    0(0.00%) |   2050(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                              pipeline__187 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    828(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized2_3028 |    259(0.01%) |    259(0.01%) | 0(0.00%) |    0(0.00%) |    474(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized2_3028 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    257(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_3040 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_3040 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3063 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3064 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3065 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3066 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3067 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3068 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_3041 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_3041 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3057 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3058 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3059 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3060 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3061 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3062 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_3042 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     51(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_3042 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3051 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3052 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3053 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3054 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3055 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3056 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_3043 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_3043 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3045 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3046 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3047 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3048 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3049 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3050 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized0_3044 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                        sync_bcid_rxtx_3029 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                 mux41__parameterized2_3035 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                             reg_array__parameterized0_3036 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                             reg_array__parameterized0_3037 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                             reg_array__parameterized0_3038 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                             reg_array__parameterized0_3039 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                             sync_sr2g_3030 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                             pulse_cdc_3032 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                             pulse_cdc_3032 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_3034 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                           sync_fsm_v4_3033 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     CLUSTER_MET_APU_IN_SLR1                                                                 |                                                       dummy_apu_with_ipbus__parameterized8 |    236(0.01%) |    236(0.01%) | 0(0.00%) |    0(0.00%) |    337(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (CLUSTER_MET_APU_IN_SLR1)                                                             |                                                       dummy_apu_with_ipbus__parameterized8 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |    177(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                       ipbus_ctrlreg_v__parameterized3_3025 |    164(0.01%) |    164(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     CONE_JET2_APP_IN_SLR1                                                                   |                                                                      app__parameterized8_0 |   1481(0.04%) |   1481(0.04%) | 0(0.00%) |    0(0.00%) |   3824(0.06%) |   12(0.24%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       (CONE_JET2_APP_IN_SLR1)                                                               |                                                                      app__parameterized8_0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     41(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__184 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                logger__parameterized6_2975 |    127(0.01%) |    127(0.01%) | 0(0.00%) |    0(0.00%) |    140(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                logger__parameterized6_2975 |     66(0.01%) |     66(0.01%) | 0(0.00%) |    0(0.00%) |     75(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                     ipbus_ram_wrapper_3018 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                     ipbus_ram_wrapper_3018 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_3024 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                     ipbus_ram_wrapper_3019 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                     ipbus_ram_wrapper_3019 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_3023 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                     ipbus_ram_wrapper__parameterized0_3020 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                     ipbus_ram_wrapper__parameterized0_3020 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized3_3022 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized2_3021 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                       ipbus_ctrlreg_v__parameterized1_2976 |   1056(0.03%) |   1056(0.03%) | 0(0.00%) |    0(0.00%) |   2050(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                              pipeline__185 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    828(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized2_2977 |    259(0.01%) |    259(0.01%) | 0(0.00%) |    0(0.00%) |    474(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized2_2977 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    257(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_2989 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_2989 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3012 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3013 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3014 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3015 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3016 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3017 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_2990 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_2990 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3006 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3007 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3008 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3009 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3010 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3011 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_2991 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     51(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_2991 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_3000 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_3001 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_3002 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_3003 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_3004 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_3005 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_2992 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_2992 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2994 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2995 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2996 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2997 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2998 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2999 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized0_2993 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                        sync_bcid_rxtx_2978 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                 mux41__parameterized2_2984 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                             reg_array__parameterized0_2985 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                             reg_array__parameterized0_2986 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                             reg_array__parameterized0_2987 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                             reg_array__parameterized0_2988 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2979 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                             pulse_cdc_2981 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                             pulse_cdc_2981 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_2983 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                           sync_fsm_v4_2982 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     CONE_JET2_APU_IN_SLR1                                                                   |                                                     dummy_apu_with_ipbus__parameterized8_1 |    236(0.01%) |    236(0.01%) | 0(0.00%) |    0(0.00%) |    337(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (CONE_JET2_APU_IN_SLR1)                                                               |                                                     dummy_apu_with_ipbus__parameterized8_1 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |    177(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                       ipbus_ctrlreg_v__parameterized3_2974 |    164(0.01%) |    164(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     EGAMMA1_APP_IN_SLR3                                                                     |                                                                        app__parameterized5 |   2551(0.08%) |   2551(0.08%) | 0(0.00%) |    0(0.00%) |   5532(0.08%) |   24(0.49%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       (EGAMMA1_APP_IN_SLR3)                                                                 |                                                                        app__parameterized5 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__68 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    252(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                logger__parameterized3_2831 |    124(0.01%) |    124(0.01%) | 0(0.00%) |    0(0.00%) |    143(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                logger__parameterized3_2831 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     78(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                     ipbus_ram_wrapper_2967 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                     ipbus_ram_wrapper_2967 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_2973 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                     ipbus_ram_wrapper_2968 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                     ipbus_ram_wrapper_2968 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_2972 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                     ipbus_ram_wrapper__parameterized0_2969 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                     ipbus_ram_wrapper__parameterized0_2969 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized3_2971 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized2_2970 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                       ipbus_ctrlreg_v__parameterized1_2832 |   1273(0.04%) |   1273(0.04%) | 0(0.00%) |    0(0.00%) |   2058(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__64 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized2_2833 |    291(0.01%) |    291(0.01%) | 0(0.00%) |    0(0.00%) |    337(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized2_2833 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_2938 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_2938 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2961 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2962 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2963 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2964 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2965 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2966 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_2939 |     80(0.01%) |     80(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_2939 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2955 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2956 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2957 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2958 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2959 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2960 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_2940 |     68(0.01%) |     68(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_2940 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2949 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2950 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2951 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2952 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2953 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2954 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_2941 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_2941 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2943 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2944 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2945 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2946 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2947 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2948 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized0_2942 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                        sync_bcid_rxtx_2834 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                 mux41__parameterized2_2933 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                             reg_array__parameterized0_2934 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                             reg_array__parameterized0_2935 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                             reg_array__parameterized0_2936 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                             reg_array__parameterized0_2937 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2835 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__65 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2836 |    247(0.01%) |    247(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2836 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2904 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2904 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2927 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2928 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2929 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2930 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2931 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2932 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2905 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2905 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2921 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2922 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2923 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2924 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2925 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2926 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2906 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2906 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2915 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2916 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2917 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2918 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2919 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2920 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2907 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2907 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2909 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2910 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2911 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2912 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2913 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2914 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2908 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2837 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__66 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2838 |    272(0.01%) |    272(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2838 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2875 |     59(0.01%) |     59(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2875 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2898 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2899 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2900 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2901 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2902 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2903 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2876 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2876 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2892 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2893 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2894 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2895 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2896 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2897 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2877 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2877 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2886 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2887 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2888 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2889 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2890 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2891 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2878 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2878 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2880 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2881 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2882 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2883 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2884 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2885 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2879 |     24(0.01%) |     24(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2839 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__67 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2840 |    288(0.01%) |    288(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2840 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2846 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2846 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2869 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2870 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2871 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2872 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2873 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2874 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2847 |     76(0.01%) |     76(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2847 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2863 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2864 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2865 |     41(0.01%) |     41(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2866 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2867 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2868 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2848 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2848 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2857 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2858 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2859 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2860 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2861 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2862 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2849 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2849 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2851 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2852 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2853 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2854 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2855 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2856 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2850 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2841 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                             pulse_cdc_2843 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                             pulse_cdc_2843 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_2845 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                           sync_fsm_v4_2844 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     EGAMMA1_APU_IN_SLR3                                                                     |                                                       dummy_apu_with_ipbus__parameterized3 |    261(0.01%) |    261(0.01%) | 0(0.00%) |    0(0.00%) |    340(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (EGAMMA1_APU_IN_SLR3)                                                                 |                                                       dummy_apu_with_ipbus__parameterized3 |     90(0.01%) |     90(0.01%) | 0(0.00%) |    0(0.00%) |    180(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                       ipbus_ctrlreg_v__parameterized3_2830 |    171(0.01%) |    171(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     EGAMMA2_APP_IN_SLR2                                                                     |                                                                        app__parameterized6 |   1699(0.05%) |   1699(0.05%) | 0(0.00%) |    0(0.00%) |   4248(0.06%) |   14(0.28%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       (EGAMMA2_APP_IN_SLR2)                                                                 |                                                                        app__parameterized6 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     44(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__71 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                logger__parameterized4_2749 |    124(0.01%) |    124(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                logger__parameterized4_2749 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                     ipbus_ram_wrapper_2823 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                     ipbus_ram_wrapper_2823 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_2829 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                     ipbus_ram_wrapper_2824 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                     ipbus_ram_wrapper_2824 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_2828 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                     ipbus_ram_wrapper__parameterized0_2825 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                     ipbus_ram_wrapper__parameterized0_2825 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized3_2827 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized2_2826 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                       ipbus_ctrlreg_v__parameterized1_2750 |   1106(0.03%) |   1106(0.03%) | 0(0.00%) |    0(0.00%) |   2053(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__69 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    252(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized6_2751 |    134(0.01%) |    134(0.01%) | 0(0.00%) |    0(0.00%) |    197(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized6_2751 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2794 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2794 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2817 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2818 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2819 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2820 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2821 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2822 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2795 |     45(0.01%) |     45(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2795 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2811 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2812 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2813 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2814 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2815 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2816 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2796 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2796 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2805 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2806 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2807 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2808 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2809 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2810 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2797 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2797 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2799 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2800 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2801 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2802 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2803 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2804 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized2_2798 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                        sync_bcid_rxtx_2752 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                 mux41__parameterized2_2789 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                             reg_array__parameterized0_2790 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                             reg_array__parameterized0_2791 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                             reg_array__parameterized0_2792 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                             reg_array__parameterized0_2793 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2753 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__70 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    792(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized2_2754 |    289(0.01%) |    289(0.01%) | 0(0.00%) |    0(0.00%) |    474(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized2_2754 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    257(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_2760 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_2760 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2783 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2784 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2785 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2786 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2787 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2788 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_2761 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_2761 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2777 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2778 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2779 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2780 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2781 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2782 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_2762 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     51(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_2762 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2771 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2772 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2773 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2774 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2775 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2776 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_2763 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_2763 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2765 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2766 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2767 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2768 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2769 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2770 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized0_2764 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2755 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                             pulse_cdc_2757 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                             pulse_cdc_2757 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_2759 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                           sync_fsm_v4_2758 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     EGAMMA2_APU_IN_SLR2                                                                     |                                                     dummy_apu_with_ipbus__parameterized4_2 |    242(0.01%) |    242(0.01%) | 0(0.00%) |    0(0.00%) |    330(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (EGAMMA2_APU_IN_SLR2)                                                                 |                                                     dummy_apu_with_ipbus__parameterized4_2 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |    170(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                       ipbus_ctrlreg_v__parameterized3_2748 |    167(0.01%) |    167(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     HYPOTHESIS_APP_IN_SLR0                                                                  |                                                                       app__parameterized13 |   8379(0.25%) |   8379(0.25%) | 0(0.00%) |    0(0.00%) |  16665(0.25%) |   79(1.60%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (HYPOTHESIS_APP_IN_SLR0)                                                              |                                                                       app__parameterized13 |     48(0.01%) |     48(0.01%) | 0(0.00%) |    0(0.00%) |     99(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__97 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                     logger__parameterized7 |    130(0.01%) |    130(0.01%) | 0(0.00%) |    0(0.00%) |    161(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                     logger__parameterized7 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     96(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                     ipbus_ram_wrapper_2741 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                     ipbus_ram_wrapper_2741 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_2747 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                     ipbus_ram_wrapper_2742 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                     ipbus_ram_wrapper_2742 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_2746 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                     ipbus_ram_wrapper__parameterized0_2743 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                     ipbus_ram_wrapper__parameterized0_2743 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized3_2745 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized2_2744 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                       ipbus_ctrlreg_v__parameterized1_2049 |   3202(0.10%) |   3202(0.10%) | 0(0.00%) |    0(0.00%) |   2102(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__96 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    456(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2050 |    190(0.01%) |    190(0.01%) | 0(0.00%) |    0(0.00%) |    297(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2050 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2712 |     42(0.01%) |     42(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2712 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2735 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2736 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2737 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2738 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2739 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2740 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2713 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2713 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2729 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2730 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2731 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2732 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2733 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2734 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2714 |     44(0.01%) |     44(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2714 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2723 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2724 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2725 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2726 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2727 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2728 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2715 |     43(0.01%) |     43(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2715 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2717 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2718 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2719 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2720 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2721 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2722 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2716 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                        sync_bcid_rxtx_2051 |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                 mux41__parameterized2_2707 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                             reg_array__parameterized0_2708 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                             reg_array__parameterized0_2709 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                             reg_array__parameterized0_2710 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                             reg_array__parameterized0_2711 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         dmux_wr_en                                                                          |                                                                                     dmux14 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2052 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[10].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__84 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    414(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[10].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized4_2053 |    229(0.01%) |    229(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[10].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized4_2053 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2678 |     52(0.01%) |     52(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2678 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2701 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2702 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2703 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2704 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2705 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2706 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2679 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2679 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2695 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2696 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2697 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2698 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2699 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2700 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2680 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2680 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2689 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2690 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2691 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2692 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2693 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2694 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2681 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2681 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2683 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2684 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2685 |     29(0.01%) |     29(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2686 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2687 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2688 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2682 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[10].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2054 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[11].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__83 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[11].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized4_2055 |    352(0.01%) |    352(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[11].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized4_2055 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2649 |     52(0.01%) |     52(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2649 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2672 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2673 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2674 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2675 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2676 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2677 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2650 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2650 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2666 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2667 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2668 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2669 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2670 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2671 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2651 |     51(0.01%) |     51(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2651 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2660 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2661 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2662 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2663 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2664 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2665 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2652 |     51(0.01%) |     51(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2652 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2654 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2655 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2656 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2657 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2658 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2659 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2653 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[11].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2056 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[12].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__82 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    414(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[12].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized4_2057 |    231(0.01%) |    231(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[12].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized4_2057 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2620 |     51(0.01%) |     51(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2620 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2643 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2644 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2645 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2646 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2647 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2648 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2621 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2621 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2637 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2638 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2639 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2640 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2641 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2642 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2622 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2622 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2631 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2632 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2633 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2634 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2635 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2636 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2623 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2623 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2625 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2626 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2627 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2628 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2629 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2630 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2624 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[12].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2058 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[13].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__81 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    410(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[13].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized4_2059 |    235(0.01%) |    235(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[13].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized4_2059 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2591 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2591 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2614 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2615 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2616 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2617 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2618 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2619 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2592 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2592 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2608 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2609 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2610 |     39(0.01%) |     39(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2611 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2612 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2613 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2593 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2593 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2602 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2603 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2604 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2605 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2606 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2607 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2594 |     55(0.01%) |     55(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2594 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2596 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2597 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2598 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2599 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2600 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2601 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2595 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[13].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2060 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[14].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__93 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    414(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[14].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized4_2061 |    321(0.01%) |    321(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[14].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized4_2061 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2562 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2562 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2585 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2586 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2587 |     29(0.01%) |     29(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2588 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2589 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2590 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2563 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2563 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2579 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2580 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2581 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2582 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2583 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2584 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2564 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2564 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2573 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2574 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2575 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2576 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2577 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2578 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2565 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2565 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2567 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2568 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2569 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2570 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2571 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2572 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2566 |     89(0.01%) |     89(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[14].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2062 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[15].FREE_FROM_SLR_input_pipeline                                              |                                                                              pipeline__103 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[15].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized6_2063 |    233(0.01%) |    233(0.01%) | 0(0.00%) |    0(0.00%) |    189(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[15].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized6_2063 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2533 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2533 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2556 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2557 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2558 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2559 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2560 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2561 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2534 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2534 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2550 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2551 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2552 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2553 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2554 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2555 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2535 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2535 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2544 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2545 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2546 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2547 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2548 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2549 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2536 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2536 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2538 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2539 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2540 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2541 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2542 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2543 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized2_2537 |    127(0.01%) |    127(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[15].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2064 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[16].FREE_FROM_SLR_input_pipeline                                              |                                                                              pipeline__102 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[16].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized6_2065 |    100(0.01%) |    100(0.01%) | 0(0.00%) |    0(0.00%) |    189(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[16].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized6_2065 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2504 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2504 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2527 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2528 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2529 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2530 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2531 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2532 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2505 |     35(0.01%) |     35(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2505 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2521 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2522 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2523 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2524 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2525 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2526 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2506 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2506 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2515 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2516 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2517 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2518 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2519 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2520 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2507 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2507 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2509 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2510 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2511 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2512 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2513 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2514 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized2_2508 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[16].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2066 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[17].FREE_FROM_SLR_input_pipeline                                              |                                                                              pipeline__101 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[17].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized6_2067 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |    189(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[17].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized6_2067 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2475 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2475 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2498 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2499 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2500 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2501 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2502 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2503 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2476 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2476 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2492 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2493 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2494 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2495 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2496 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2497 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2477 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2477 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2486 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2487 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2488 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2489 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2490 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2491 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2478 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2478 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2480 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2481 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2482 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2483 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2484 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2485 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized2_2479 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[17].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2068 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[18].FREE_FROM_SLR_input_pipeline                                              |                                                                              pipeline__100 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[18].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized6_2069 |    101(0.01%) |    101(0.01%) | 0(0.00%) |    0(0.00%) |    189(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[18].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized6_2069 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2446 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2446 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2469 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2470 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2471 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2472 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2473 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2474 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2447 |     35(0.01%) |     35(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2447 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2463 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2464 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2465 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2466 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2467 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2468 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2448 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2448 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2457 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2458 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2459 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2460 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2461 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2462 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2449 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2449 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2451 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2452 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2453 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2454 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2455 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2456 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized2_2450 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[18].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2070 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[19].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__99 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[19].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized6_2071 |    166(0.01%) |    166(0.01%) | 0(0.00%) |    0(0.00%) |    189(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[19].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized6_2071 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2417 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2417 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2440 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2441 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2442 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2443 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2444 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2445 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2418 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2418 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2434 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2435 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2436 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2437 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2438 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2439 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2419 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2419 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2428 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2429 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2430 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2431 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2432 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2433 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2420 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2420 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2422 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2423 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2424 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2425 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2426 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2427 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized2_2421 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[19].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2072 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__95 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2073 |    188(0.01%) |    188(0.01%) | 0(0.00%) |    0(0.00%) |    297(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2073 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2388 |     43(0.01%) |     43(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2388 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2411 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2412 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2413 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2414 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2415 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2416 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2389 |     59(0.01%) |     59(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2389 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2405 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2406 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2407 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2408 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2409 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2410 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2390 |     44(0.01%) |     44(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2390 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2399 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2400 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2401 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2402 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2403 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2404 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2391 |     42(0.01%) |     42(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2391 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2393 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2394 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2395 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2396 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2397 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2398 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2392 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2074 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[20].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__98 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[20].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized6_2075 |    170(0.01%) |    170(0.01%) | 0(0.00%) |    0(0.00%) |    189(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[20].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized6_2075 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2359 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2359 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2382 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2383 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2384 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2385 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2386 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2387 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2360 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2360 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2376 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2377 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2378 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2379 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2380 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2381 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2361 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2361 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2370 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2371 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2372 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2373 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2374 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2375 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2362 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2362 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2364 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2365 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2366 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2367 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2368 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2369 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized2_2363 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[20].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2076 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[21].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__94 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[21].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                       sync_mt_fifo_v2__parameterized6_2077 |    132(0.01%) |    132(0.01%) | 0(0.00%) |    0(0.00%) |    197(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[21].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                       sync_mt_fifo_v2__parameterized6_2077 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2330 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2330 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2353 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2354 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2355 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2356 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2357 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2358 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2331 |     43(0.01%) |     43(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2331 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2347 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2348 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2349 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2350 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2351 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2352 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2332 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2332 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2341 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2342 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2343 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2344 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2345 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2346 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2333 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2333 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2335 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2336 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2337 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2338 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2339 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2340 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized2_2334 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[21].sync_if.sync_sr                                                           |                                                                             sync_sr2g_2078 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__92 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    416(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2079 |    189(0.01%) |    189(0.01%) | 0(0.00%) |    0(0.00%) |    297(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2079 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2301 |     43(0.01%) |     43(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2301 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2324 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2325 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2326 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2327 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2328 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2329 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2302 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2302 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2318 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2319 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2320 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2321 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2322 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2323 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2303 |     42(0.01%) |     42(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2303 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2312 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2313 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2314 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2315 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2316 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2317 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2304 |     43(0.01%) |     43(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2304 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2306 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2307 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2308 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2309 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2310 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2311 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2305 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2080 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__91 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2081 |    317(0.01%) |    317(0.01%) | 0(0.00%) |    0(0.00%) |    297(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2081 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2272 |     43(0.01%) |     43(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2272 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2295 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2296 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2297 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2298 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2299 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2300 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2273 |     62(0.01%) |     62(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2273 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2289 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2290 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2291 |     29(0.01%) |     29(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2292 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2293 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2294 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2274 |     42(0.01%) |     42(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2274 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2283 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2284 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2285 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2286 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2287 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2288 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2275 |     42(0.01%) |     42(0.01%) | 0(0.00%) |    0(0.00%) |     42(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2275 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2277 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2278 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2279 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2280 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2281 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2282 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2276 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2082 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[4].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__89 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[4].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2083 |    244(0.01%) |    244(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[4].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2083 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2243 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2243 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2266 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2267 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2268 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2269 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2270 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2271 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2244 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2244 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2260 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2261 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2262 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2263 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2264 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2265 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2245 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2245 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2254 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2255 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2256 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2257 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2258 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2259 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2246 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2246 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2248 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2249 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2250 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2251 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2252 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2253 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2247 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[4].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2084 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[5].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__87 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[5].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2085 |    246(0.01%) |    246(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[5].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2085 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2214 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2214 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2237 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2238 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2239 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2240 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2241 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2242 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2215 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2215 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2231 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2232 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2233 |     39(0.01%) |     39(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2234 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2235 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2236 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2216 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2216 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2225 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2226 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2227 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2228 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2229 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2230 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2217 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2217 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2219 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2220 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2221 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2222 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2223 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2224 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2218 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[5].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2086 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[6].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__85 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[6].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_2087 |    273(0.01%) |    273(0.01%) | 0(0.00%) |    0(0.00%) |    331(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[6].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_2087 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_2185 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_2185 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2208 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2209 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2210 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2211 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2212 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2213 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_2186 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     47(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_2186 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2202 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2203 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2204 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2205 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2206 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2207 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_2187 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_2187 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2196 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2197 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2198 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2199 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2200 |     35(0.01%) |     35(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2201 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_2188 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_2188 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_2190 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_2191 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_2192 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_2193 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_2194 |     29(0.01%) |     29(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_2195 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_2189 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[6].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2088 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[7].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__90 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[7].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2089 |    374(0.01%) |    374(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[7].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2089 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2156 |     56(0.01%) |     56(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2156 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2179 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2180 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2181 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2182 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2183 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2184 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2157 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2157 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2173 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2174 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2175 |     39(0.01%) |     39(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2176 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2177 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2178 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2158 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2158 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2167 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2168 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2169 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2170 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2171 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2172 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2159 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2159 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2161 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2162 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2163 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2164 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2165 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2166 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2160 |    129(0.01%) |    129(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[7].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2090 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[8].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__88 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[8].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2091 |    243(0.01%) |    243(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[8].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2091 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2127 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2127 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2150 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2151 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2152 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2153 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2154 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2155 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2128 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2128 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2144 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2145 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2146 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2147 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2148 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2149 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2129 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2129 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2138 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2139 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2140 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2141 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2142 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2143 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2130 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2130 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2132 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2133 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2134 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2135 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2136 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2137 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2131 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[8].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2092 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[9].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__86 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[9].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized4_2093 |    246(0.01%) |    246(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[9].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized4_2093 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2098 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2098 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2121 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2122 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2123 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2124 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2125 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2126 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2099 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2099 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2115 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2116 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2117 |     39(0.01%) |     39(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2118 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2119 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2120 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2100 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2100 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2109 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2110 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2111 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2112 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2113 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2114 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized0_2101 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized0_2101 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized1_2103 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized1_2104 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2105 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized0_2106 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized0_2107 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                            perf_count_2108 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized1_2102 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[9].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2094 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                             pulse_cdc_2095 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                             pulse_cdc_2095 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_2097 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                           sync_fsm_v4_2096 |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     HYPOTHESIS_APU_IN_SLR0                                                                  |                                                      dummy_apu_with_ipbus__parameterized13 |    376(0.01%) |    376(0.01%) | 0(0.00%) |    0(0.00%) |    478(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (HYPOTHESIS_APU_IN_SLR0)                                                              |                                                      dummy_apu_with_ipbus__parameterized13 |     76(0.01%) |     76(0.01%) | 0(0.00%) |    0(0.00%) |    309(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                       ipbus_ctrlreg_v__parameterized3_2048 |    300(0.01%) |    300(0.01%) | 0(0.00%) |    0(0.00%) |    169(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     JET_TAG_APP_IN_SLR1                                                                     |                                                                        app__parameterized9 |   1436(0.04%) |   1436(0.04%) | 0(0.00%) |    0(0.00%) |   2974(0.04%) |    7(0.14%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (JET_TAG_APP_IN_SLR1)                                                                 |                                                                        app__parameterized9 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     41(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__77 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                logger__parameterized6_1999 |    136(0.01%) |    136(0.01%) | 0(0.00%) |    0(0.00%) |    140(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                logger__parameterized6_1999 |     68(0.01%) |     68(0.01%) | 0(0.00%) |    0(0.00%) |     75(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                     ipbus_ram_wrapper_2041 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                     ipbus_ram_wrapper_2041 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_2047 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                     ipbus_ram_wrapper_2042 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                     ipbus_ram_wrapper_2042 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_2046 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                     ipbus_ram_wrapper__parameterized0_2043 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                     ipbus_ram_wrapper__parameterized0_2043 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized3_2045 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized2_2044 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                       ipbus_ctrlreg_v__parameterized1_2000 |   1094(0.03%) |   1094(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__76 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    252(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                       sync_mt_fifo_v2__parameterized6_2001 |    163(0.01%) |    163(0.01%) | 0(0.00%) |    0(0.00%) |    202(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                       sync_mt_fifo_v2__parameterized6_2001 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2012 |     46(0.01%) |     46(0.01%) | 0(0.00%) |    0(0.00%) |     35(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2012 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2035 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2036 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2037 |     24(0.01%) |     24(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2038 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2039 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2040 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2013 |     41(0.01%) |     41(0.01%) | 0(0.00%) |    0(0.00%) |     34(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2013 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2029 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2030 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2031 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2032 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2033 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2034 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2014 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     34(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2014 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2023 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2024 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2025 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2026 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2027 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2028 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                    sync_fifo_cntrl_v2__parameterized1_2015 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     34(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                    sync_fifo_cntrl_v2__parameterized1_2015 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                             reg_array__parameterized2_2017 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                             reg_array__parameterized2_2018 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2019 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                              sync_rd_side_roll_detect__parameterized1_2020 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                    fifo_addr_count_v2__parameterized1_2021 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized7_2022 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                            dp_bram_v2__parameterized2_2016 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                        sync_bcid_rxtx_2002 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                             reg_array__parameterized0_2008 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                             reg_array__parameterized0_2009 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                             reg_array__parameterized0_2010 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                             reg_array__parameterized0_2011 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                             sync_sr2g_2003 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                             pulse_cdc_2005 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                             pulse_cdc_2005 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_2007 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                           sync_fsm_v4_2006 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     JET_TAG_APU_IN_SLR1                                                                     |                                                     dummy_apu_with_ipbus__parameterized8_3 |    235(0.01%) |    235(0.01%) | 0(0.00%) |    0(0.00%) |    329(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (JET_TAG_APU_IN_SLR1)                                                                 |                                                     dummy_apu_with_ipbus__parameterized8_3 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |    169(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                       ipbus_ctrlreg_v__parameterized3_1998 |    166(0.01%) |    166(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     LAR_PREPROC1_APP_IN_SLR3                                                                |                                                                                        app |   7864(0.23%) |   7864(0.23%) | 0(0.00%) |    0(0.00%) |  14865(0.22%) |   69(1.40%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (LAR_PREPROC1_APP_IN_SLR3)                                                            |                                                                                        app |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     88(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                pipeline__parameterized2__6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    456(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                                     logger |    130(0.01%) |    130(0.01%) | 0(0.00%) |    0(0.00%) |    159(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                                     logger |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     94(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                     ipbus_ram_wrapper_1991 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                     ipbus_ram_wrapper_1991 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_1997 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                     ipbus_ram_wrapper_1992 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                     ipbus_ram_wrapper_1992 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_1996 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                     ipbus_ram_wrapper__parameterized0_1993 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                     ipbus_ram_wrapper__parameterized0_1993 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized3_1995 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized2_1994 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                       ipbus_ctrlreg_v__parameterized1_1484 |   2626(0.08%) |   2626(0.08%) | 0(0.00%) |    0(0.00%) |   2076(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__31 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1485 |    229(0.01%) |    229(0.01%) | 0(0.00%) |    0(0.00%) |    341(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1485 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1962 |     59(0.01%) |     59(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1962 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1985 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1986 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1987 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1988 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1989 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1990 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1963 |     59(0.01%) |     59(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1963 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1979 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1980 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1981 |     24(0.01%) |     24(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1982 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1983 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1984 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1964 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1964 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1973 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1974 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1975 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1976 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1977 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1978 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1965 |     53(0.01%) |     53(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1965 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1967 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1968 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1969 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1970 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1971 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1972 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1966 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                        sync_bcid_rxtx_1486 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                 mux41__parameterized2_1957 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                             reg_array__parameterized0_1958 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                             reg_array__parameterized0_1959 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                             reg_array__parameterized0_1960 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                             reg_array__parameterized0_1961 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1487 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[10].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__22 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    418(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[10].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                       sync_mt_fifo_v2_1488 |    256(0.01%) |    256(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[10].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                       sync_mt_fifo_v2_1488 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1928 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1928 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1951 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1952 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1953 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1954 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1955 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1956 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1929 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1929 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1945 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1946 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1947 |     34(0.01%) |     34(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1948 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1949 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1950 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1930 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1930 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1939 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1940 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1941 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1942 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1943 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1944 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1931 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1931 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1933 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1934 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1935 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1936 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1937 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1938 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1932 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[10].sync_if.sync_sr                                                           |                                                                             sync_sr2g_1489 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[11].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__21 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[11].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                       sync_mt_fifo_v2_1490 |    385(0.01%) |    385(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[11].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                       sync_mt_fifo_v2_1490 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1899 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1899 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1922 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1923 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1924 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1925 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1926 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1927 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1900 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1900 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1916 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1917 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1918 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1919 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1920 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1921 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1901 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1901 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1910 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1911 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1912 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1913 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1914 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1915 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1902 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1902 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1904 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1905 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1906 |     24(0.01%) |     24(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1907 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1908 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1909 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1903 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[11].sync_if.sync_sr                                                           |                                                                             sync_sr2g_1491 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[12].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__18 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[12].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                       sync_mt_fifo_v2_1492 |    286(0.01%) |    286(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[12].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                       sync_mt_fifo_v2_1492 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1870 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1870 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1893 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1894 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1895 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1896 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1897 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1898 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1871 |     79(0.01%) |     79(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1871 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1887 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1888 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1889 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1890 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1891 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1892 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1872 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1872 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1881 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1882 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1883 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1884 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1885 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1886 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1873 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1873 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1875 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1876 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1877 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1878 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1879 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1880 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1874 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[12].sync_if.sync_sr                                                           |                                                                             sync_sr2g_1493 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[13].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__17 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    410(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[13].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                       sync_mt_fifo_v2_1494 |    291(0.01%) |    291(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[13].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                       sync_mt_fifo_v2_1494 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1841 |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1841 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1864 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1865 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1866 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1867 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1868 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1869 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1842 |     80(0.01%) |     80(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1842 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1858 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1859 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1860 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1861 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1862 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1863 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1843 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1843 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1852 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1853 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1854 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1855 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1856 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1857 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1844 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1844 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1846 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1847 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1848 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1849 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1850 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1851 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1845 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[13].sync_if.sync_sr                                                           |                                                                             sync_sr2g_1495 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[14].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__16 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[14].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                       sync_mt_fifo_v2_1496 |    288(0.01%) |    288(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[14].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                       sync_mt_fifo_v2_1496 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1812 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1812 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1835 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1836 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1837 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1838 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1839 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1840 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1813 |     79(0.01%) |     79(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1813 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1829 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1830 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1831 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1832 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1833 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1834 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1814 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1814 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1823 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1824 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1825 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1826 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1827 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1828 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1815 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1815 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1817 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1818 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1819 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1820 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1821 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1822 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1816 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[14].sync_if.sync_sr                                                           |                                                                             sync_sr2g_1497 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[15].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__29 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    410(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[15].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                       sync_mt_fifo_v2_1498 |    551(0.02%) |    551(0.02%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[15].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                       sync_mt_fifo_v2_1498 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1783 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1783 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1806 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1807 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1808 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1809 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1810 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1811 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1784 |     80(0.01%) |     80(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1784 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1800 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1801 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1802 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1803 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1804 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1805 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1785 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1785 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1794 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1795 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1796 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1797 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1798 |     39(0.01%) |     39(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1799 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1786 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1786 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1788 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1789 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1790 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1791 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1792 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1793 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1787 |    256(0.01%) |    256(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[15].sync_if.sync_sr                                                           |                                                                             sync_sr2g_1499 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__30 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1500 |    228(0.01%) |    228(0.01%) | 0(0.00%) |    0(0.00%) |    344(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1500 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1754 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1754 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1777 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1778 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1779 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1780 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1781 |     29(0.01%) |     29(0.01%) | 0(0.00%) |    0(0.00%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1782 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1755 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     47(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1755 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1771 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1772 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1773 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1774 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1775 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1776 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1756 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1756 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1765 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1766 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1767 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1768 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1769 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1770 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1757 |     53(0.01%) |     53(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1757 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1759 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1760 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1761 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1762 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1763 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1764 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1758 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1501 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__28 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1502 |    234(0.01%) |    234(0.01%) | 0(0.00%) |    0(0.00%) |    346(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1502 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1725 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     52(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1725 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1748 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1749 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1750 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1751 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1752 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1753 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1726 |     59(0.01%) |     59(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1726 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1742 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1743 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1744 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1745 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1746 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1747 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1727 |     59(0.01%) |     59(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1727 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1736 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1737 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1738 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1739 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1740 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1741 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1728 |     55(0.01%) |     55(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1728 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1730 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1731 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1732 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1733 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1734 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1735 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1729 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1503 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__26 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1504 |    418(0.01%) |    418(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1504 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1696 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1696 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1719 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1720 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1721 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1722 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1723 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1724 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1697 |     81(0.01%) |     81(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1697 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1713 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1714 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1715 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1716 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1717 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1718 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1698 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1698 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1707 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1708 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1709 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1710 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1711 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1712 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1699 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1699 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1701 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1702 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1703 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1704 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1705 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1706 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1700 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1505 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[4].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__25 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[4].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1506 |    287(0.01%) |    287(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[4].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1506 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1667 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1667 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1690 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1691 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1692 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1693 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1694 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1695 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1668 |     80(0.01%) |     80(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1668 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1684 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1685 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1686 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1687 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1688 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1689 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1669 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1669 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1678 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1679 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1680 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1681 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1682 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1683 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1670 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1670 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1672 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1673 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1674 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1675 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1676 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1677 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1671 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[4].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1507 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[5].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__23 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[5].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1508 |    291(0.01%) |    291(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[5].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1508 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1638 |     76(0.01%) |     76(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1638 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1661 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1662 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1663 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1664 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1665 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1666 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1639 |     78(0.01%) |     78(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1639 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1655 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1656 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1657 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1658 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1659 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1660 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1640 |     66(0.01%) |     66(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1640 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1649 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1650 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1651 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1652 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1653 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1654 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1641 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1641 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1643 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1644 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1645 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1646 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1647 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1648 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1642 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[5].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1509 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[6].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__24 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    410(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[6].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1510 |    286(0.01%) |    286(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[6].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1510 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1609 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1609 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1632 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1633 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1634 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1635 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1636 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1637 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1610 |     79(0.01%) |     79(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1610 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1626 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1627 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1628 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1629 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1630 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1631 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1611 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1611 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1620 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1621 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1622 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1623 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1624 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1625 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1612 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1612 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1614 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1615 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1616 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1617 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1618 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1619 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1613 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[6].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1511 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[7].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__19 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[7].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1512 |    385(0.01%) |    385(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[7].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1512 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1580 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1580 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1603 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1604 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1605 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1606 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1607 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1608 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1581 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1581 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1597 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1598 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1599 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1600 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1601 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1602 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1582 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1582 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1591 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1592 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1593 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1594 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1595 |     34(0.01%) |     34(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1596 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1583 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1583 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1585 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1586 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1587 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1588 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1589 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1590 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1584 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[7].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1513 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[8].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__27 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[8].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1514 |    290(0.01%) |    290(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[8].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1514 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1551 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1551 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1574 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1575 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1576 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1577 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1578 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1579 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1552 |     80(0.01%) |     80(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1552 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1568 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1569 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1570 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1571 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1572 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1573 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1553 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1553 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1562 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1563 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1564 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1565 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1566 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1567 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1554 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1554 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1556 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1557 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1558 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1559 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1560 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1561 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1555 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[8].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1515 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[9].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__20 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    420(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[9].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1516 |    255(0.01%) |    255(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[9].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1516 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1522 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1522 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1545 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1546 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1547 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1548 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1549 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1550 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1523 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1523 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1539 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1540 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1541 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1542 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1543 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1544 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1524 |     59(0.01%) |     59(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1524 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1533 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1534 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1535 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1536 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1537 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1538 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1525 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1525 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1527 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1528 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1529 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1530 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1531 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1532 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1526 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[9].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1517 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                             pulse_cdc_1519 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                             pulse_cdc_1519 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_1521 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                           sync_fsm_v4_1520 |     46(0.01%) |     46(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     LAR_PREPROC1_APU_IN_SLR3                                                                |                                                                       dummy_apu_with_ipbus |    310(0.01%) |    310(0.01%) | 0(0.00%) |    0(0.00%) |    416(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (LAR_PREPROC1_APU_IN_SLR3)                                                            |                                                                       dummy_apu_with_ipbus |     92(0.01%) |     92(0.01%) | 0(0.00%) |    0(0.00%) |    248(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                       ipbus_ctrlreg_v__parameterized3_1483 |    218(0.01%) |    218(0.01%) | 0(0.00%) |    0(0.00%) |    168(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     LAR_PREPROC2_APP_IN_SLR3                                                                |                                                                        app__parameterized0 |   7985(0.24%) |   7985(0.24%) | 0(0.00%) |    0(0.00%) |  14832(0.22%) |   69(1.40%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (LAR_PREPROC2_APP_IN_SLR3)                                                            |                                                                        app__parameterized0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     77(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__32 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                     logger__parameterized0 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |    155(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                     logger__parameterized0 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     90(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                     ipbus_ram_wrapper_1476 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                     ipbus_ram_wrapper_1476 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_1482 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                     ipbus_ram_wrapper_1477 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                     ipbus_ram_wrapper_1477 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized2_1481 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                     ipbus_ram_wrapper__parameterized0_1478 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                     ipbus_ram_wrapper__parameterized0_1478 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                  dual_port_bram_infer__parameterized3_1480 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized2_1479 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                        ipbus_ctrlreg_v__parameterized1_969 |   2651(0.08%) |   2651(0.08%) | 0(0.00%) |    0(0.00%) |   2076(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__48 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    450(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_970 |    234(0.01%) |    234(0.01%) | 0(0.00%) |    0(0.00%) |    367(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_970 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1447 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     70(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1447 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1470 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1471 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1472 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     21(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1473 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1474 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     21(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1475 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1448 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1448 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1464 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1465 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1466 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1467 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1468 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1469 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1449 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1449 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1458 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1459 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1460 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1461 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1462 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1463 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1450 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     69(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1450 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1452 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1453 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1454 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     21(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1455 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1456 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1457 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1451 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                         sync_bcid_rxtx_971 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                 mux41__parameterized2_1442 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                             reg_array__parameterized0_1443 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                             reg_array__parameterized0_1444 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                             reg_array__parameterized0_1445 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                             reg_array__parameterized0_1446 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                              sync_sr2g_972 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[10].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__39 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[10].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                        sync_mt_fifo_v2_973 |    271(0.01%) |    271(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[10].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                        sync_mt_fifo_v2_973 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1413 |     68(0.01%) |     68(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1413 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1436 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1437 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1438 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1439 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1440 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1441 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1414 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1414 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1430 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1431 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1432 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1433 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1434 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1435 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1415 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1415 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1424 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1425 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1426 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1427 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1428 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1429 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1416 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1416 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1418 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1419 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1420 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1421 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1422 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1423 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1417 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[10].sync_if.sync_sr                                                           |                                                                              sync_sr2g_974 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[11].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__38 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[11].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                        sync_mt_fifo_v2_975 |    408(0.01%) |    408(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[11].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                        sync_mt_fifo_v2_975 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1384 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1384 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1407 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1408 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1409 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1410 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1411 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1412 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1385 |     78(0.01%) |     78(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1385 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1401 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1402 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1403 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1404 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1405 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1406 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1386 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1386 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1395 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1396 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1397 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1398 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1399 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1400 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1387 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1387 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1389 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1390 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1391 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1392 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1393 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1394 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1388 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[11].sync_if.sync_sr                                                           |                                                                              sync_sr2g_976 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[12].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__35 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[12].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                        sync_mt_fifo_v2_977 |    291(0.01%) |    291(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[12].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                        sync_mt_fifo_v2_977 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1355 |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1355 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1378 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1379 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1380 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1381 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1382 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1383 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1356 |     78(0.01%) |     78(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1356 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1372 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1373 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1374 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1375 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1376 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1377 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1357 |     67(0.01%) |     67(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1357 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1366 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1367 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1368 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1369 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1370 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1371 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1358 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1358 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1360 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1361 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1362 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1363 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1364 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1365 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1359 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[12].sync_if.sync_sr                                                           |                                                                              sync_sr2g_978 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[13].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__34 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[13].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                        sync_mt_fifo_v2_979 |    294(0.01%) |    294(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[13].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                        sync_mt_fifo_v2_979 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1326 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1326 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1349 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1350 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1351 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1352 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1353 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1354 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1327 |     79(0.01%) |     79(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1327 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1343 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1344 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1345 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1346 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1347 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1348 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1328 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1328 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1337 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1338 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1339 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1340 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1341 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1342 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1329 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1329 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1331 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1332 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1333 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1334 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1335 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1336 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1330 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[13].sync_if.sync_sr                                                           |                                                                              sync_sr2g_980 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[14].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__33 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[14].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                        sync_mt_fifo_v2_981 |    290(0.01%) |    290(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[14].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                        sync_mt_fifo_v2_981 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1297 |     76(0.01%) |     76(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1297 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1320 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1321 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1322 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1323 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1324 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1325 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1298 |     79(0.01%) |     79(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1298 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1314 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1315 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1316 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1317 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1318 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1319 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1299 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1299 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1308 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1309 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1310 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1311 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1312 |     34(0.01%) |     34(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1313 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1300 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1300 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1302 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1303 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1304 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1305 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1306 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1307 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1301 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[14].sync_if.sync_sr                                                           |                                                                              sync_sr2g_982 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[15].FREE_FROM_SLR_input_pipeline                                              |                                                                               pipeline__46 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[15].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                      |                                                                        sync_mt_fifo_v2_983 |    558(0.02%) |    558(0.02%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[15].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                  |                                                                        sync_mt_fifo_v2_983 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1268 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1268 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1291 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1292 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1293 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1294 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1295 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1296 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1269 |     81(0.01%) |     81(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1269 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1285 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1286 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1287 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1288 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1289 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1290 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1270 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1270 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1279 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1280 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1281 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1282 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1283 |     44(0.01%) |     44(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1284 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1271 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1271 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1273 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1274 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1275 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1276 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1277 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1278 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1272 |    256(0.01%) |    256(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[15].sync_if.sync_sr                                                           |                                                                              sync_sr2g_984 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__47 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    419(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_985 |    231(0.01%) |    231(0.01%) | 0(0.00%) |    0(0.00%) |    345(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_985 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1239 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1239 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1262 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1263 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1264 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1265 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1266 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1267 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1240 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1240 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1256 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1257 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1258 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1259 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1260 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1261 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1241 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1241 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1250 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1251 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1252 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1253 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1254 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1255 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1242 |     55(0.01%) |     55(0.01%) | 0(0.00%) |    0(0.00%) |     61(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1242 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1244 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1245 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1246 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1247 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1248 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1249 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1243 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                              sync_sr2g_986 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__45 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    414(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_987 |    238(0.01%) |    238(0.01%) | 0(0.00%) |    0(0.00%) |    326(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_987 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1210 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1210 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1233 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1234 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1235 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1236 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1237 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1238 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1211 |     62(0.01%) |     62(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1211 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1227 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1228 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1229 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1230 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1231 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1232 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1212 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1212 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1221 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1222 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1223 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1224 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1225 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1226 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1213 |     56(0.01%) |     56(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1213 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1215 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1216 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1217 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1218 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1219 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1220 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1214 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].sync_if.sync_sr                                                            |                                                                              sync_sr2g_988 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__43 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_989 |    415(0.01%) |    415(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_989 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1181 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1181 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1204 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1205 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1206 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1207 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1208 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1209 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1182 |     81(0.01%) |     81(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1182 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1198 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1199 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1200 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1201 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1202 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1203 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1183 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1183 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1192 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1193 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1194 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1195 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1196 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1197 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1184 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1184 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1186 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1187 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1188 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1189 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1190 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1191 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1185 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].sync_if.sync_sr                                                            |                                                                              sync_sr2g_990 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[4].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__42 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    412(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[4].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_991 |    289(0.01%) |    289(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[4].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_991 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1152 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1152 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1175 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1176 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1177 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1178 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1179 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1180 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1153 |     78(0.01%) |     78(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1153 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1169 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1170 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1171 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1172 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1173 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1174 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1154 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1154 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1163 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1164 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1165 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1166 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1167 |     35(0.01%) |     35(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1168 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1155 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1155 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1157 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1158 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1159 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1160 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1161 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1162 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1156 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[4].sync_if.sync_sr                                                            |                                                                              sync_sr2g_992 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[5].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__40 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    410(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[5].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_993 |    288(0.01%) |    288(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[5].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_993 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1123 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1123 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1146 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1147 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1148 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1149 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1150 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1151 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1124 |     79(0.01%) |     79(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1124 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1140 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1141 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1142 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1143 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1144 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1145 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1125 |     68(0.01%) |     68(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1125 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1134 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1135 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1136 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1137 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1138 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1139 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1126 |     68(0.01%) |     68(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1126 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1128 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1129 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1130 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1131 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1132 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1133 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1127 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[5].sync_if.sync_sr                                                            |                                                                              sync_sr2g_994 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[6].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__41 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    416(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[6].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_995 |    293(0.01%) |    293(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[6].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_995 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1094 |     78(0.01%) |     78(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1094 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1117 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1118 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1119 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1120 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1121 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1122 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1095 |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1095 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1111 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1112 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1113 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1114 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1115 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1116 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1096 |     66(0.01%) |     66(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1096 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1105 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1106 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1107 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1108 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1109 |     35(0.01%) |     35(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1110 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1097 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1097 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1099 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1100 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1101 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1102 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1103 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1104 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1098 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[6].sync_if.sync_sr                                                            |                                                                              sync_sr2g_996 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[7].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__36 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    414(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[7].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_997 |    404(0.01%) |    404(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[7].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_997 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1065 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1065 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1088 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1089 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1090 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1091 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1092 |     34(0.01%) |     34(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1093 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1066 |     76(0.01%) |     76(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1066 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1082 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1083 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1084 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1085 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1086 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1087 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1067 |     67(0.01%) |     67(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1067 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1076 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1077 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1078 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1079 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1080 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1081 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1068 |     63(0.01%) |     63(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1068 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1070 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1071 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1072 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1073 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1074 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1075 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1069 |    128(0.01%) |    128(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[7].sync_if.sync_sr                                                            |                                                                              sync_sr2g_998 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[8].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__44 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[8].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_999 |    289(0.01%) |    289(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[8].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_999 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1036 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1036 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1059 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1060 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1061 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1062 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1063 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1064 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1037 |     79(0.01%) |     79(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1037 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1053 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1054 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1055 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1056 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1057 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1058 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1038 |     66(0.01%) |     66(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1038 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1047 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1048 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1049 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1050 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1051 |     35(0.01%) |     35(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1052 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1039 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1039 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1041 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1042 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1043 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1044 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1045 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1046 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1040 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[8].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1000 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[9].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__37 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[9].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                       sync_mt_fifo_v2_1001 |    273(0.01%) |    273(0.01%) | 0(0.00%) |    0(0.00%) |    332(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[9].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                       sync_mt_fifo_v2_1001 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                    sync_fifo_cntrl_v2_1007 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                    sync_fifo_cntrl_v2_1007 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1030 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1031 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1032 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1033 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1034 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1035 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                    sync_fifo_cntrl_v2_1008 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                    sync_fifo_cntrl_v2_1008 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1024 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1025 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1026 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1027 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1028 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1029 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                    sync_fifo_cntrl_v2_1009 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                    sync_fifo_cntrl_v2_1009 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1018 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1019 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1020 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1021 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1022 |     35(0.01%) |     35(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1023 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                    sync_fifo_cntrl_v2_1010 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     53(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                    sync_fifo_cntrl_v2_1010 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                             reg_array_1012 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                             reg_array_1013 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                    fifo_addr_count_v2_1014 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                              sync_rd_side_roll_detect_1015 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                    fifo_addr_count_v2_1016 |     29(0.01%) |     29(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                            perf_count__parameterized2_1017 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                            dp_bram_v2_1011 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[9].sync_if.sync_sr                                                            |                                                                             sync_sr2g_1002 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                             pulse_cdc_1004 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                             pulse_cdc_1004 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_1006 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                           sync_fsm_v4_1005 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     LAR_PREPROC2_APU_IN_SLR3                                                                |                                                                     dummy_apu_with_ipbus_4 |    327(0.01%) |    327(0.01%) | 0(0.00%) |    0(0.00%) |    416(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (LAR_PREPROC2_APU_IN_SLR3)                                                            |                                                                     dummy_apu_with_ipbus_4 |     92(0.01%) |     92(0.01%) | 0(0.00%) |    0(0.00%) |    248(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                        ipbus_ctrlreg_v__parameterized3_968 |    236(0.01%) |    236(0.01%) | 0(0.00%) |    0(0.00%) |    168(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     MET_APP_IN_SLR1                                                                         |                                                                       app__parameterized12 |   1741(0.05%) |   1741(0.05%) | 0(0.00%) |    0(0.00%) |   4248(0.06%) |   14(0.28%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       (MET_APP_IN_SLR1)                                                                     |                                                                       app__parameterized12 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     44(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__80 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                 logger__parameterized4_887 |    124(0.01%) |    124(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                 logger__parameterized4_887 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                      ipbus_ram_wrapper_961 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                      ipbus_ram_wrapper_961 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_967 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                      ipbus_ram_wrapper_962 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                      ipbus_ram_wrapper_962 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_966 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                      ipbus_ram_wrapper__parameterized0_963 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                      ipbus_ram_wrapper__parameterized0_963 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized3_965 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized2_964 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                        ipbus_ctrlreg_v__parameterized1_888 |   1147(0.03%) |   1147(0.03%) | 0(0.00%) |    0(0.00%) |   2053(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__78 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    828(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                        sync_mt_fifo_v2__parameterized2_889 |    260(0.01%) |    260(0.01%) | 0(0.00%) |    0(0.00%) |    474(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                        sync_mt_fifo_v2__parameterized2_889 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    257(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                     sync_fifo_cntrl_v2_932 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                     sync_fifo_cntrl_v2_932 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_955 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_956 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_957 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_958 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_959 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_960 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                     sync_fifo_cntrl_v2_933 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                     sync_fifo_cntrl_v2_933 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_949 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_950 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_951 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_952 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_953 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_954 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                     sync_fifo_cntrl_v2_934 |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     51(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                     sync_fifo_cntrl_v2_934 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_943 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_944 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_945 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_946 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_947 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_948 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                     sync_fifo_cntrl_v2_935 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                     sync_fifo_cntrl_v2_935 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_937 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_938 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_939 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_940 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_941 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_942 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                             dp_bram_v2__parameterized0_936 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                         sync_bcid_rxtx_890 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                  mux41__parameterized2_927 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                              reg_array__parameterized0_928 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                              reg_array__parameterized0_929 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                              reg_array__parameterized0_930 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                              reg_array__parameterized0_931 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                              sync_sr2g_891 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__79 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                        sync_mt_fifo_v2__parameterized6_892 |    165(0.01%) |    165(0.01%) | 0(0.00%) |    0(0.00%) |    197(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                        sync_mt_fifo_v2__parameterized6_892 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                     sync_fifo_cntrl_v2__parameterized1_898 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                     sync_fifo_cntrl_v2__parameterized1_898 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized2_921 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized2_922 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_923 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized1_924 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_925 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized7_926 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                     sync_fifo_cntrl_v2__parameterized1_899 |     44(0.01%) |     44(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                     sync_fifo_cntrl_v2__parameterized1_899 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized2_915 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized2_916 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_917 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized1_918 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_919 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized7_920 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                     sync_fifo_cntrl_v2__parameterized1_900 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                     sync_fifo_cntrl_v2__parameterized1_900 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized2_909 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized2_910 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_911 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized1_912 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_913 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized7_914 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                     sync_fifo_cntrl_v2__parameterized1_901 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                     sync_fifo_cntrl_v2__parameterized1_901 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized2_903 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized2_904 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_905 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized1_906 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_907 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized7_908 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                             dp_bram_v2__parameterized2_902 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                              sync_sr2g_893 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                              pulse_cdc_895 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                              pulse_cdc_895 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_897 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                            sync_fsm_v4_896 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     MET_APU_IN_SLR1                                                                         |                                                     dummy_apu_with_ipbus__parameterized4_5 |    245(0.01%) |    245(0.01%) | 0(0.00%) |    0(0.00%) |    330(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (MET_APU_IN_SLR1)                                                                     |                                                     dummy_apu_with_ipbus__parameterized4_5 |     78(0.01%) |     78(0.01%) | 0(0.00%) |    0(0.00%) |    170(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                        ipbus_ctrlreg_v__parameterized3_886 |    167(0.01%) |    167(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TAU1_APP_IN_SLR3                                                                        |                                                                        app__parameterized3 |   2454(0.07%) |   2454(0.07%) | 0(0.00%) |    0(0.00%) |   5528(0.08%) |   21(0.43%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TAU1_APP_IN_SLR3)                                                                    |                                                                        app__parameterized3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__60 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    252(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                     logger__parameterized3 |    124(0.01%) |    124(0.01%) | 0(0.00%) |    0(0.00%) |    143(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                     logger__parameterized3 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     78(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                      ipbus_ram_wrapper_879 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                      ipbus_ram_wrapper_879 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_885 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                      ipbus_ram_wrapper_880 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                      ipbus_ram_wrapper_880 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_884 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                      ipbus_ram_wrapper__parameterized0_881 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                      ipbus_ram_wrapper__parameterized0_881 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized3_883 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized2_882 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                        ipbus_ctrlreg_v__parameterized1_750 |   1169(0.03%) |   1169(0.03%) | 0(0.00%) |    0(0.00%) |   2054(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__56 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_751 |    295(0.01%) |    295(0.01%) | 0(0.00%) |    0(0.00%) |    337(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_751 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                     sync_fifo_cntrl_v2_850 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                     sync_fifo_cntrl_v2_850 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_873 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_874 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_875 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_876 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_877 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_878 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                     sync_fifo_cntrl_v2_851 |     81(0.01%) |     81(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                     sync_fifo_cntrl_v2_851 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_867 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_868 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_869 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_870 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_871 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_872 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                     sync_fifo_cntrl_v2_852 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                     sync_fifo_cntrl_v2_852 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_861 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_862 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_863 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_864 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_865 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_866 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                     sync_fifo_cntrl_v2_853 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                     sync_fifo_cntrl_v2_853 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_855 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_856 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_857 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_858 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_859 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_860 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                             dp_bram_v2_854 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                         sync_bcid_rxtx_752 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                  mux41__parameterized2_845 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                              reg_array__parameterized0_846 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                              reg_array__parameterized0_847 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                              reg_array__parameterized0_848 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                              reg_array__parameterized0_849 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                              sync_sr2g_753 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__57 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                            sync_mt_fifo_v2__parameterized4 |    247(0.01%) |    247(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                            sync_mt_fifo_v2__parameterized4 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_816 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_816 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_839 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_840 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_841 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_842 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_843 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_844 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_817 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_817 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_833 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_834 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_835 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_836 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_837 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_838 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_818 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_818 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_827 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_828 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_829 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_830 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_831 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_832 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_819 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_819 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_821 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_822 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_823 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_824 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_825 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_826 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                             dp_bram_v2__parameterized1_820 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                              sync_sr2g_754 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__58 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                        sync_mt_fifo_v2__parameterized4_755 |    271(0.01%) |    271(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                        sync_mt_fifo_v2__parameterized4_755 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_787 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_787 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_810 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_811 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_812 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_813 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_814 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_815 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_788 |     75(0.01%) |     75(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_788 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_804 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_805 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_806 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_807 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_808 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_809 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_789 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_789 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_798 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_799 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_800 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_801 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_802 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_803 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_790 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_790 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_792 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_793 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_794 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_795 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_796 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_797 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                             dp_bram_v2__parameterized1_791 |     24(0.01%) |     24(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].sync_if.sync_sr                                                            |                                                                              sync_sr2g_756 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__59 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                        sync_mt_fifo_v2__parameterized4_757 |    289(0.01%) |    289(0.01%) | 0(0.00%) |    0(0.00%) |    313(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                        sync_mt_fifo_v2__parameterized4_757 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                         sync_fifo_cntrl_v2__parameterized0 |     58(0.01%) |     58(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                         sync_fifo_cntrl_v2__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_781 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_782 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_783 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_784 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_785 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_786 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_763 |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_763 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_775 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_776 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_777 |     41(0.01%) |     41(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_778 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_779 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_780 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_764 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_764 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized1_769 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_770 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_771 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized0_772 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_773 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_774 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                     sync_fifo_cntrl_v2__parameterized0_765 |     57(0.01%) |     57(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                     sync_fifo_cntrl_v2__parameterized0_765 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                  reg_array__parameterized1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized1_766 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                         fifo_addr_count_v2__parameterized0 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                   sync_rd_side_roll_detect__parameterized0 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized0_767 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                             perf_count_768 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                 dp_bram_v2__parameterized1 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].sync_if.sync_sr                                                            |                                                                              sync_sr2g_758 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                              pulse_cdc_760 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                              pulse_cdc_760 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_762 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                            sync_fsm_v4_761 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TAU1_APU_IN_SLR3                                                                        |                                                     dummy_apu_with_ipbus__parameterized3_6 |    263(0.01%) |    263(0.01%) | 0(0.00%) |    0(0.00%) |    340(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TAU1_APU_IN_SLR3)                                                                    |                                                     dummy_apu_with_ipbus__parameterized3_6 |     91(0.01%) |     91(0.01%) | 0(0.00%) |    0(0.00%) |    180(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                        ipbus_ctrlreg_v__parameterized3_749 |    172(0.01%) |    172(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TAU2_APP_IN_SLR2                                                                        |                                                                        app__parameterized4 |   1704(0.05%) |   1704(0.05%) | 0(0.00%) |    0(0.00%) |   4248(0.06%) |   14(0.28%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       (TAU2_APP_IN_SLR2)                                                                    |                                                                        app__parameterized4 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     44(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__63 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                     logger__parameterized4 |    124(0.01%) |    124(0.01%) | 0(0.00%) |    0(0.00%) |    141(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                     logger__parameterized4 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                      ipbus_ram_wrapper_742 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                      ipbus_ram_wrapper_742 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_748 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                      ipbus_ram_wrapper_743 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                      ipbus_ram_wrapper_743 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_747 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                      ipbus_ram_wrapper__parameterized0_744 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                      ipbus_ram_wrapper__parameterized0_744 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized3_746 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized2_745 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                        ipbus_ctrlreg_v__parameterized1_676 |   1109(0.03%) |   1109(0.03%) | 0(0.00%) |    0(0.00%) |   2053(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__61 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    252(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                            sync_mt_fifo_v2__parameterized6 |    134(0.01%) |    134(0.01%) | 0(0.00%) |    0(0.00%) |    197(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                            sync_mt_fifo_v2__parameterized6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                         sync_fifo_cntrl_v2__parameterized1 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                         sync_fifo_cntrl_v2__parameterized1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized2_736 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized2_737 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_738 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized1_739 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_740 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized7_741 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                     sync_fifo_cntrl_v2__parameterized1_719 |     45(0.01%) |     45(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                     sync_fifo_cntrl_v2__parameterized1_719 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized2_730 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized2_731 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_732 |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized1_733 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_734 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized7_735 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                     sync_fifo_cntrl_v2__parameterized1_720 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                     sync_fifo_cntrl_v2__parameterized1_720 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized2_724 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized2_725 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_726 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized1_727 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_728 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized7_729 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                     sync_fifo_cntrl_v2__parameterized1_721 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     33(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                     sync_fifo_cntrl_v2__parameterized1_721 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                  reg_array__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized2_722 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                         fifo_addr_count_v2__parameterized1 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                   sync_rd_side_roll_detect__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized1_723 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                 perf_count__parameterized7 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                 dp_bram_v2__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                         sync_bcid_rxtx_677 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                  mux41__parameterized2_714 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                              reg_array__parameterized0_715 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                              reg_array__parameterized0_716 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                              reg_array__parameterized0_717 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                              reg_array__parameterized0_718 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                              sync_sr2g_678 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__62 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    792(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                        sync_mt_fifo_v2__parameterized2_679 |    290(0.01%) |    290(0.01%) | 0(0.00%) |    0(0.00%) |    474(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                        sync_mt_fifo_v2__parameterized2_679 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    257(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                     sync_fifo_cntrl_v2_685 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                     sync_fifo_cntrl_v2_685 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_708 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_709 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_710 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_711 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_712 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_713 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                     sync_fifo_cntrl_v2_686 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                     sync_fifo_cntrl_v2_686 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_702 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_703 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_704 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_705 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_706 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_707 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                     sync_fifo_cntrl_v2_687 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     51(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                     sync_fifo_cntrl_v2_687 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_696 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_697 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_698 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_699 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_700 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_701 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                     sync_fifo_cntrl_v2_688 |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                     sync_fifo_cntrl_v2_688 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_690 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_691 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_692 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_693 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_694 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_695 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                             dp_bram_v2__parameterized0_689 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                              sync_sr2g_680 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                              pulse_cdc_682 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                              pulse_cdc_682 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_684 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                            sync_fsm_v4_683 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TAU2_APU_IN_SLR2                                                                        |                                                     dummy_apu_with_ipbus__parameterized4_7 |    244(0.01%) |    244(0.01%) | 0(0.00%) |    0(0.00%) |    330(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TAU2_APU_IN_SLR2)                                                                    |                                                     dummy_apu_with_ipbus__parameterized4_7 |     78(0.01%) |     78(0.01%) | 0(0.00%) |    0(0.00%) |    170(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                        ipbus_ctrlreg_v__parameterized3_675 |    167(0.01%) |    167(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR0_FOR[0].source_tgen_IN_SLR0                                                   |                                                                                 ipbus_tgen |    973(0.03%) |    973(0.03%) | 0(0.00%) |    0(0.00%) |   2530(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR0_FOR[0].source_tgen_IN_SLR0)                                               |                                                                                 ipbus_tgen |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__106 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__105 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_669 |    105(0.01%) |    105(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_670 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_670 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_673 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_674 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_671 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_672 |    864(0.03%) |    864(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR0_FOR[1].source_tgen_IN_SLR0                                                   |                                                                               ipbus_tgen_8 |    974(0.03%) |    974(0.03%) | 0(0.00%) |    0(0.00%) |   2530(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR0_FOR[1].source_tgen_IN_SLR0)                                               |                                                                               ipbus_tgen_8 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__108 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__107 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_663 |    106(0.01%) |    106(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_664 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_664 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_667 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_668 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_665 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_666 |    864(0.03%) |    864(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR0_FOR[2].source_tgen_IN_SLR0                                                   |                                                                               ipbus_tgen_9 |    972(0.03%) |    972(0.03%) | 0(0.00%) |    0(0.00%) |   2530(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR0_FOR[2].source_tgen_IN_SLR0)                                               |                                                                               ipbus_tgen_9 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__110 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__109 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_657 |    106(0.01%) |    106(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_658 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_658 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_661 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_662 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_659 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_660 |    862(0.03%) |    862(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR0_FOR[3].source_tgen_IN_SLR0                                                   |                                                                              ipbus_tgen_10 |    987(0.03%) |    987(0.03%) | 0(0.00%) |    0(0.00%) |   2530(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR0_FOR[3].source_tgen_IN_SLR0)                                               |                                                                              ipbus_tgen_10 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                                pipeline__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                                pipeline__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_651 |    106(0.01%) |    106(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_652 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_652 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_655 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_656 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_653 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_654 |    877(0.03%) |    877(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR0_FOR[4].source_tgen_IN_SLR0                                                   |                                                                 ipbus_tgen__parameterized0 |    971(0.03%) |    971(0.03%) | 0(0.00%) |    0(0.00%) |   2530(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR0_FOR[4].source_tgen_IN_SLR0)                                               |                                                                 ipbus_tgen__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                                pipeline__3 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                                pipeline__4 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_645 |    105(0.01%) |    105(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_646 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_646 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_649 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_650 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_647 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_648 |    863(0.03%) |    863(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[0].source_tgen_IN_SLR2                                                   |                                                                 ipbus_tgen__parameterized1 |    997(0.03%) |    997(0.03%) | 0(0.00%) |    0(0.00%) |   2602(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[0].source_tgen_IN_SLR2)                                               |                                                                 ipbus_tgen__parameterized1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__111 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                pipeline__parameterized2__8 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    456(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_639 |    115(0.01%) |    115(0.01%) | 0(0.00%) |    0(0.00%) |     71(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_640 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_640 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_643 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_644 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_641 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_642 |    879(0.03%) |    879(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[1].source_tgen_IN_SLR2                                                   |                                                              ipbus_tgen__parameterized1_11 |    989(0.03%) |    989(0.03%) | 0(0.00%) |    0(0.00%) |   2542(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[1].source_tgen_IN_SLR2)                                               |                                                              ipbus_tgen__parameterized1_11 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__112 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                pipeline__parameterized2__9 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    420(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_633 |    108(0.01%) |    108(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_634 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_634 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_637 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_638 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_635 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_636 |    877(0.03%) |    877(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[2].source_tgen_IN_SLR2                                                   |                                                              ipbus_tgen__parameterized1_12 |    988(0.03%) |    988(0.03%) | 0(0.00%) |    0(0.00%) |   2542(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[2].source_tgen_IN_SLR2)                                               |                                                              ipbus_tgen__parameterized1_12 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                                pipeline__5 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                pipeline__parameterized2__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    420(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_627 |    108(0.01%) |    108(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_628 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_628 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_631 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_632 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_629 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_630 |    876(0.03%) |    876(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[3].source_tgen_IN_SLR2                                                   |                                                                 ipbus_tgen__parameterized2 |    986(0.03%) |    986(0.03%) | 0(0.00%) |    0(0.00%) |   2542(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[3].source_tgen_IN_SLR2)                                               |                                                                 ipbus_tgen__parameterized2 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__113 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                               pipeline__parameterized2__10 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    420(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_621 |    109(0.01%) |    109(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_622 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_622 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_625 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_626 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_623 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_624 |    873(0.03%) |    873(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[4].source_tgen_IN_SLR2                                                   |                                                              ipbus_tgen__parameterized2_13 |    989(0.03%) |    989(0.03%) | 0(0.00%) |    0(0.00%) |   2542(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[4].source_tgen_IN_SLR2)                                               |                                                              ipbus_tgen__parameterized2_13 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__114 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                               pipeline__parameterized2__11 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    420(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_615 |    109(0.01%) |    109(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_616 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_616 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_619 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_620 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_617 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_618 |    876(0.03%) |    876(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[5].source_tgen_IN_SLR2                                                   |                                                              ipbus_tgen__parameterized2_14 |    986(0.03%) |    986(0.03%) | 0(0.00%) |    0(0.00%) |   2542(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[5].source_tgen_IN_SLR2)                                               |                                                              ipbus_tgen__parameterized2_14 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                                pipeline__6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                pipeline__parameterized2__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    420(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_609 |    108(0.01%) |    108(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_610 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_610 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_613 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_614 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_611 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_612 |    874(0.03%) |    874(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[6].source_tgen_IN_SLR2                                                   |                                                                 ipbus_tgen__parameterized3 |    978(0.03%) |    978(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[6].source_tgen_IN_SLR2)                                               |                                                                 ipbus_tgen__parameterized3 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                                pipeline__7 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                pipeline__parameterized2__3 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_603 |     98(0.01%) |     98(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_604 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_604 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_607 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_608 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_605 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_606 |    876(0.03%) |    876(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[7].source_tgen_IN_SLR2                                                   |                                                                 ipbus_tgen__parameterized4 |    987(0.03%) |    987(0.03%) | 0(0.00%) |    0(0.00%) |   2622(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[7].source_tgen_IN_SLR2)                                               |                                                                 ipbus_tgen__parameterized4 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__115 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                               pipeline__parameterized2__12 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    500(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_597 |    109(0.01%) |    109(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_598 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_598 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_601 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_602 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_599 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_600 |    874(0.03%) |    874(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[8].source_tgen_IN_SLR2                                                   |                                                              ipbus_tgen__parameterized4_15 |   1339(0.04%) |   1339(0.04%) | 0(0.00%) |    0(0.00%) |   2530(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[8].source_tgen_IN_SLR2)                                               |                                                              ipbus_tgen__parameterized4_15 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                                pipeline__8 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                pipeline__parameterized2__4 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                   tgen_591 |    107(0.01%) |    107(0.01%) | 0(0.00%) |    0(0.00%) |     59(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                             dp_ram_ipb_592 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                             dp_ram_ipb_592 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                   dual_port_bram_infer_595 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_596 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_593 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_594 |   1228(0.04%) |   1228(0.04%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR2_FOR[9].source_tgen_IN_SLR2                                                   |                                                                 ipbus_tgen__parameterized5 |    992(0.03%) |    992(0.03%) | 0(0.00%) |    0(0.00%) |   2590(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR2_FOR[9].source_tgen_IN_SLR2)                                               |                                                                 ipbus_tgen__parameterized5 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                                pipeline__9 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                pipeline__parameterized2__5 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                                       tgen |    113(0.01%) |    113(0.01%) | 0(0.00%) |    0(0.00%) |     71(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                                 dp_ram_ipb |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                                 dp_ram_ipb |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                                       dual_port_bram_infer |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_590 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                                             perf_count_588 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_589 |    876(0.03%) |    876(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[0].source_tgen_IN_SLR3                                                   |                                                                 ipbus_tgen__parameterized6 |   1006(0.03%) |   1006(0.03%) | 0(0.00%) |    0(0.00%) |   2591(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[0].source_tgen_IN_SLR3)                                               |                                                                 ipbus_tgen__parameterized6 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__117 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__116 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_582 |    110(0.01%) |    110(0.01%) | 0(0.00%) |    0(0.00%) |     72(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_583 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_583 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_586 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_587 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_584 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_585 |    892(0.03%) |    892(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[10].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_16 |    994(0.03%) |    994(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[10].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_16 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__137 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__136 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_576 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_577 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_577 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_580 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_581 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_578 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_579 |    887(0.03%) |    887(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[11].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_17 |    992(0.03%) |    992(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[11].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_17 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__139 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__138 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_570 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_571 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_571 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_574 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_575 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_572 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_573 |    885(0.03%) |    885(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[12].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_18 |    991(0.03%) |    991(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[12].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_18 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__141 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__140 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_564 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_565 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_565 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_568 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_569 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_566 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_567 |    884(0.03%) |    884(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[13].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_19 |    994(0.03%) |    994(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[13].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_19 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__143 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__142 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_558 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_559 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_559 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_562 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_563 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_560 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_561 |    887(0.03%) |    887(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[14].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_20 |    995(0.03%) |    995(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[14].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_20 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__145 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__144 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_552 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_553 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_553 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_556 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_557 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_554 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_555 |    888(0.03%) |    888(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[15].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_21 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[15].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_21 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__147 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__146 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_546 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_547 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_547 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_550 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_551 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_548 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_549 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[16].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_22 |   1032(0.03%) |   1032(0.03%) | 0(0.00%) |    0(0.00%) |   2591(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[16].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_22 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__149 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__148 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_540 |    110(0.01%) |    110(0.01%) | 0(0.00%) |    0(0.00%) |     72(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_541 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_541 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_544 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_545 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_542 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_543 |    918(0.03%) |    918(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[17].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_23 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[17].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_23 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__151 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__150 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_534 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_535 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_535 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_538 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_539 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_536 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_537 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[18].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_24 |   1016(0.03%) |   1016(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[18].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_24 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__153 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__152 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_528 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_529 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_529 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_532 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_533 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_530 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_531 |    909(0.03%) |    909(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[19].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_25 |    994(0.03%) |    994(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[19].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_25 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__155 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__154 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_522 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_523 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_523 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_526 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_527 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_524 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_525 |    887(0.03%) |    887(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[1].source_tgen_IN_SLR3                                                   |                                                              ipbus_tgen__parameterized6_26 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[1].source_tgen_IN_SLR3)                                               |                                                              ipbus_tgen__parameterized6_26 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__119 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__118 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_516 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_517 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_517 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_520 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_521 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_518 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_519 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[20].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_27 |    992(0.03%) |    992(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[20].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_27 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__157 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__156 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_510 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_511 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_511 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_514 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_515 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_512 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_513 |    885(0.03%) |    885(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[21].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_28 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[21].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_28 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__159 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__158 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_504 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_505 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_505 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_508 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_509 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_506 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_507 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[22].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_29 |    992(0.03%) |    992(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[22].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_29 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__161 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__160 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_498 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_499 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_499 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_502 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_503 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_500 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_501 |    885(0.03%) |    885(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[23].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_30 |   1005(0.03%) |   1005(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[23].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_30 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__163 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__162 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_492 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_493 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_493 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_496 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_497 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_494 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_495 |    898(0.03%) |    898(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[24].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_31 |    992(0.03%) |    992(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[24].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_31 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__165 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__164 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_486 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_487 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_487 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_490 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_491 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_488 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_489 |    885(0.03%) |    885(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[25].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_32 |   1003(0.03%) |   1003(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[25].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_32 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__167 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__166 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_480 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_481 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_481 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_484 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_485 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_482 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_483 |    896(0.03%) |    896(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[26].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_33 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[26].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_33 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__169 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__168 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_474 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_475 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_475 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_478 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_479 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_476 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_477 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[27].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_34 |    994(0.03%) |    994(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[27].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_34 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__171 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__170 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_468 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_469 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_469 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_472 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_473 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_470 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_471 |    887(0.03%) |    887(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[28].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_35 |   1030(0.03%) |   1030(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[28].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_35 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__173 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__172 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_462 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_463 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_463 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_466 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_467 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_464 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_465 |    923(0.03%) |    923(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[29].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_36 |   1027(0.03%) |   1027(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[29].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_36 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__175 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__174 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_456 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_457 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_457 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_460 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_461 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_458 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_459 |    920(0.03%) |    920(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[2].source_tgen_IN_SLR3                                                   |                                                              ipbus_tgen__parameterized6_37 |   1018(0.03%) |   1018(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[2].source_tgen_IN_SLR3)                                               |                                                              ipbus_tgen__parameterized6_37 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__121 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__120 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_450 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_451 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_451 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_454 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_455 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_452 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_453 |    911(0.03%) |    911(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[30].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_38 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[30].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_38 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__177 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__176 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_444 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_445 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_445 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_448 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_449 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_446 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_447 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[31].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized6_39 |    994(0.03%) |    994(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[31].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized6_39 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                               pipeline__10 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__11 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_438 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_439 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_439 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_442 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_443 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_440 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_441 |    887(0.03%) |    887(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[32].source_tgen_IN_SLR3                                                  |                                                                 ipbus_tgen__parameterized8 |   1003(0.03%) |   1003(0.03%) | 0(0.00%) |    0(0.00%) |   2591(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[32].source_tgen_IN_SLR3)                                              |                                                                 ipbus_tgen__parameterized8 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__179 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__178 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_432 |    110(0.01%) |    110(0.01%) | 0(0.00%) |    0(0.00%) |     72(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_433 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_433 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_436 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_437 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_434 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_435 |    889(0.03%) |    889(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[33].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized8_40 |    995(0.03%) |    995(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[33].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized8_40 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__181 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__180 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_426 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_427 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_427 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_430 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_431 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_428 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_429 |    888(0.03%) |    888(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[34].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized8_41 |    992(0.03%) |    992(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[34].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized8_41 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__183 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__182 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_420 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_421 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_421 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_424 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_425 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_422 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_423 |    885(0.03%) |    885(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[35].source_tgen_IN_SLR3                                                  |                                                              ipbus_tgen__parameterized8_42 |    992(0.03%) |    992(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[35].source_tgen_IN_SLR3)                                              |                                                              ipbus_tgen__parameterized8_42 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                               pipeline__12 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__13 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_414 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_415 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_415 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_418 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_419 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_416 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_417 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[3].source_tgen_IN_SLR3                                                   |                                                              ipbus_tgen__parameterized6_43 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[3].source_tgen_IN_SLR3)                                               |                                                              ipbus_tgen__parameterized6_43 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__123 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__122 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_408 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_409 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_409 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_412 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_413 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_410 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_411 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[4].source_tgen_IN_SLR3                                                   |                                                              ipbus_tgen__parameterized6_44 |    992(0.03%) |    992(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[4].source_tgen_IN_SLR3)                                               |                                                              ipbus_tgen__parameterized6_44 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__125 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__124 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_402 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_403 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_403 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_406 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_407 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_404 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_405 |    885(0.03%) |    885(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[5].source_tgen_IN_SLR3                                                   |                                                              ipbus_tgen__parameterized6_45 |    994(0.03%) |    994(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[5].source_tgen_IN_SLR3)                                               |                                                              ipbus_tgen__parameterized6_45 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__127 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__126 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_396 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_397 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_397 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_400 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_401 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_398 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_399 |    887(0.03%) |    887(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[6].source_tgen_IN_SLR3                                                   |                                                              ipbus_tgen__parameterized6_46 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[6].source_tgen_IN_SLR3)                                               |                                                              ipbus_tgen__parameterized6_46 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__129 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__128 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_390 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_391 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_391 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_394 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_395 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_392 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_393 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[7].source_tgen_IN_SLR3                                                   |                                                              ipbus_tgen__parameterized6_47 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[7].source_tgen_IN_SLR3)                                               |                                                              ipbus_tgen__parameterized6_47 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__131 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__130 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_384 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_385 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_385 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_388 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_389 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_386 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_387 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[8].source_tgen_IN_SLR3                                                   |                                                              ipbus_tgen__parameterized6_48 |    993(0.03%) |    993(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[8].source_tgen_IN_SLR3)                                               |                                                              ipbus_tgen__parameterized6_48 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__133 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__132 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                   tgen__parameterized2_378 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                             dp_ram_ipb__parameterized0_379 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                             dp_ram_ipb__parameterized0_379 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                   dual_port_bram_infer__parameterized0_382 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_383 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_380 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_381 |    886(0.03%) |    886(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TGENS_SLR3_FOR[9].source_tgen_IN_SLR3                                                   |                                                              ipbus_tgen__parameterized6_49 |    991(0.03%) |    991(0.03%) | 0(0.00%) |    0(0.00%) |   2531(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TGENS_SLR3_FOR[9].source_tgen_IN_SLR3)                                               |                                                              ipbus_tgen__parameterized6_49 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__135 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                              pipeline__134 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                       tgen__parameterized2 |    103(0.01%) |    103(0.01%) | 0(0.00%) |    0(0.00%) |     60(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                 dp_ram_ipb__parameterized0 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                 dp_ram_ipb__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                       dual_port_bram_infer__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_377 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                             perf_count__parameterized2_375 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized1_376 |    884(0.03%) |    884(0.03%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TILECAL_PREPROC_APP_IN_SLR3                                                             |                                                                        app__parameterized1 |   2617(0.08%) |   2617(0.08%) | 0(0.00%) |    0(0.00%) |   5810(0.09%) |   21(0.43%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TILECAL_PREPROC_APP_IN_SLR3)                                                         |                                                                        app__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     52(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                pipeline__parameterized2__7 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    456(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                     logger__parameterized1 |    126(0.01%) |    126(0.01%) | 0(0.00%) |    0(0.00%) |    147(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                     logger__parameterized1 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     82(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                      ipbus_ram_wrapper_368 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                      ipbus_ram_wrapper_368 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_374 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                      ipbus_ram_wrapper_369 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                      ipbus_ram_wrapper_369 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_373 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                      ipbus_ram_wrapper__parameterized0_370 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                      ipbus_ram_wrapper__parameterized0_370 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized3_372 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized2_371 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                        ipbus_ctrlreg_v__parameterized1_233 |   1143(0.03%) |   1143(0.03%) | 0(0.00%) |    0(0.00%) |   2052(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__49 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_234 |    369(0.01%) |    369(0.01%) | 0(0.00%) |    0(0.00%) |    337(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_234 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                     sync_fifo_cntrl_v2_339 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                     sync_fifo_cntrl_v2_339 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_362 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_363 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_364 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_365 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_366 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_367 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                     sync_fifo_cntrl_v2_340 |     79(0.01%) |     79(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                     sync_fifo_cntrl_v2_340 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_356 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_357 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_358 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_359 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_360 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_361 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                     sync_fifo_cntrl_v2_341 |     67(0.01%) |     67(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                     sync_fifo_cntrl_v2_341 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_350 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_351 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_352 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_353 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_354 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_355 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                     sync_fifo_cntrl_v2_342 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                     sync_fifo_cntrl_v2_342 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_344 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_345 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_346 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_347 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_348 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_349 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                             dp_bram_v2_343 |     80(0.01%) |     80(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                         sync_bcid_rxtx_235 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                  mux41__parameterized2_334 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                              reg_array__parameterized0_335 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                              reg_array__parameterized0_336 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                              reg_array__parameterized0_337 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                              reg_array__parameterized0_338 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                              sync_sr2g_236 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__50 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_237 |    333(0.01%) |    333(0.01%) | 0(0.00%) |    0(0.00%) |    337(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_237 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                     sync_fifo_cntrl_v2_305 |     76(0.01%) |     76(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                     sync_fifo_cntrl_v2_305 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_328 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_329 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_330 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_331 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_332 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_333 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                     sync_fifo_cntrl_v2_306 |     76(0.01%) |     76(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                     sync_fifo_cntrl_v2_306 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_322 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_323 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_324 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_325 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_326 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_327 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                     sync_fifo_cntrl_v2_307 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                     sync_fifo_cntrl_v2_307 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_316 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_317 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_318 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_319 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_320 |     34(0.01%) |     34(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_321 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                     sync_fifo_cntrl_v2_308 |     68(0.01%) |     68(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                     sync_fifo_cntrl_v2_308 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_310 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_311 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_312 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_313 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_314 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_315 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                             dp_bram_v2_309 |     48(0.01%) |     48(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                              sync_sr2g_238 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__51 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_239 |    290(0.01%) |    290(0.01%) | 0(0.00%) |    0(0.00%) |    337(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_239 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                     sync_fifo_cntrl_v2_276 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                     sync_fifo_cntrl_v2_276 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_299 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_300 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_301 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_302 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_303 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_304 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                     sync_fifo_cntrl_v2_277 |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                     sync_fifo_cntrl_v2_277 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_293 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_294 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_295 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_296 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_297 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_298 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                     sync_fifo_cntrl_v2_278 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                     sync_fifo_cntrl_v2_278 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_287 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_288 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_289 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_290 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_291 |     38(0.01%) |     38(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_292 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                     sync_fifo_cntrl_v2_279 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                     sync_fifo_cntrl_v2_279 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_281 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_282 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_283 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_284 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_285 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_286 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                             dp_bram_v2_280 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].sync_if.sync_sr                                                            |                                                                              sync_sr2g_240 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__52 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                        sync_mt_fifo_v2_241 |    290(0.01%) |    290(0.01%) | 0(0.00%) |    0(0.00%) |    337(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                        sync_mt_fifo_v2_241 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                     sync_fifo_cntrl_v2_247 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                     sync_fifo_cntrl_v2_247 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_270 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_271 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_272 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_273 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_274 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_275 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                     sync_fifo_cntrl_v2_248 |     78(0.01%) |     78(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                     sync_fifo_cntrl_v2_248 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_264 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_265 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_266 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_267 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_268 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_269 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                     sync_fifo_cntrl_v2_249 |     69(0.01%) |     69(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                     sync_fifo_cntrl_v2_249 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_258 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_259 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_260 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_261 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_262 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_263 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                     sync_fifo_cntrl_v2_250 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                     sync_fifo_cntrl_v2_250 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_252 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_253 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_254 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_255 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_256 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_257 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                             dp_bram_v2_251 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[3].sync_if.sync_sr                                                            |                                                                              sync_sr2g_242 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                              pulse_cdc_244 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                              pulse_cdc_244 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_246 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                            sync_fsm_v4_245 |     26(0.01%) |     26(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TILECAL_PREPROC_APU_IN_SLR3                                                             |                                                       dummy_apu_with_ipbus__parameterized1 |    248(0.01%) |    248(0.01%) | 0(0.00%) |    0(0.00%) |    396(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TILECAL_PREPROC_APU_IN_SLR3)                                                         |                                                       dummy_apu_with_ipbus__parameterized1 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |    236(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                        ipbus_ctrlreg_v__parameterized3_232 |    178(0.01%) |    178(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TIP_APP_IN_SLR0                                                                         |                                                                       app__parameterized14 |   1317(0.04%) |   1317(0.04%) | 0(0.00%) |    0(0.00%) |   3377(0.05%) |   12(0.24%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       (TIP_APP_IN_SLR0)                                                                     |                                                                       app__parameterized14 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     36(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                                   pipeline |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    396(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                 logger__parameterized6_190 |    127(0.01%) |    127(0.01%) | 0(0.00%) |    0(0.00%) |    126(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                 logger__parameterized6_190 |     66(0.01%) |     66(0.01%) | 0(0.00%) |    0(0.00%) |     69(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                      ipbus_ram_wrapper_225 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                      ipbus_ram_wrapper_225 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_231 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                      ipbus_ram_wrapper_226 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                      ipbus_ram_wrapper_226 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_230 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                      ipbus_ram_wrapper__parameterized0_227 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                      ipbus_ram_wrapper__parameterized0_227 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized3_229 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized2_228 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                        ipbus_ctrlreg_v__parameterized1_191 |   1042(0.03%) |   1042(0.03%) | 0(0.00%) |    0(0.00%) |   2050(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                              pipeline__104 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                            sync_mt_fifo_v2__parameterized8 |    109(0.01%) |    109(0.01%) | 0(0.00%) |    0(0.00%) |    250(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                            sync_mt_fifo_v2__parameterized8 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                         sync_fifo_cntrl_v2__parameterized2 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     30(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                         sync_fifo_cntrl_v2__parameterized2 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized3_219 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized3_220 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized2_221 |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized2_222 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized2_223 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized6_224 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                     sync_fifo_cntrl_v2__parameterized2_201 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                     sync_fifo_cntrl_v2__parameterized2_201 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized3_213 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized3_214 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized2_215 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized2_216 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized2_217 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized6_218 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                     sync_fifo_cntrl_v2__parameterized2_202 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |     30(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                     sync_fifo_cntrl_v2__parameterized2_202 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                              reg_array__parameterized3_207 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized3_208 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized2_209 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                               sync_rd_side_roll_detect__parameterized2_210 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized2_211 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized6_212 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                     sync_fifo_cntrl_v2__parameterized2_203 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |     30(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                     sync_fifo_cntrl_v2__parameterized2_203 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                  reg_array__parameterized3 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                              reg_array__parameterized3_204 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                         fifo_addr_count_v2__parameterized2 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                   sync_rd_side_roll_detect__parameterized2 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                     fifo_addr_count_v2__parameterized2_205 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized6_206 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                 dp_bram_v2__parameterized3 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                         sync_bcid_rxtx_192 |     14(0.01%) |     14(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                              reg_array__parameterized0_197 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                              reg_array__parameterized0_198 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                              reg_array__parameterized0_199 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                              reg_array__parameterized0_200 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                              sync_sr2g_193 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                              pulse_cdc_194 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                              pulse_cdc_194 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                              syncreg_w_196 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                            sync_fsm_v4_195 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TIP_APU_IN_SLR0                                                                         |                                                      dummy_apu_with_ipbus__parameterized14 |    248(0.01%) |    248(0.01%) | 0(0.00%) |    0(0.00%) |    393(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TIP_APU_IN_SLR0)                                                                     |                                                      dummy_apu_with_ipbus__parameterized14 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |    233(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                        ipbus_ctrlreg_v__parameterized3_189 |    174(0.01%) |    174(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TOPOC_PU_APP_IN_SLR3                                                                    |                                                                        app__parameterized2 |   2297(0.07%) |   2297(0.07%) | 0(0.00%) |    0(0.00%) |   5571(0.08%) |   23(0.47%) |  2(0.02%) | 0(0.00%) |   0(0.00%) |
|       (TOPOC_PU_APP_IN_SLR3)                                                                |                                                                        app__parameterized2 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     70(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                   pipeline__parameterized3 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    915(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                     logger__parameterized2 |    135(0.01%) |    135(0.01%) | 0(0.00%) |    0(0.00%) |    166(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                     logger__parameterized2 |     80(0.01%) |     80(0.01%) | 0(0.00%) |    0(0.00%) |    101(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                      ipbus_ram_wrapper_182 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                      ipbus_ram_wrapper_182 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_188 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                      ipbus_ram_wrapper_183 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                      ipbus_ram_wrapper_183 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized2_187 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                      ipbus_ram_wrapper__parameterized0_184 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                      ipbus_ram_wrapper__parameterized0_184 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                   dual_port_bram_infer__parameterized3_186 |     29(0.01%) |     29(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                        ipbus_ctrlreg_v__parameterized2_185 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                         ipbus_ctrlreg_v__parameterized1_81 |   1212(0.04%) |   1212(0.04%) | 0(0.00%) |    0(0.00%) |   2053(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__53 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    444(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                                            sync_mt_fifo_v2 |    302(0.01%) |    302(0.01%) | 0(0.00%) |    0(0.00%) |    341(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                                            sync_mt_fifo_v2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                     sync_fifo_cntrl_v2_154 |     76(0.01%) |     76(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                     sync_fifo_cntrl_v2_154 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_176 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_177 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_178 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_179 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_180 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_181 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                     sync_fifo_cntrl_v2_155 |     81(0.01%) |     81(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                     sync_fifo_cntrl_v2_155 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_170 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_171 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_172 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_173 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_174 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_175 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                     sync_fifo_cntrl_v2_156 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                     sync_fifo_cntrl_v2_156 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_164 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_165 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_166 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_167 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_168 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_169 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                     sync_fifo_cntrl_v2_157 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                     sync_fifo_cntrl_v2_157 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_158 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_159 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_160 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_161 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_162 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_163 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                                 dp_bram_v2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                          sync_bcid_rxtx_82 |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                  mux41__parameterized2_149 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                              reg_array__parameterized0_150 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                              reg_array__parameterized0_151 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                              reg_array__parameterized0_152 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                              reg_array__parameterized0_153 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                               sync_sr2g_83 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__54 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                         sync_mt_fifo_v2__parameterized2_84 |    290(0.01%) |    290(0.01%) | 0(0.00%) |    0(0.00%) |    341(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                         sync_mt_fifo_v2__parameterized2_84 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                     sync_fifo_cntrl_v2_120 |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                     sync_fifo_cntrl_v2_120 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_143 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_144 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_145 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_146 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_147 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_148 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                     sync_fifo_cntrl_v2_121 |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                     sync_fifo_cntrl_v2_121 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_137 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_138 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_139 |     36(0.01%) |     36(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_140 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_141 |     29(0.01%) |     29(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_142 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                     sync_fifo_cntrl_v2_122 |     70(0.01%) |     70(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                     sync_fifo_cntrl_v2_122 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_131 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_132 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_133 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_134 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_135 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_136 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                     sync_fifo_cntrl_v2_123 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                     sync_fifo_cntrl_v2_123 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_125 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_126 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_127 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_128 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_129 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_130 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                             dp_bram_v2__parameterized0_124 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[1].sync_if.sync_sr                                                            |                                                                               sync_sr2g_85 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__55 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    408(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                         sync_mt_fifo_v2__parameterized2_86 |    292(0.01%) |    292(0.01%) | 0(0.00%) |    0(0.00%) |    342(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                         sync_mt_fifo_v2__parameterized2_86 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    129(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                      sync_fifo_cntrl_v2_91 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                      sync_fifo_cntrl_v2_91 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_114 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_115 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_116 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_117 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_118 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_119 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                      sync_fifo_cntrl_v2_92 |     76(0.01%) |     76(0.01%) | 0(0.00%) |    0(0.00%) |     50(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                      sync_fifo_cntrl_v2_92 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_108 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_109 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_110 |     35(0.01%) |     35(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_111 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_112 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_113 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                      sync_fifo_cntrl_v2_93 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                      sync_fifo_cntrl_v2_93 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                              reg_array_102 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                              reg_array_103 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                     fifo_addr_count_v2_104 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                               sync_rd_side_roll_detect_105 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_106 |     30(0.01%) |     30(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_107 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                      sync_fifo_cntrl_v2_94 |     71(0.01%) |     71(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                      sync_fifo_cntrl_v2_94 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                               reg_array_96 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                               reg_array_97 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                      fifo_addr_count_v2_98 |     27(0.01%) |     27(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                                sync_rd_side_roll_detect_99 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                     fifo_addr_count_v2_100 |     33(0.01%) |     33(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                             perf_count__parameterized2_101 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                              dp_bram_v2__parameterized0_95 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[2].sync_if.sync_sr                                                            |                                                                               sync_sr2g_87 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                               pulse_cdc_88 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                               pulse_cdc_88 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                               syncreg_w_90 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                             sync_fsm_v4_89 |     32(0.01%) |     32(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TOPOC_PU_APU_IN_SLR3                                                                    |                                                       dummy_apu_with_ipbus__parameterized2 |    454(0.01%) |    454(0.01%) | 0(0.00%) |    0(0.00%) |    523(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TOPOC_PU_APU_IN_SLR3)                                                                |                                                       dummy_apu_with_ipbus__parameterized2 |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |    363(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                         ipbus_ctrlreg_v__parameterized3_80 |    380(0.01%) |    380(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TOWER_MET_APP_IN_SLR1                                                                   |                                                                     app__parameterized8_50 |   1490(0.04%) |   1490(0.04%) | 0(0.00%) |    0(0.00%) |   3824(0.06%) |   12(0.24%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       (TOWER_MET_APP_IN_SLR1)                                                               |                                                                     app__parameterized8_50 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     41(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__75 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    216(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                    |                                                                     logger__parameterized6 |    126(0.01%) |    126(0.01%) | 0(0.00%) |    0(0.00%) |    140(0.01%) |    5(0.10%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                |                                                                     logger__parameterized6 |     66(0.01%) |     66(0.01%) | 0(0.00%) |    0(0.00%) |     75(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                            |                                                                          ipbus_ram_wrapper |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                        |                                                                          ipbus_ram_wrapper |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                    dual_port_bram_infer__parameterized2_79 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                        |                                                                       ipbus_ram_wrapper_78 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                    |                                                                       ipbus_ram_wrapper_78 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                       dual_port_bram_infer__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SRC_RAM                                                                             |                                                          ipbus_ram_wrapper__parameterized0 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (SRC_RAM)                                                                         |                                                          ipbus_ram_wrapper__parameterized0 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           memory                                                                            |                                                       dual_port_bram_infer__parameterized3 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    1(0.02%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         logger_registers                                                                    |                                                            ipbus_ctrlreg_v__parameterized2 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                             |                                                            ipbus_ctrlreg_v__parameterized1 |   1058(0.03%) |   1058(0.03%) | 0(0.00%) |    0(0.00%) |   2050(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                               |                                                                               pipeline__74 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    828(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                       |                                                            sync_mt_fifo_v2__parameterized2 |    268(0.01%) |    268(0.01%) | 0(0.00%) |    0(0.00%) |    474(0.01%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                   |                                                            sync_mt_fifo_v2__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    257(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                    |                                                                         sync_fifo_cntrl_v2 |     65(0.01%) |     65(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                |                                                                         sync_fifo_cntrl_v2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                               reg_array_72 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                               reg_array_73 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                      fifo_addr_count_v2_74 |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                                sync_rd_side_roll_detect_75 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                      fifo_addr_count_v2_76 |     31(0.01%) |     31(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                              perf_count__parameterized2_77 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                    |                                                                      sync_fifo_cntrl_v2_55 |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     56(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                |                                                                      sync_fifo_cntrl_v2_55 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                               reg_array_66 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                               reg_array_67 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                      fifo_addr_count_v2_68 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                                sync_rd_side_roll_detect_69 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                      fifo_addr_count_v2_70 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                              perf_count__parameterized2_71 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                    |                                                                      sync_fifo_cntrl_v2_56 |     64(0.01%) |     64(0.01%) | 0(0.00%) |    0(0.00%) |     51(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                |                                                                      sync_fifo_cntrl_v2_56 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                               reg_array_60 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                               reg_array_61 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                      fifo_addr_count_v2_62 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                                sync_rd_side_roll_detect_63 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                      fifo_addr_count_v2_64 |     34(0.01%) |     34(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                              perf_count__parameterized2_65 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                    |                                                                      sync_fifo_cntrl_v2_57 |     62(0.01%) |     62(0.01%) | 0(0.00%) |    0(0.00%) |     55(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                |                                                                      sync_fifo_cntrl_v2_57 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                               |                                                                                  reg_array |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                               |                                                                               reg_array_58 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                     |                                                                         fifo_addr_count_v2 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                    |                                                                   sync_rd_side_roll_detect |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                     |                                                                      fifo_addr_count_v2_59 |     28(0.01%) |     28(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                  |                                                                 perf_count__parameterized2 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                          |                                                                 dp_bram_v2__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    7(0.14%) |  1(0.01%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_bcid_transceiver                                              |                                                                             sync_bcid_rxtx |     13(0.01%) |     13(0.01%) | 0(0.00%) |    0(0.00%) |     48(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_out_mux                                                                        |                                                                      mux41__parameterized2 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg0                                                                           |                                                                  reg_array__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg1                                                                           |                                                               reg_array__parameterized0_52 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg2                                                                           |                                                               reg_array__parameterized0_53 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bcid_reg3                                                                           |                                                               reg_array__parameterized0_54 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mainfor[0].sync_if.sync_sr                                                            |                                                                                  sync_sr2g |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       pulse_we                                                                              |                                                                                  pulse_cdc |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                          |                                                                                  pulse_cdc |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                                  syncreg_w |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sync_inst                                                                             |                                                                                sync_fsm_v4 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     TOWER_MET_APU_IN_SLR1                                                                   |                                                    dummy_apu_with_ipbus__parameterized8_51 |    236(0.01%) |    236(0.01%) | 0(0.00%) |    0(0.00%) |    337(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (TOWER_MET_APU_IN_SLR1)                                                               |                                                    dummy_apu_with_ipbus__parameterized8_51 |     72(0.01%) |     72(0.01%) | 0(0.00%) |    0(0.00%) |    177(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       n_debug.apu_registers                                                                 |                                                            ipbus_ctrlreg_v__parameterized3 |    164(0.01%) |    164(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     destination_tgen_IN_SLR0                                                                |                                                                 ipbus_tgen__parameterized9 |   1024(0.03%) |   1024(0.03%) | 0(0.00%) |    0(0.00%) |   2526(0.04%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (destination_tgen_IN_SLR0)                                                            |                                                                 ipbus_tgen__parameterized9 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_input_pipeline                                                          |                                                                               pipeline__14 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    396(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                         |                                                                               pipeline__15 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       TGEN_VERILOG                                                                          |                                                                       tgen__parameterized4 |    109(0.01%) |    109(0.01%) | 0(0.00%) |    0(0.00%) |     52(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       mem                                                                                   |                                                                 dp_ram_ipb__parameterized1 |     85(0.01%) |     85(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (mem)                                                                               |                                                                 dp_ram_ipb__parameterized1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         memory                                                                              |                                                       dual_port_bram_infer__parameterized1 |     82(0.01%) |     82(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    4(0.08%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                      |                                                                             syncreg_w_3159 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                       |                                                            perf_count__parameterized4_3157 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sim.tgen_registers                                                                    |                                                       ipbus_ctrlreg_v__parameterized1_3158 |    822(0.02%) |    822(0.02%) | 0(0.00%) |    0(0.00%) |   2048(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     vio_rst_ctrl_IN_SLR0                                                                    |                                                                                      vio_0 |    754(0.02%) |    754(0.02%) | 0(0.00%) |    0(0.00%) |   1100(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       inst                                                                                  |                                                                 vio_0_axis_vio_v1_0_12_vio |    754(0.02%) |    754(0.02%) | 0(0.00%) |    0(0.00%) |   1100(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (inst)                                                                              |                                                                 vio_0_axis_vio_v1_0_12_vio |    119(0.01%) |    119(0.01%) | 0(0.00%) |    0(0.00%) |    228(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         axis_dbg_stub                                                                       |                                                   vio_0_axis_dbg_stub_v1_0_1_axis_dbg_stub |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         probe_out_all_inst                                                                  |                                                       vio_0_axis_vio_v1_0_12_probe_out_all |    179(0.01%) |    179(0.01%) | 0(0.00%) |    0(0.00%) |    242(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (probe_out_all_inst)                                                              |                                                       vio_0_axis_vio_v1_0_12_probe_out_all |    149(0.01%) |    149(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           G_PROBE_OUT[0].probe_out_all_sync                                                 |                                        vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__xdcDup__1 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (G_PROBE_OUT[0].probe_out_all_sync)                                             |                                        vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__xdcDup__1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             genblk1_0.xpm_cdc_handshake_inst                                                |                                                         vio_0_xpm_cdc_handshake__xdcDup__1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (genblk1_0.xpm_cdc_handshake_inst)                                            |                                                         vio_0_xpm_cdc_handshake__xdcDup__1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_single_dest2src_inst                                                  |                                                                    vio_0_xpm_cdc_single__7 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_single_src2dest_inst                                                  |                                                                    vio_0_xpm_cdc_single__6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           G_PROBE_OUT[0].probe_out_one_inst                                                 |                                        vio_0_axis_vio_v1_0_12_reg_array__parameterized0__1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           G_PROBE_OUT[1].probe_out_all_sync                                                 |                                        vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__xdcDup__2 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (G_PROBE_OUT[1].probe_out_all_sync)                                             |                                        vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__xdcDup__2 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             genblk1_0.xpm_cdc_handshake_inst                                                |                                                         vio_0_xpm_cdc_handshake__xdcDup__2 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (genblk1_0.xpm_cdc_handshake_inst)                                            |                                                         vio_0_xpm_cdc_handshake__xdcDup__2 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_single_dest2src_inst                                                  |                                                                    vio_0_xpm_cdc_single__9 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_single_src2dest_inst                                                  |                                                                    vio_0_xpm_cdc_single__8 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           G_PROBE_OUT[1].probe_out_one_inst                                                 |                                        vio_0_axis_vio_v1_0_12_reg_array__parameterized0__2 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           G_PROBE_OUT[2].probe_out_all_sync                                                 |                                                   vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (G_PROBE_OUT[2].probe_out_all_sync)                                             |                                                   vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             genblk1_0.xpm_cdc_handshake_inst                                                |                                                                    vio_0_xpm_cdc_handshake |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (genblk1_0.xpm_cdc_handshake_inst)                                            |                                                                    vio_0_xpm_cdc_handshake |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_single_dest2src_inst                                                  |                                                                       vio_0_xpm_cdc_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_single_src2dest_inst                                                  |                                                                   vio_0_xpm_cdc_single__10 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           G_PROBE_OUT[2].probe_out_one_inst                                                 |                                        vio_0_axis_vio_v1_0_12_reg_array__parameterized0__3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           commit_sync_inst                                                                  |                        vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1__xdcDup__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             genblk1_3.xpm_cdc_single_inst                                                   |                                                    vio_0_xpm_cdc_single__parameterized0__3 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           reset_sync_inst                                                                   |                                   vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (reset_sync_inst)                                                               |                                   vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             genblk1.xpm_cdc_async_rst_inst                                                  |                                                                    vio_0_xpm_cdc_async_rst |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         u_clk_status                                                                        |                                                          vio_0_axis_vio_v1_0_12_clk_status |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (u_clk_status)                                                                    |                                                          vio_0_axis_vio_v1_0_12_clk_status |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_flag_0_sync_inst                                                             |                        vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1__xdcDup__2 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_flag_0_sync_inst)                                                         |                        vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1__xdcDup__2 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             genblk1_3.xpm_cdc_single_inst                                                   |                                                       vio_0_xpm_cdc_single__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           des_flag_0_sync_inst                                                              |                                   vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (des_flag_0_sync_inst)                                                          |                                   vio_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             genblk1_3.xpm_cdc_single_inst                                                   |                                                    vio_0_xpm_cdc_single__parameterized0__4 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         u_core_ctrl_reg                                                                     |                                           vio_0_axis_vio_v1_0_12_reg_array__parameterized0 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         u_core_info_reg                                                                     |                                        vio_0_axis_vio_v1_0_12_reg_array__parameterized1__1 |    220(0.01%) |    220(0.01%) | 0(0.00%) |    0(0.00%) |    240(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         u_core_probe_in_width_reg                                                           |                                                           vio_0_axis_vio_v1_0_12_reg_array |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     65(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         u_core_probe_no                                                                     |                                           vio_0_axis_vio_v1_0_12_reg_array__parameterized1 |    218(0.01%) |    218(0.01%) | 0(0.00%) |    0(0.00%) |    240(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|   axi_dbg_hub                                                                               |                                                                  axi_dbg_hub_axi_dbg_hub_0 |   1107(0.03%) |   1107(0.03%) | 0(0.00%) |    0(0.00%) |   1096(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     (axi_dbg_hub)                                                                           |                                                                  axi_dbg_hub_axi_dbg_hub_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     inst                                                                                    |                                                      axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub |   1107(0.03%) |   1107(0.03%) | 0(0.00%) |    0(0.00%) |   1096(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       sv_top_inst                                                                           |                                        axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_sv_top |   1107(0.03%) |   1107(0.03%) | 0(0.00%) |    0(0.00%) |   1096(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         core_inst                                                                           |                                          axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_core |   1107(0.03%) |   1107(0.03%) | 0(0.00%) |    0(0.00%) |   1096(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (core_inst)                                                                       |                                          axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_core |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           dbg_core_intf_inst                                                                |                                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_core_intf |    489(0.01%) |    489(0.01%) | 0(0.00%) |    0(0.00%) |    416(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (dbg_core_intf_inst)                                                            |                                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_core_intf |     60(0.01%) |     60(0.01%) | 0(0.00%) |    0(0.00%) |    175(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             dbg_core_axis_intf0_inst                                                        |                                 axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_stream_engine |     62(0.01%) |     62(0.01%) | 0(0.00%) |    0(0.00%) |     47(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_rx_stream_inst                                                       |                                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_rx_engine |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_tx_stream_inst                                                       |                                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_tx_engine |     51(0.01%) |     51(0.01%) | 0(0.00%) |    0(0.00%) |     40(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             dbg_core_axis_intf1_inst                                                        |                 axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_stream_engine__parameterized0 |     62(0.01%) |     62(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_rx_stream_inst                                                       |                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_rx_engine__parameterized0 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_tx_stream_inst                                                       |                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_tx_engine__parameterized0 |     51(0.01%) |     51(0.01%) | 0(0.00%) |    0(0.00%) |     39(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             dbg_core_axis_intf2_inst                                                        |                 axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_stream_engine__parameterized1 |     62(0.01%) |     62(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_rx_stream_inst                                                       |                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_rx_engine__parameterized1 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_tx_stream_inst                                                       |                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_tx_engine__parameterized1 |     51(0.01%) |     51(0.01%) | 0(0.00%) |    0(0.00%) |     39(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             dbg_core_axis_intf3_inst                                                        |                 axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_stream_engine__parameterized2 |     63(0.01%) |     63(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_rx_stream_inst                                                       |                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_rx_engine__parameterized2 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_tx_stream_inst                                                       |                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_tx_engine__parameterized2 |     51(0.01%) |     51(0.01%) | 0(0.00%) |    0(0.00%) |     39(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             dbg_core_axis_intf4_inst                                                        |                 axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_stream_engine__parameterized3 |     62(0.01%) |     62(0.01%) | 0(0.00%) |    0(0.00%) |     46(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_rx_stream_inst                                                       |                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_rx_engine__parameterized3 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               dbg_core_tx_stream_inst                                                       |                     axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_tx_engine__parameterized3 |     51(0.01%) |     51(0.01%) | 0(0.00%) |    0(0.00%) |     39(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             dbg_core_rx_ch_sel_inst                                                         |                                        axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_ch_sel |    112(0.01%) |    112(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             dbg_core_tx_ch_sel_inst                                                         |                                      axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_ch_sel_0 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           dbg_core_reg_intf_inst                                                            |                                      axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_reg_intf |    617(0.02%) |    617(0.02%) | 0(0.00%) |    0(0.00%) |    680(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|   axi_noc                                                                                   |                                                                   design_axi_noc_axi_noc_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     inst                                                                                    |                                                           design_axi_noc_axi_noc_0_bd_1091 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (inst)                                                                                |                                                           design_axi_noc_axi_noc_0_bd_1091 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       M00_AXI_nsu                                                                           |                                             design_axi_noc_axi_noc_0_bd_1091_M00_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         bd_1091_M00_AXI_nsu_0_top_INST                                                      |                                         design_axi_noc_axi_noc_0_bd_1091_M00_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|   proc_sys_reset                                                                            |                                                            proc_sys_reset_proc_sys_reset_0 |     22(0.01%) |     21(0.01%) | 0(0.00%) |    1(0.01%) |     35(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     U0                                                                                      |                                             proc_sys_reset_proc_sys_reset_0_proc_sys_reset |     22(0.01%) |     21(0.01%) | 0(0.00%) |    1(0.01%) |     35(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (U0)                                                                                  |                                             proc_sys_reset_proc_sys_reset_0_proc_sys_reset |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       EXT_LPF                                                                               |                                                        proc_sys_reset_proc_sys_reset_0_lpf |      5(0.01%) |      4(0.01%) | 0(0.00%) |    1(0.01%) |     19(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (EXT_LPF)                                                                           |                                                        proc_sys_reset_proc_sys_reset_0_lpf |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         ACTIVE_LOW_AUX.ACT_LO_AUX                                                           |                                                   proc_sys_reset_proc_sys_reset_0_cdc_sync |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         ACTIVE_LOW_EXT.ACT_LO_EXT                                                           |                                                 proc_sys_reset_proc_sys_reset_0_cdc_sync_0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       SEQ                                                                                   |                                               proc_sys_reset_proc_sys_reset_0_sequence_psr |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (SEQ)                                                                               |                                               proc_sys_reset_proc_sys_reset_0_sequence_psr |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         SEQ_COUNTER                                                                         |                                                    proc_sys_reset_proc_sys_reset_0_upcnt_n |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|   vpk180_bd                                                                                 |                                                                         vpk180_ipb_wrapper |  14766(0.44%) |  13703(0.41%) | 0(0.00%) | 1063(0.06%) |  28076(0.42%) |   44(0.89%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     (vpk180_bd)                                                                             |                                                                         vpk180_ipb_wrapper |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|     vpk180_ipb_i                                                                            |                                                                                 vpk180_ipb |  14751(0.44%) |  13688(0.41%) | 0(0.00%) | 1063(0.06%) |  28076(0.42%) |   44(0.89%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       (vpk180_ipb_i)                                                                        |                                                                                 vpk180_ipb |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       axi_bram_ctrl_1                                                                       |                                                               vpk180_ipb_axi_bram_ctrl_1_0 |    405(0.01%) |    403(0.01%) | 0(0.00%) |    2(0.01%) |    308(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         (axi_bram_ctrl_1)                                                                   |                                                               vpk180_ipb_axi_bram_ctrl_1_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                 vpk180_ipb_axi_bram_ctrl_1_0_axi_bram_ctrl |    405(0.01%) |    403(0.01%) | 0(0.00%) |    2(0.01%) |    308(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gext_inst.abcv4_0_ext_inst                                                        |                                             vpk180_ipb_axi_bram_ctrl_1_0_axi_bram_ctrl_top |    405(0.01%) |    403(0.01%) | 0(0.00%) |    2(0.01%) |    308(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             GEN_AXI4.I_FULL_AXI                                                             |                                                      vpk180_ipb_axi_bram_ctrl_1_0_full_axi |    405(0.01%) |    403(0.01%) | 0(0.00%) |    2(0.01%) |    308(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_RD_CHNL                                                                     |                                                       vpk180_ipb_axi_bram_ctrl_1_0_rd_chnl |    240(0.01%) |    240(0.01%) | 0(0.00%) |    0(0.00%) |    178(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_RD_CHNL)                                                                 |                                                       vpk180_ipb_axi_bram_ctrl_1_0_rd_chnl |    187(0.01%) |    187(0.01%) | 0(0.00%) |    0(0.00%) |    165(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 GEN_NO_RD_CMD_OPT.I_WRAP_BRST                                               |                                                   vpk180_ipb_axi_bram_ctrl_1_0_wrap_brst_0 |     54(0.01%) |     54(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               I_WR_CHNL                                                                     |                                                       vpk180_ipb_axi_bram_ctrl_1_0_wr_chnl |    165(0.01%) |    163(0.01%) | 0(0.00%) |    2(0.01%) |    130(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (I_WR_CHNL)                                                                 |                                                       vpk180_ipb_axi_bram_ctrl_1_0_wr_chnl |     88(0.01%) |     88(0.01%) | 0(0.00%) |    0(0.00%) |    112(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 BID_FIFO                                                                    |                                                      vpk180_ipb_axi_bram_ctrl_1_0_SRL_FIFO |     27(0.01%) |     25(0.01%) | 0(0.00%) |    2(0.01%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 I_WRAP_BRST                                                                 |                                                     vpk180_ipb_axi_bram_ctrl_1_0_wrap_brst |     52(0.01%) |     52(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       axi_bram_ctrl_1_bram                                                                  |                                                          vpk180_ipb_axi_bram_ctrl_1_bram_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         inst                                                                                |                                      vpk180_ipb_axi_bram_ctrl_1_bram_0_emb_mem_gen_v1_0_10 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_xpm.gen_base.xpm_memory_base_inst                                             |                                          vpk180_ipb_axi_bram_ctrl_1_bram_0_xpm_memory_base |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    2(0.04%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       axi_firewall_slr1                                                                     |                                                             vpk180_ipb_axi_firewall_slr1_0 |   1358(0.04%) |   1314(0.04%) | 0(0.00%) |   44(0.01%) |   2799(0.04%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         inst                                                                                |                                     vpk180_ipb_axi_firewall_slr1_0_axi_firewall_v1_2_8_top |   1358(0.04%) |   1314(0.04%) | 0(0.00%) |   44(0.01%) |   2799(0.04%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (inst)                                                                            |                                     vpk180_ipb_axi_firewall_slr1_0_axi_firewall_v1_2_8_top |    426(0.01%) |    426(0.01%) | 0(0.00%) |    0(0.00%) |    727(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_areset_delay_inst                                                 |                                           vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_async_rst |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_aresetn_inst                                                      |                                        vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_async_rst__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_delay_inst                                                        |                vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_handshake__parameterized1__xdcDup__1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_ctl_cdc.cdc_delay_inst)                                                    |                vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_handshake__parameterized1__xdcDup__1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     66(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_dest2src_inst                                                    |                                           vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_single__9 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_src2dest_inst                                                    |                                           vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_single__8 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_prescaler_inst                                                    |                           vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_handshake__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_ctl_cdc.cdc_prescaler_inst)                                                |                           vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_handshake__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     66(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_dest2src_inst                                                    |                                          vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_single__11 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_src2dest_inst                                                    |                                          vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_single__10 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_read_inst                                                         |                                           vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |    366(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_ctl_cdc.cdc_read_inst)                                                     |                                           vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |    358(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_dest2src_inst                                                    |                                              vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_src2dest_inst                                                    |                                          vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_single__14 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_status_inst                                                       |                                        vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_array_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    156(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_write_inst                                                        |                           vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_handshake__parameterized0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |    214(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_ctl_cdc.cdc_write_inst)                                                    |                           vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_handshake__parameterized0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |    206(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_dest2src_inst                                                    |                                          vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_single__13 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_src2dest_inst                                                    |                                          vpk180_ipb_axi_firewall_slr1_0_xpm_cdc_single__12 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.checks                                                                     |                               vpk180_ipb_axi_firewall_slr1_0_axi_firewall_v1_2_8_checks_mi |    385(0.01%) |    349(0.01%) | 0(0.00%) |   36(0.01%) |    221(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_mi.checks)                                                                 |                               vpk180_ipb_axi_firewall_slr1_0_axi_firewall_v1_2_8_checks_mi |    274(0.01%) |    274(0.01%) | 0(0.00%) |    0(0.00%) |    181(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_read_checks.gen_rthread_loop[0].rlen_queue                                  |         vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__1 |     23(0.01%) |     15(0.01%) | 0(0.00%) |    8(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_read_checks.gen_rthread_loop[0].rlen_queue)                              |         vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__1 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_35 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_36 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_37 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_38 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[4].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_39 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[5].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_40 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[6].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_41 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[7].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_42 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_read_checks.gen_rthread_loop[1].rlen_queue                                  |         vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__2 |     24(0.01%) |     16(0.01%) | 0(0.00%) |    8(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_read_checks.gen_rthread_loop[1].rlen_queue)                              |         vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__2 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_27 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_28 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_29 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_30 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[4].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_31 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[5].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_32 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[6].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_33 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[7].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_34 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_read_checks.gen_rthread_loop[2].rlen_queue                                  |         vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__3 |     24(0.01%) |     16(0.01%) | 0(0.00%) |    8(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_read_checks.gen_rthread_loop[2].rlen_queue)                              |         vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__3 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_19 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_20 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_21 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_22 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[4].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_23 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[5].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_24 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[6].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_25 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[7].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_26 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_read_checks.gen_rthread_loop[3].rlen_queue                                  |            vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0 |     23(0.01%) |     15(0.01%) | 0(0.00%) |    8(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_read_checks.gen_rthread_loop[3].rlen_queue)                              |            vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_11 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_12 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_13 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_14 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[4].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_15 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[5].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_16 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[6].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_17 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[7].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_18 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_write_checks.awid_queue                                                     |            vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized1 |     17(0.01%) |     13(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_write_checks.awid_queue)                                                 |            vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized1 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                      vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                    vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_8 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                    vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_9 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl__parameterized0_10 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.gen_read.r_threadcam                                                       |                               vpk180_ipb_axi_firewall_slr1_0_axi_firewall_v1_2_8_threadcam |    151(0.01%) |    147(0.01%) | 0(0.00%) |    4(0.01%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_mi.gen_read.r_threadcam)                                                   |                               vpk180_ipb_axi_firewall_slr1_0_axi_firewall_v1_2_8_threadcam |    135(0.01%) |    135(0.01%) | 0(0.00%) |    0(0.00%) |     64(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_cam.allocate_queue                                                          |                            vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo |     16(0.01%) |     12(0.01%) | 0(0.00%) |    4(0.01%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_cam.allocate_queue)                                                      |                            vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl_4 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl_5 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl_6 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl_7 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.gen_write.w_threadcam                                                      |                             vpk180_ipb_axi_firewall_slr1_0_axi_firewall_v1_2_8_threadcam_0 |    146(0.01%) |    142(0.01%) | 0(0.00%) |    4(0.01%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_mi.gen_write.w_threadcam)                                                  |                             vpk180_ipb_axi_firewall_slr1_0_axi_firewall_v1_2_8_threadcam_0 |    129(0.01%) |    129(0.01%) | 0(0.00%) |    0(0.00%) |     64(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_cam.allocate_queue                                                          |                         vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__1 |     17(0.01%) |     13(0.01%) | 0(0.00%) |    4(0.01%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_cam.allocate_queue)                                                      |                         vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axic_reg_srl_fifo__1 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                                      vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl_1 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl_2 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_srl_rtl_3 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_ar_reg                                                                   |             vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall__parameterized0__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_aw_reg                                                                   |             vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall__parameterized0__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_b_reg                                                                    |                             vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall__5 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_r_reg                                                                    |                             vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall__4 |     41(0.01%) |     41(0.01%) | 0(0.00%) |    0(0.00%) |    134(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_w_reg                                                                    |                vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_ar_reg                                                                   |                             vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall__6 |     56(0.01%) |     56(0.01%) | 0(0.00%) |    0(0.00%) |    194(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_aw_reg                                                                   |                                vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall |     56(0.01%) |     56(0.01%) | 0(0.00%) |    0(0.00%) |    194(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_b_reg                                                                    |                             vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall__3 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_r_reg                                                                    |                             vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall__2 |     43(0.01%) |     43(0.01%) | 0(0.00%) |    0(0.00%) |    140(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_w_reg                                                                    |                             vpk180_ipb_axi_firewall_slr1_0_sc_util_v1_0_4_axi_reg_stall__1 |     43(0.01%) |     43(0.01%) | 0(0.00%) |    0(0.00%) |    136(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       axi_firewall_slr2                                                                     |                                                             vpk180_ipb_axi_firewall_slr2_0 |   1351(0.04%) |   1307(0.04%) | 0(0.00%) |   44(0.01%) |   2799(0.04%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         inst                                                                                |                                     vpk180_ipb_axi_firewall_slr2_0_axi_firewall_v1_2_8_top |   1351(0.04%) |   1307(0.04%) | 0(0.00%) |   44(0.01%) |   2799(0.04%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (inst)                                                                            |                                     vpk180_ipb_axi_firewall_slr2_0_axi_firewall_v1_2_8_top |    423(0.01%) |    423(0.01%) | 0(0.00%) |    0(0.00%) |    727(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_areset_delay_inst                                                 |                                           vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_async_rst |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_aresetn_inst                                                      |                                        vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_async_rst__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_delay_inst                                                        |                vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_handshake__parameterized1__xdcDup__1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_ctl_cdc.cdc_delay_inst)                                                    |                vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_handshake__parameterized1__xdcDup__1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     66(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_dest2src_inst                                                    |                                           vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_single__9 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_src2dest_inst                                                    |                                           vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_single__8 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_prescaler_inst                                                    |                           vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_handshake__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_ctl_cdc.cdc_prescaler_inst)                                                |                           vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_handshake__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     66(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_dest2src_inst                                                    |                                          vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_single__11 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_src2dest_inst                                                    |                                          vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_single__10 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_read_inst                                                         |                                           vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |    366(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_ctl_cdc.cdc_read_inst)                                                     |                                           vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |    358(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_dest2src_inst                                                    |                                              vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_src2dest_inst                                                    |                                          vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_single__14 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_status_inst                                                       |                                        vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_array_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |    156(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_ctl_cdc.cdc_write_inst                                                        |                           vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_handshake__parameterized0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |    214(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_ctl_cdc.cdc_write_inst)                                                    |                           vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_handshake__parameterized0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |    206(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_dest2src_inst                                                    |                                          vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_single__13 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             xpm_cdc_single_src2dest_inst                                                    |                                          vpk180_ipb_axi_firewall_slr2_0_xpm_cdc_single__12 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.checks                                                                     |                               vpk180_ipb_axi_firewall_slr2_0_axi_firewall_v1_2_8_checks_mi |    387(0.01%) |    351(0.01%) | 0(0.00%) |   36(0.01%) |    221(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_mi.checks)                                                                 |                               vpk180_ipb_axi_firewall_slr2_0_axi_firewall_v1_2_8_checks_mi |    273(0.01%) |    273(0.01%) | 0(0.00%) |    0(0.00%) |    181(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_read_checks.gen_rthread_loop[0].rlen_queue                                  |         vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__1 |     25(0.01%) |     17(0.01%) | 0(0.00%) |    8(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_read_checks.gen_rthread_loop[0].rlen_queue)                              |         vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__1 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_35 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_36 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_37 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_38 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[4].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_39 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[5].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_40 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[6].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_41 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[7].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_42 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_read_checks.gen_rthread_loop[1].rlen_queue                                  |         vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__2 |     26(0.01%) |     18(0.01%) | 0(0.00%) |    8(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_read_checks.gen_rthread_loop[1].rlen_queue)                              |         vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__2 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_27 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_28 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_29 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_30 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[4].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_31 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[5].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_32 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[6].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_33 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[7].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_34 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_read_checks.gen_rthread_loop[2].rlen_queue                                  |         vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__3 |     23(0.01%) |     15(0.01%) | 0(0.00%) |    8(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_read_checks.gen_rthread_loop[2].rlen_queue)                              |         vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0__3 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_19 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_20 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_21 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_22 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[4].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_23 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[5].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_24 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[6].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_25 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[7].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_26 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_read_checks.gen_rthread_loop[3].rlen_queue                                  |            vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0 |     25(0.01%) |     17(0.01%) | 0(0.00%) |    8(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_read_checks.gen_rthread_loop[3].rlen_queue)                              |            vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized0 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_11 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_12 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_13 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_14 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[4].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_15 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[5].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_16 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[6].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_17 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[7].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_18 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_write_checks.awid_queue                                                     |            vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized1 |     17(0.01%) |     13(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_write_checks.awid_queue)                                                 |            vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__parameterized1 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                      vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                    vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_8 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                    vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_9 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                   vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl__parameterized0_10 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.gen_read.r_threadcam                                                       |                               vpk180_ipb_axi_firewall_slr2_0_axi_firewall_v1_2_8_threadcam |    149(0.01%) |    145(0.01%) | 0(0.00%) |    4(0.01%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_mi.gen_read.r_threadcam)                                                   |                               vpk180_ipb_axi_firewall_slr2_0_axi_firewall_v1_2_8_threadcam |    133(0.01%) |    133(0.01%) | 0(0.00%) |    0(0.00%) |     64(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_cam.allocate_queue                                                          |                            vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo |     17(0.01%) |     13(0.01%) | 0(0.00%) |    4(0.01%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_cam.allocate_queue)                                                      |                            vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl_4 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl_5 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl_6 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl_7 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.gen_write.w_threadcam                                                      |                             vpk180_ipb_axi_firewall_slr2_0_axi_firewall_v1_2_8_threadcam_0 |    143(0.01%) |    139(0.01%) | 0(0.00%) |    4(0.01%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (gen_mi.gen_write.w_threadcam)                                                  |                             vpk180_ipb_axi_firewall_slr2_0_axi_firewall_v1_2_8_threadcam_0 |    127(0.01%) |    127(0.01%) | 0(0.00%) |    0(0.00%) |     64(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             gen_cam.allocate_queue                                                          |                         vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__1 |     16(0.01%) |     12(0.01%) | 0(0.00%) |    4(0.01%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (gen_cam.allocate_queue)                                                      |                         vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axic_reg_srl_fifo__1 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[0].srl_nx1                                                           |                                      vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[1].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl_1 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[2].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl_2 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               gen_srls[3].srl_nx1                                                           |                                    vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_srl_rtl_3 |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_ar_reg                                                                   |             vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall__parameterized0__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_aw_reg                                                                   |             vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall__parameterized0__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_b_reg                                                                    |                             vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall__5 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_r_reg                                                                    |                             vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall__4 |     40(0.01%) |     40(0.01%) | 0(0.00%) |    0(0.00%) |    134(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.m_w_reg                                                                    |                vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_ar_reg                                                                   |                             vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall__6 |     56(0.01%) |     56(0.01%) | 0(0.00%) |    0(0.00%) |    194(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_aw_reg                                                                   |                                vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall |     56(0.01%) |     56(0.01%) | 0(0.00%) |    0(0.00%) |    194(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_b_reg                                                                    |                             vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall__3 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_r_reg                                                                    |                             vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall__2 |     44(0.01%) |     44(0.01%) | 0(0.00%) |    0(0.00%) |    140(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           gen_mi.s_w_reg                                                                    |                             vpk180_ipb_axi_firewall_slr2_0_sc_util_v1_0_4_axi_reg_stall__1 |     41(0.01%) |     41(0.01%) | 0(0.00%) |    0(0.00%) |    136(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       axi_noc_0                                                                             |                                                                     vpk180_ipb_axi_noc_0_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         inst                                                                                |                                                             vpk180_ipb_axi_noc_0_0_bd_6a49 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (inst)                                                                            |                                                             vpk180_ipb_axi_noc_0_0_bd_6a49 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           M00_AXI_nsu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M00_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (M00_AXI_nsu)                                                                   |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M00_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_M00_AXI_nsu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_M00_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           M01_AXI_nsu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M01_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (M01_AXI_nsu)                                                                   |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M01_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_M01_AXI_nsu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_M01_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           M02_AXI_nsu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M02_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (M02_AXI_nsu)                                                                   |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M02_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_M02_AXI_nsu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_M02_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           M03_AXI_nsu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M03_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (M03_AXI_nsu)                                                                   |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M03_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_M03_AXI_nsu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_M03_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           M04_AXI_nsu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M04_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_M04_AXI_nsu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_M04_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           M05_AXI_nsu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_M05_AXI_nsu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_M05_AXI_nsu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_M05_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           MC0_ddrc                                                                          |                                                  vpk180_ipb_axi_noc_0_0_bd_6a49_MC0_ddrc_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                          vpk180_ipb_axi_noc_0_0_bd_6a49_MC0_ddrc_0_wrapper |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               noc_ddr4_phy                                                                  |                                                                     bd_6a49_MC0_ddrc_0_phy |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst                                                                        |                                                             bd_6a49_MC0_ddrc_0_phy_wrapper |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (inst)                                                                    |                                                             bd_6a49_MC0_ddrc_0_phy_wrapper |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   BANK_WRAPPER_INST0                                                        |                                   advanced_io_wizard_phy_v1_0_bank_wrapper__parameterized1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   BANK_WRAPPER_INST1                                                        |                                   advanced_io_wizard_phy_v1_0_bank_wrapper__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   BANK_WRAPPER_INST2                                                        |                                                   advanced_io_wizard_phy_v1_0_bank_wrapper |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           S00_AXI_nmu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_S00_AXI_nmu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_S00_AXI_nmu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_S00_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           S01_AXI_nmu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_S01_AXI_nmu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_S01_AXI_nmu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_S01_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           S02_AXI_nmu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_S02_AXI_nmu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_S02_AXI_nmu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_S02_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           S03_AXI_nmu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_S03_AXI_nmu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_S03_AXI_nmu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_S03_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           S04_AXI_rpu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_S04_AXI_rpu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_S04_AXI_rpu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_S04_AXI_rpu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           S05_AXI_nmu                                                                       |                                               vpk180_ipb_axi_noc_0_0_bd_6a49_S05_AXI_nmu_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             bd_6a49_S05_AXI_nmu_0_top_INST                                                  |                                           vpk180_ipb_axi_noc_0_0_bd_6a49_S05_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           const_0                                                                           |                                                   vpk180_ipb_axi_noc_0_0_bd_6a49_const_0_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       axis_ila_alone                                                                        |                                                                vpk180_ipb_axis_ila_alone_0 |   2572(0.08%) |   2355(0.07%) | 0(0.00%) |  217(0.01%) |   4825(0.07%) |    9(0.18%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                        vpk180_ipb_axis_ila_alone_0_bd_cd51 |   2572(0.08%) |   2355(0.07%) | 0(0.00%) |  217(0.01%) |   4825(0.07%) |    9(0.18%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (U0)                                                                              |                                                        vpk180_ipb_axis_ila_alone_0_bd_cd51 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_cap_ctrl                                                                     |                                        vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_cap_ctrl_0 |    133(0.01%) |    133(0.01%) | 0(0.00%) |    0(0.00%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                             vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |    133(0.01%) |    133(0.01%) | 0(0.00%) |    0(0.00%) |     74(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                             vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |     61(0.01%) |     61(0.01%) | 0(0.00%) |    0(0.00%) |     43(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_1                                                                      |                                     vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_case1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_2                                                                      |                                     vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_case2 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_3                                                                      |                                     vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_case3 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_4                                                                      |                                     vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_case4 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_5                                                                      |                                     vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_case5 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_6                                                                      |                                     vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_case6 |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_7                                                                      |                                     vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_case7 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_8                                                                      |                                     vpk180_ipb_axis_ila_alone_0_axis_cap_ctrl_v1_0_1_case8 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_stub                                                                     |                                        vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_dbg_stub_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                             vpk180_ipb_axis_ila_alone_0_axis_dbg_stub_v1_0_1_axis_dbg_stub |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_2                                                                   |                                      vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_dbg_sync_2_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                             vpk180_ipb_axis_ila_alone_0_axis_dbg_sync_v1_0_1_axis_dbg_sync |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_3.xpm_cdc_single_inst                                                 |                                                 vpk180_ipb_axis_ila_alone_0_xpm_cdc_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_3                                                                   |                                      vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_dbg_sync_3_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |  vpk180_ipb_axis_ila_alone_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0__xdcDup__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                                           vpk180_ipb_axis_ila_alone_0_xpm_cdc_array_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_4                                                                   |                                      vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_dbg_sync_4_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |             vpk180_ipb_axis_ila_alone_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                                        vpk180_ipb_axis_ila_alone_0_xpm_cdc_array_single__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_5                                                                   |                                      vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_dbg_sync_5_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |             vpk180_ipb_axis_ila_alone_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                           vpk180_ipb_axis_ila_alone_0_xpm_cdc_array_single__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_6                                                                   |                                      vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_dbg_sync_6_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |             vpk180_ipb_axis_ila_alone_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1.xpm_cdc_async_rst_inst                                                |                                              vpk180_ipb_axis_ila_alone_0_xpm_cdc_async_rst |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_ila_intf                                                                     |                                        vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_ila_intf_0 |   1209(0.04%) |   1209(0.04%) | 0(0.00%) |    0(0.00%) |   1960(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_ila_intf)                                                                 |                                        vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_ila_intf_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                             vpk180_ipb_axis_ila_alone_0_axis_ila_intf_v1_0_2_axis_ila_intf |   1209(0.04%) |   1209(0.04%) | 0(0.00%) |    0(0.00%) |   1960(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                             vpk180_ipb_axis_ila_alone_0_axis_ila_intf_v1_0_2_axis_ila_intf |    394(0.01%) |    394(0.01%) | 0(0.00%) |    0(0.00%) |   1451(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_clk_status                                                                  |                                vpk180_ipb_axis_ila_alone_0_axis_ila_intf_v1_0_2_clk_status |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_clk_status)                                                              |                                vpk180_ipb_axis_ila_alone_0_axis_ila_intf_v1_0_2_clk_status |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 axis_flag_0_sync_inst                                                       |  vpk180_ipb_axis_ila_alone_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (axis_flag_0_sync_inst)                                                   |  vpk180_ipb_axis_ila_alone_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                             |                              vpk180_ipb_axis_ila_alone_0_xpm_cdc_single__parameterized0__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 des_flag_0_sync_inst                                                        |             vpk180_ipb_axis_ila_alone_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (des_flag_0_sync_inst)                                                    |             vpk180_ipb_axis_ila_alone_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                             |                                 vpk180_ipb_axis_ila_alone_0_xpm_cdc_single__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_core_reg                                                                    |                                 vpk180_ipb_axis_ila_alone_0_axis_ila_intf_v1_0_2_reg_array |    798(0.02%) |    798(0.02%) | 0(0.00%) |    0(0.00%) |    489(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_core_reg)                                                                |                                 vpk180_ipb_axis_ila_alone_0_axis_ila_intf_v1_0_2_reg_array |    795(0.02%) |    795(0.02%) | 0(0.00%) |    0(0.00%) |    413(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 u_done_sync                                                                 |                             vpk180_ipb_axis_ila_alone_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (u_done_sync)                                                             |                             vpk180_ipb_axis_ila_alone_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_0.xpm_cdc_handshake_inst                                          |                                              vpk180_ipb_axis_ila_alone_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (genblk1_0.xpm_cdc_handshake_inst)                                      |                                              vpk180_ipb_axis_ila_alone_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     72(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     xpm_cdc_single_dest2src_inst                                            |                                              vpk180_ipb_axis_ila_alone_0_xpm_cdc_single__5 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     xpm_cdc_single_src2dest_inst                                            |                                              vpk180_ipb_axis_ila_alone_0_xpm_cdc_single__4 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_ila_pp                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_ila_pp)                                                                   |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                 vpk180_ipb_axis_ila_alone_0_axis_ila_pp_v1_0_2_axis_ila_pp |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_itct                                                                         |                                            vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_itct_0 |     95(0.01%) |     95(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_itct)                                                                     |                                            vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_itct_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                     vpk180_ipb_axis_ila_alone_0_axis_itct_v1_0_1_axis_itct |     95(0.01%) |     95(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                     vpk180_ipb_axis_ila_alone_0_axis_itct_v1_0_1_axis_itct |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_mu_itct                                                                     |                                       vpk180_ipb_axis_ila_alone_0_axis_itct_v1_0_1_mu_itct |     95(0.01%) |     95(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_mu_itct)                                                                 |                                       vpk180_ipb_axis_ila_alone_0_axis_itct_v1_0_1_mu_itct |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 u_cfg_en                                                                    |                                        vpk180_ipb_axis_ila_alone_0_axis_itct_v1_0_1_cfg_en |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     68(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mem                                                                          |                                             vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mem_0 |    321(0.01%) |    319(0.01%) | 0(0.00%) |    2(0.01%) |   1942(0.03%) |    9(0.18%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_mem)                                                                      |                                             vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mem_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                       vpk180_ipb_axis_ila_alone_0_axis_mem_v1_0_2_axis_mem |    321(0.01%) |    319(0.01%) | 0(0.00%) |    2(0.01%) |   1942(0.03%) |    9(0.18%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                       vpk180_ipb_axis_ila_alone_0_axis_mem_v1_0_2_axis_mem |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |   1258(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_generic_memrd                                                               |                                  vpk180_ipb_axis_ila_alone_0_axis_mem_v1_0_2_generic_memrd |    163(0.01%) |    161(0.01%) | 0(0.00%) |    2(0.01%) |    356(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_trace_mem                                                                   |                                            vpk180_ipb_axis_ila_alone_0_axis_mem_v1_0_2_mem |    157(0.01%) |    157(0.01%) | 0(0.00%) |    0(0.00%) |    326(0.01%) |    9(0.18%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_trace_mem)                                                               |                                            vpk180_ipb_axis_ila_alone_0_axis_mem_v1_0_2_mem |    157(0.01%) |    157(0.01%) | 0(0.00%) |    0(0.00%) |    326(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 BRAM.XPM_1.sdpram                                                           |                                              vpk180_ipb_axis_ila_alone_0_xpm_memory_sdpram |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    9(0.18%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   xpm_memory_base_inst                                                      |                                                vpk180_ipb_axis_ila_alone_0_xpm_memory_base |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    9(0.18%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_en_deep_strg_o                                                        |                                              vpk180_ipb_axis_ila_alone_0_xpm_cdc_single__6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu0_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu0_0_0 |    114(0.01%) |     81(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu |    114(0.01%) |     81(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu |     22(0.01%) |     21(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_57 |     28(0.01%) |     12(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_58 |     29(0.01%) |     13(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic_59 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu10_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu10_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized0_55 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_56 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu11_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu11_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_53 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_54 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu12_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu12_0_0 |    111(0.01%) |     78(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__1 |    111(0.01%) |     78(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__1 |     22(0.01%) |     21(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_51 |     28(0.01%) |     12(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_52 |     27(0.01%) |     11(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                                vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu13_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu13_0_0 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized2 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized2 |      9(0.01%) |      8(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized2_49 |      6(0.01%) |      2(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_50 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu14_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu14_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized3_47 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_48 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu15_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu15_0_0 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__10 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__10 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_45 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_46 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu16_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu16_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized4 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized4 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized4_43 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_44 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu17_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu17_0_0 |     14(0.01%) |     11(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__6 |     14(0.01%) |     11(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__6 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized0_41 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_42 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu18_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu18_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__5 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__5 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized3_39 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_40 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu19_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu19_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__5 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__5 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized0_37 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_38 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu1_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu1_0_0 |     23(0.01%) |     18(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |     23(0.01%) |     18(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                            vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized2 |      7(0.01%) |      3(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu20_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu20_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__4 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__4 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized0_35 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_36 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu21_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu21_0_0 |     62(0.01%) |     45(0.01%) | 0(0.00%) |   17(0.01%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized5 |     62(0.01%) |     45(0.01%) | 0(0.00%) |   17(0.01%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized5 |     14(0.01%) |     13(0.01%) | 0(0.00%) |    1(0.01%) |     21(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_33 |     28(0.01%) |     12(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized3_34 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu22_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu22_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__9 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__9 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_31 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_32 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu23_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu23_0_0 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__8 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__8 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_29 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_30 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu24_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu24_0_0 |     43(0.01%) |     33(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized6 |     43(0.01%) |     33(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized6 |     11(0.01%) |     10(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized5_27 |     15(0.01%) |      6(0.01%) | 0(0.00%) |    9(0.01%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized4_28 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu25_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu25_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__7 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__7 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_25 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_26 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu26_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu26_0_0 |     41(0.01%) |     31(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized6__1 |     41(0.01%) |     31(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized6__1 |     10(0.01%) |      9(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                            vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized5 |     15(0.01%) |      6(0.01%) | 0(0.00%) |    9(0.01%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized4 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu27_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu27_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__6 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__6 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_23 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_24 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu28_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu28_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__5 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__5 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_21 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_22 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu29_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu29_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__4 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__4 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_19 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_20 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu2_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu2_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__4 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__4 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized3_17 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_18 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu30_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu30_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__3 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized3_15 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_16 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu31_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu31_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__3 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_13 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_14 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu32_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu32_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__2 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__2 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1_11 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_12 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu33_0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu33_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__2 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__2 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized3_9 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_10 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu3_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu3_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |      5(0.01%) |      4(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                            vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized1 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_8 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu4_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu4_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized4__1 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized4__1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                            vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized4 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu5_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu5_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__3 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__3 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized0_6 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_7 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu6_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu6_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__1 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized3__1 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                            vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized3 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_5 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu7_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu7_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__2 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__2 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized0_3 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_4 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu8_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu8_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                            vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx__parameterized0 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu9_0                                                                        |                                           vpk180_ipb_axis_ila_alone_0_bd_cd51_axis_mu9_0_0 |     63(0.01%) |     46(0.01%) | 0(0.00%) |   17(0.01%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized5__1 |     63(0.01%) |     46(0.01%) | 0(0.00%) |   17(0.01%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized5__1 |     14(0.01%) |     13(0.01%) | 0(0.00%) |    1(0.01%) |     21(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                            vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx |     28(0.01%) |     12(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_allx_carry_logic__parameterized3 |     21(0.01%) |     21(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_cc_axis_mu0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized7 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized7 |      9(0.01%) |      8(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_mu_eq_2 |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu1                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_cc_axis_mu1_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized7__3 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized7__3 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_mu_eq_1 |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu2                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_cc_axis_mu2_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized7__2 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized7__2 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_mu_eq_0 |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu3                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_cc_axis_mu3_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized7__1 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized7__1 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                           vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_mu_eq |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_ar                                                                         |                                            vpk180_ipb_axis_ila_alone_0_bd_cd51_slot_0_ar_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_aw                                                                         |                                            vpk180_ipb_axis_ila_alone_0_bd_cd51_slot_0_aw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_b                                                                          |                                             vpk180_ipb_axis_ila_alone_0_bd_cd51_slot_0_b_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_r                                                                          |                                             vpk180_ipb_axis_ila_alone_0_bd_cd51_slot_0_r_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_w                                                                          |                                             vpk180_ipb_axis_ila_alone_0_bd_cd51_slot_0_w_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           tc_axis_mu0                                                                       |                                          vpk180_ipb_axis_ila_alone_0_bd_cd51_tc_axis_mu0_0 |     25(0.01%) |     17(0.01%) | 0(0.00%) |    8(0.01%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized8 |     25(0.01%) |     17(0.01%) | 0(0.00%) |    8(0.01%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                         vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_axis_mu__parameterized8 |     11(0.01%) |     10(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                           vpk180_ipb_axis_ila_alone_0_axis_mu_v1_0_1_mu_eq__parameterized0 |     16(0.01%) |      9(0.01%) | 0(0.00%) |    7(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       axis_ila_idregs                                                                       |                                                               vpk180_ipb_axis_ila_idregs_0 |   2751(0.08%) |   2500(0.07%) | 0(0.00%) |  251(0.01%) |   5474(0.08%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                       vpk180_ipb_axis_ila_idregs_0_bd_43cf |   2751(0.08%) |   2500(0.07%) | 0(0.00%) |  251(0.01%) |   5474(0.08%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (U0)                                                                              |                                                       vpk180_ipb_axis_ila_idregs_0_bd_43cf |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_cap_ctrl                                                                     |                                       vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_cap_ctrl_0 |    138(0.01%) |    138(0.01%) | 0(0.00%) |    0(0.00%) |     73(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                            vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |    138(0.01%) |    138(0.01%) | 0(0.00%) |    0(0.00%) |     73(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                            vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     43(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_1                                                                      |                                    vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_case1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_2                                                                      |                                    vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_case2 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_3                                                                      |                                    vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_case3 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_4                                                                      |                                    vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_case4 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_5                                                                      |                                    vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_case5 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_6                                                                      |                                    vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_case6 |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_7                                                                      |                                    vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_case7 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_8                                                                      |                                    vpk180_ipb_axis_ila_idregs_0_axis_cap_ctrl_v1_0_1_case8 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_stub                                                                     |                                       vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_dbg_stub_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                            vpk180_ipb_axis_ila_idregs_0_axis_dbg_stub_v1_0_1_axis_dbg_stub |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_2                                                                   |                                     vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_dbg_sync_2_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                            vpk180_ipb_axis_ila_idregs_0_axis_dbg_sync_v1_0_1_axis_dbg_sync |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_3.xpm_cdc_single_inst                                                 |                                                vpk180_ipb_axis_ila_idregs_0_xpm_cdc_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_3                                                                   |                                     vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_dbg_sync_3_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            | vpk180_ipb_axis_ila_idregs_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0__xdcDup__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                                          vpk180_ipb_axis_ila_idregs_0_xpm_cdc_array_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_4                                                                   |                                     vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_dbg_sync_4_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |            vpk180_ipb_axis_ila_idregs_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                                       vpk180_ipb_axis_ila_idregs_0_xpm_cdc_array_single__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_5                                                                   |                                     vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_dbg_sync_5_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |            vpk180_ipb_axis_ila_idregs_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                          vpk180_ipb_axis_ila_idregs_0_xpm_cdc_array_single__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_6                                                                   |                                     vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_dbg_sync_6_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |            vpk180_ipb_axis_ila_idregs_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1.xpm_cdc_async_rst_inst                                                |                                             vpk180_ipb_axis_ila_idregs_0_xpm_cdc_async_rst |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_ila_intf                                                                     |                                       vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_ila_intf_0 |   1204(0.04%) |   1204(0.04%) | 0(0.00%) |    0(0.00%) |   2096(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_ila_intf)                                                                 |                                       vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_ila_intf_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                            vpk180_ipb_axis_ila_idregs_0_axis_ila_intf_v1_0_2_axis_ila_intf |   1204(0.04%) |   1204(0.04%) | 0(0.00%) |    0(0.00%) |   2096(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                            vpk180_ipb_axis_ila_idregs_0_axis_ila_intf_v1_0_2_axis_ila_intf |    376(0.01%) |    376(0.01%) | 0(0.00%) |    0(0.00%) |   1587(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_clk_status                                                                  |                               vpk180_ipb_axis_ila_idregs_0_axis_ila_intf_v1_0_2_clk_status |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_clk_status)                                                              |                               vpk180_ipb_axis_ila_idregs_0_axis_ila_intf_v1_0_2_clk_status |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 axis_flag_0_sync_inst                                                       | vpk180_ipb_axis_ila_idregs_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (axis_flag_0_sync_inst)                                                   | vpk180_ipb_axis_ila_idregs_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                             |                             vpk180_ipb_axis_ila_idregs_0_xpm_cdc_single__parameterized0__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 des_flag_0_sync_inst                                                        |            vpk180_ipb_axis_ila_idregs_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (des_flag_0_sync_inst)                                                    |            vpk180_ipb_axis_ila_idregs_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                             |                                vpk180_ipb_axis_ila_idregs_0_xpm_cdc_single__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_core_reg                                                                    |                                vpk180_ipb_axis_ila_idregs_0_axis_ila_intf_v1_0_2_reg_array |    809(0.02%) |    809(0.02%) | 0(0.00%) |    0(0.00%) |    489(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_core_reg)                                                                |                                vpk180_ipb_axis_ila_idregs_0_axis_ila_intf_v1_0_2_reg_array |    806(0.02%) |    806(0.02%) | 0(0.00%) |    0(0.00%) |    413(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 u_done_sync                                                                 |                            vpk180_ipb_axis_ila_idregs_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (u_done_sync)                                                             |                            vpk180_ipb_axis_ila_idregs_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_0.xpm_cdc_handshake_inst                                          |                                             vpk180_ipb_axis_ila_idregs_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (genblk1_0.xpm_cdc_handshake_inst)                                      |                                             vpk180_ipb_axis_ila_idregs_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     72(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     xpm_cdc_single_dest2src_inst                                            |                                             vpk180_ipb_axis_ila_idregs_0_xpm_cdc_single__5 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     xpm_cdc_single_src2dest_inst                                            |                                             vpk180_ipb_axis_ila_idregs_0_xpm_cdc_single__4 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_ila_pp                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_ila_pp)                                                                   |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                vpk180_ipb_axis_ila_idregs_0_axis_ila_pp_v1_0_2_axis_ila_pp |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_itct                                                                         |                                           vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_itct_0 |     96(0.01%) |     96(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_itct)                                                                     |                                           vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_itct_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                    vpk180_ipb_axis_ila_idregs_0_axis_itct_v1_0_1_axis_itct |     96(0.01%) |     96(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                    vpk180_ipb_axis_ila_idregs_0_axis_itct_v1_0_1_axis_itct |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_mu_itct                                                                     |                                      vpk180_ipb_axis_ila_idregs_0_axis_itct_v1_0_1_mu_itct |     96(0.01%) |     96(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_mu_itct)                                                                 |                                      vpk180_ipb_axis_ila_idregs_0_axis_itct_v1_0_1_mu_itct |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 u_cfg_en                                                                    |                                       vpk180_ipb_axis_ila_idregs_0_axis_itct_v1_0_1_cfg_en |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     68(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mem                                                                          |                                            vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mem_0 |    388(0.01%) |    386(0.01%) | 0(0.00%) |    2(0.01%) |   2350(0.03%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_mem)                                                                      |                                            vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mem_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                      vpk180_ipb_axis_ila_idregs_0_axis_mem_v1_0_2_axis_mem |    388(0.01%) |    386(0.01%) | 0(0.00%) |    2(0.01%) |   2350(0.03%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                      vpk180_ipb_axis_ila_idregs_0_axis_mem_v1_0_2_axis_mem |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |   1530(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_generic_memrd                                                               |                                 vpk180_ipb_axis_ila_idregs_0_axis_mem_v1_0_2_generic_memrd |    196(0.01%) |    194(0.01%) | 0(0.00%) |    2(0.01%) |    424(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_trace_mem                                                                   |                                           vpk180_ipb_axis_ila_idregs_0_axis_mem_v1_0_2_mem |    191(0.01%) |    191(0.01%) | 0(0.00%) |    0(0.00%) |    394(0.01%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_trace_mem)                                                               |                                           vpk180_ipb_axis_ila_idregs_0_axis_mem_v1_0_2_mem |    191(0.01%) |    191(0.01%) | 0(0.00%) |    0(0.00%) |    394(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 BRAM.XPM_1.sdpram                                                           |                                             vpk180_ipb_axis_ila_idregs_0_xpm_memory_sdpram |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   xpm_memory_base_inst                                                      |                                               vpk180_ipb_axis_ila_idregs_0_xpm_memory_base |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_en_deep_strg_o                                                        |                                             vpk180_ipb_axis_ila_idregs_0_xpm_cdc_single__6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu0_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu0_0_0 |    114(0.01%) |     81(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu |    114(0.01%) |     81(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu |     23(0.01%) |     22(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_60 |     28(0.01%) |     12(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_61 |     27(0.01%) |     11(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic_62 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu10_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu10_0_0 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized0 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized0 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized0_58 |      7(0.01%) |      3(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_59 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu11_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu11_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_56 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_57 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu12_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu12_0_0 |    112(0.01%) |     79(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__3 |    112(0.01%) |     79(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__3 |     22(0.01%) |     21(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_53 |     28(0.01%) |     12(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_54 |     26(0.01%) |     10(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic_55 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu13_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu13_0_0 |     22(0.01%) |     17(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized0__2 |     22(0.01%) |     17(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized0__2 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized0_51 |      6(0.01%) |      2(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_52 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu14_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu14_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized2_49 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_50 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu15_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu15_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                    vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__10 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                    vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__10 |      5(0.01%) |      4(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_47 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_48 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu16_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu16_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized3 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized3_45 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_46 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu17_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu17_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized4_43 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_44 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu18_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu18_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__5 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__5 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized2_41 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_42 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu19_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu19_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__5 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__5 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized4_39 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_40 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu1_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu1_0_0 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized0 |      7(0.01%) |      3(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu20_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu20_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__4 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__4 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized4_37 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_38 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu21_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu21_0_0 |    114(0.01%) |     81(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__2 |    114(0.01%) |     81(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__2 |     23(0.01%) |     22(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_34 |     28(0.01%) |     12(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_35 |     26(0.01%) |     10(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic_36 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu22_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu22_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__9 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__9 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_32 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_33 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu23_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu23_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__8 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__8 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_30 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_31 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu24_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu24_0_0 |     43(0.01%) |     33(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized5 |     43(0.01%) |     33(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized5 |     11(0.01%) |     10(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized5_28 |     15(0.01%) |      6(0.01%) | 0(0.00%) |    9(0.01%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized3_29 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu25_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu25_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__7 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__7 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_26 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_27 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu26_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu26_0_0 |     40(0.01%) |     30(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized5__1 |     40(0.01%) |     30(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized5__1 |     10(0.01%) |      9(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized5 |     14(0.01%) |      5(0.01%) | 0(0.00%) |    9(0.01%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized3 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu27_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu27_0_0 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__6 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__6 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_24 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_25 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu28_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu28_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__5 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__5 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_22 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_23 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu29_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu29_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__4 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__4 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_20 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_21 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu2_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu2_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__4 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__4 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized2_18 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_19 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu30_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu30_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized2_16 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_17 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu31_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu31_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__3 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_14 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_15 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu32_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu32_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__2 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__2 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1_12 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_13 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu33_0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu33_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized2_10 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |            vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_11 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu3_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu3_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized1 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_9 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu4_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu4_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized3__1 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized3__1 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized3 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu5_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu5_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__3 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized4_7 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_8 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu6_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu6_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized2 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_6 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu7_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu7_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__2 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__2 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                         vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized4_4 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |             vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_5 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu8_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu8_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__1 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized4__1 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx__parameterized4 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu9_0                                                                        |                                          vpk180_ipb_axis_ila_idregs_0_bd_43cf_axis_mu9_0_0 |    115(0.01%) |     82(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__1 |    115(0.01%) |     82(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__1 |     22(0.01%) |     21(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                           vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx |     27(0.01%) |     11(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                         vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_3 |     30(0.01%) |     14(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                               vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_allx_carry_logic |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_cc_axis_mu0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized6 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized6 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_mu_eq_2 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu1                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_cc_axis_mu1_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized6__3 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized6__3 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_mu_eq_1 |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu2                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_cc_axis_mu2_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized6__2 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized6__2 |      9(0.01%) |      8(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_mu_eq_0 |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu3                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_cc_axis_mu3_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized6__1 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                     vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized6__1 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                          vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_mu_eq |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_ar                                                                         |                                           vpk180_ipb_axis_ila_idregs_0_bd_43cf_slot_0_ar_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_aw                                                                         |                                           vpk180_ipb_axis_ila_idregs_0_bd_43cf_slot_0_aw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_b                                                                          |                                            vpk180_ipb_axis_ila_idregs_0_bd_43cf_slot_0_b_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_r                                                                          |                                            vpk180_ipb_axis_ila_idregs_0_bd_43cf_slot_0_r_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_w                                                                          |                                            vpk180_ipb_axis_ila_idregs_0_bd_43cf_slot_0_w_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           tc_axis_mu0                                                                       |                                         vpk180_ipb_axis_ila_idregs_0_bd_43cf_tc_axis_mu0_0 |     23(0.01%) |     15(0.01%) | 0(0.00%) |    8(0.01%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized7 |     23(0.01%) |     15(0.01%) | 0(0.00%) |    8(0.01%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                        vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_axis_mu__parameterized7 |     11(0.01%) |     10(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                          vpk180_ipb_axis_ila_idregs_0_axis_mu_v1_0_1_mu_eq__parameterized0 |     14(0.01%) |      7(0.01%) | 0(0.00%) |    7(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       axis_ila_slr0                                                                         |                                                                 vpk180_ipb_axis_ila_slr0_0 |   2764(0.08%) |   2513(0.07%) | 0(0.00%) |  251(0.01%) |   5470(0.08%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                         vpk180_ipb_axis_ila_slr0_0_bd_5015 |   2764(0.08%) |   2513(0.07%) | 0(0.00%) |  251(0.01%) |   5470(0.08%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (U0)                                                                              |                                                         vpk180_ipb_axis_ila_slr0_0_bd_5015 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_cap_ctrl                                                                     |                                         vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_cap_ctrl_0 |    138(0.01%) |    138(0.01%) | 0(0.00%) |    0(0.00%) |     73(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                              vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |    138(0.01%) |    138(0.01%) | 0(0.00%) |    0(0.00%) |     73(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                              vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     43(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_1                                                                      |                                      vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_case1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_2                                                                      |                                      vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_case2 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_3                                                                      |                                      vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_case3 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_4                                                                      |                                      vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_case4 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_5                                                                      |                                      vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_case5 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_6                                                                      |                                      vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_case6 |     15(0.01%) |     15(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_7                                                                      |                                      vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_case7 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_8                                                                      |                                      vpk180_ipb_axis_ila_slr0_0_axis_cap_ctrl_v1_0_1_case8 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_stub                                                                     |                                         vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_dbg_stub_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                              vpk180_ipb_axis_ila_slr0_0_axis_dbg_stub_v1_0_1_axis_dbg_stub |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_2                                                                   |                                       vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_dbg_sync_2_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                              vpk180_ipb_axis_ila_slr0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_3.xpm_cdc_single_inst                                                 |                                                  vpk180_ipb_axis_ila_slr0_0_xpm_cdc_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_3                                                                   |                                       vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_dbg_sync_3_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |   vpk180_ipb_axis_ila_slr0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0__xdcDup__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                                            vpk180_ipb_axis_ila_slr0_0_xpm_cdc_array_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_4                                                                   |                                       vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_dbg_sync_4_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |              vpk180_ipb_axis_ila_slr0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                                         vpk180_ipb_axis_ila_slr0_0_xpm_cdc_array_single__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_5                                                                   |                                       vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_dbg_sync_5_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |              vpk180_ipb_axis_ila_slr0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                            vpk180_ipb_axis_ila_slr0_0_xpm_cdc_array_single__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_6                                                                   |                                       vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_dbg_sync_6_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |              vpk180_ipb_axis_ila_slr0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1.xpm_cdc_async_rst_inst                                                |                                               vpk180_ipb_axis_ila_slr0_0_xpm_cdc_async_rst |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_ila_intf                                                                     |                                         vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_ila_intf_0 |   1202(0.04%) |   1202(0.04%) | 0(0.00%) |    0(0.00%) |   2096(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_ila_intf)                                                                 |                                         vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_ila_intf_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                              vpk180_ipb_axis_ila_slr0_0_axis_ila_intf_v1_0_2_axis_ila_intf |   1202(0.04%) |   1202(0.04%) | 0(0.00%) |    0(0.00%) |   2096(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                              vpk180_ipb_axis_ila_slr0_0_axis_ila_intf_v1_0_2_axis_ila_intf |    375(0.01%) |    375(0.01%) | 0(0.00%) |    0(0.00%) |   1587(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_clk_status                                                                  |                                 vpk180_ipb_axis_ila_slr0_0_axis_ila_intf_v1_0_2_clk_status |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_clk_status)                                                              |                                 vpk180_ipb_axis_ila_slr0_0_axis_ila_intf_v1_0_2_clk_status |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 axis_flag_0_sync_inst                                                       |   vpk180_ipb_axis_ila_slr0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (axis_flag_0_sync_inst)                                                   |   vpk180_ipb_axis_ila_slr0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                             |                               vpk180_ipb_axis_ila_slr0_0_xpm_cdc_single__parameterized0__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 des_flag_0_sync_inst                                                        |              vpk180_ipb_axis_ila_slr0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (des_flag_0_sync_inst)                                                    |              vpk180_ipb_axis_ila_slr0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                             |                                  vpk180_ipb_axis_ila_slr0_0_xpm_cdc_single__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_core_reg                                                                    |                                  vpk180_ipb_axis_ila_slr0_0_axis_ila_intf_v1_0_2_reg_array |    809(0.02%) |    809(0.02%) | 0(0.00%) |    0(0.00%) |    489(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_core_reg)                                                                |                                  vpk180_ipb_axis_ila_slr0_0_axis_ila_intf_v1_0_2_reg_array |    806(0.02%) |    806(0.02%) | 0(0.00%) |    0(0.00%) |    413(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 u_done_sync                                                                 |                              vpk180_ipb_axis_ila_slr0_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (u_done_sync)                                                             |                              vpk180_ipb_axis_ila_slr0_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_0.xpm_cdc_handshake_inst                                          |                                               vpk180_ipb_axis_ila_slr0_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (genblk1_0.xpm_cdc_handshake_inst)                                      |                                               vpk180_ipb_axis_ila_slr0_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     72(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     xpm_cdc_single_dest2src_inst                                            |                                               vpk180_ipb_axis_ila_slr0_0_xpm_cdc_single__5 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     xpm_cdc_single_src2dest_inst                                            |                                               vpk180_ipb_axis_ila_slr0_0_xpm_cdc_single__4 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_ila_pp                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_ila_pp)                                                                   |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                  vpk180_ipb_axis_ila_slr0_0_axis_ila_pp_v1_0_2_axis_ila_pp |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_itct                                                                         |                                             vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_itct_0 |     96(0.01%) |     96(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_itct)                                                                     |                                             vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_itct_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                      vpk180_ipb_axis_ila_slr0_0_axis_itct_v1_0_1_axis_itct |     96(0.01%) |     96(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                      vpk180_ipb_axis_ila_slr0_0_axis_itct_v1_0_1_axis_itct |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_mu_itct                                                                     |                                        vpk180_ipb_axis_ila_slr0_0_axis_itct_v1_0_1_mu_itct |     96(0.01%) |     96(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_mu_itct)                                                                 |                                        vpk180_ipb_axis_ila_slr0_0_axis_itct_v1_0_1_mu_itct |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 u_cfg_en                                                                    |                                         vpk180_ipb_axis_ila_slr0_0_axis_itct_v1_0_1_cfg_en |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     68(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mem                                                                          |                                              vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mem_0 |    388(0.01%) |    386(0.01%) | 0(0.00%) |    2(0.01%) |   2350(0.03%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_mem)                                                                      |                                              vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mem_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                        vpk180_ipb_axis_ila_slr0_0_axis_mem_v1_0_2_axis_mem |    388(0.01%) |    386(0.01%) | 0(0.00%) |    2(0.01%) |   2350(0.03%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                        vpk180_ipb_axis_ila_slr0_0_axis_mem_v1_0_2_axis_mem |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |   1530(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_generic_memrd                                                               |                                   vpk180_ipb_axis_ila_slr0_0_axis_mem_v1_0_2_generic_memrd |    196(0.01%) |    194(0.01%) | 0(0.00%) |    2(0.01%) |    424(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_trace_mem                                                                   |                                             vpk180_ipb_axis_ila_slr0_0_axis_mem_v1_0_2_mem |    191(0.01%) |    191(0.01%) | 0(0.00%) |    0(0.00%) |    394(0.01%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_trace_mem)                                                               |                                             vpk180_ipb_axis_ila_slr0_0_axis_mem_v1_0_2_mem |    191(0.01%) |    191(0.01%) | 0(0.00%) |    0(0.00%) |    394(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 BRAM.XPM_1.sdpram                                                           |                                               vpk180_ipb_axis_ila_slr0_0_xpm_memory_sdpram |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   xpm_memory_base_inst                                                      |                                                 vpk180_ipb_axis_ila_slr0_0_xpm_memory_base |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_en_deep_strg_o                                                        |                                               vpk180_ipb_axis_ila_slr0_0_xpm_cdc_single__6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu0_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu0_0_0 |    115(0.01%) |     82(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu |    115(0.01%) |     82(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu |     23(0.01%) |     22(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_60 |     29(0.01%) |     13(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_61 |     27(0.01%) |     11(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic_62 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu10_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu10_0_0 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized0 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized0 |      9(0.01%) |      8(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized0_58 |      7(0.01%) |      3(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_59 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu11_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu11_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_56 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_57 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu12_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu12_0_0 |    113(0.01%) |     80(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__3 |    113(0.01%) |     80(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__3 |     21(0.01%) |     20(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_53 |     29(0.01%) |     13(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_54 |     28(0.01%) |     12(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic_55 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu13_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu13_0_0 |     25(0.01%) |     20(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized0__2 |     25(0.01%) |     20(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized0__2 |      9(0.01%) |      8(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized0_51 |      7(0.01%) |      3(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_52 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu14_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu14_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized2_49 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_50 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu15_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu15_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__10 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__10 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_47 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_48 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu16_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu16_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized3 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized3_45 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_46 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu17_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu17_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized4_43 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_44 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu18_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu18_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__5 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__5 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized2_41 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_42 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu19_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu19_0_0 |     14(0.01%) |     11(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__5 |     14(0.01%) |     11(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__5 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized4_39 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_40 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu1_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu1_0_0 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |      9(0.01%) |      8(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized0 |      6(0.01%) |      2(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                 vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu20_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu20_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__4 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__4 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized4_37 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_38 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu21_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu21_0_0 |    115(0.01%) |     82(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__2 |    115(0.01%) |     82(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__2 |     22(0.01%) |     21(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_34 |     30(0.01%) |     14(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_35 |     30(0.01%) |     14(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic_36 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu22_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu22_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__9 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__9 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_32 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_33 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu23_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu23_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__8 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__8 |      5(0.01%) |      4(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_30 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_31 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu24_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu24_0_0 |     43(0.01%) |     33(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized5 |     43(0.01%) |     33(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized5 |     11(0.01%) |     10(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized5_28 |     16(0.01%) |      7(0.01%) | 0(0.00%) |    9(0.01%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized3_29 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu25_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu25_0_0 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__7 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__7 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_26 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_27 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu26_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu26_0_0 |     42(0.01%) |     32(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized5__1 |     42(0.01%) |     32(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized5__1 |     10(0.01%) |      9(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized5 |     16(0.01%) |      7(0.01%) | 0(0.00%) |    9(0.01%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                 vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized3 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu27_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu27_0_0 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__6 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__6 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_24 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_25 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu28_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu28_0_0 |      8(0.01%) |      6(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__5 |      8(0.01%) |      6(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__5 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_22 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_23 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu29_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu29_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__4 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__4 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_20 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_21 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu2_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu2_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__4 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__4 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized2_18 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_19 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu30_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu30_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized2_16 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_17 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu31_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu31_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__3 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_14 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_15 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu32_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu32_0_0 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__2 |     11(0.01%) |      9(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__2 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1_12 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_13 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu33_0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu33_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized2_10 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_11 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu3_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu3_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized1 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_9 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu4_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu4_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized3__1 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized3__1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized3 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                 vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu5_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu5_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__3 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__3 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized4_7 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_8 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu6_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu6_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized2 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_6 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu7_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu7_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__2 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__2 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized4_4 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_5 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu8_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu8_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__1 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized4__1 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx__parameterized4 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                 vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu9_0                                                                        |                                            vpk180_ipb_axis_ila_slr0_0_bd_5015_axis_mu9_0_0 |    112(0.01%) |     79(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__1 |    112(0.01%) |     79(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__1 |     22(0.01%) |     21(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                             vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx |     29(0.01%) |     13(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                           vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_3 |     26(0.01%) |     10(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                                 vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_allx_carry_logic |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_cc_axis_mu0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized6 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized6 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_mu_eq_2 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu1                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_cc_axis_mu1_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized6__3 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized6__3 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_mu_eq_1 |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu2                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_cc_axis_mu2_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized6__2 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized6__2 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_mu_eq_0 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu3                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_cc_axis_mu3_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized6__1 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized6__1 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                            vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_mu_eq |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_ar                                                                         |                                             vpk180_ipb_axis_ila_slr0_0_bd_5015_slot_0_ar_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_aw                                                                         |                                             vpk180_ipb_axis_ila_slr0_0_bd_5015_slot_0_aw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_b                                                                          |                                              vpk180_ipb_axis_ila_slr0_0_bd_5015_slot_0_b_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_r                                                                          |                                              vpk180_ipb_axis_ila_slr0_0_bd_5015_slot_0_r_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_w                                                                          |                                              vpk180_ipb_axis_ila_slr0_0_bd_5015_slot_0_w_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           tc_axis_mu0                                                                       |                                           vpk180_ipb_axis_ila_slr0_0_bd_5015_tc_axis_mu0_0 |     24(0.01%) |     16(0.01%) | 0(0.00%) |    8(0.01%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized7 |     24(0.01%) |     16(0.01%) | 0(0.00%) |    8(0.01%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_axis_mu__parameterized7 |     10(0.01%) |      9(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                            vpk180_ipb_axis_ila_slr0_0_axis_mu_v1_0_1_mu_eq__parameterized0 |     14(0.01%) |      7(0.01%) | 0(0.00%) |    7(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       axis_ila_slr1                                                                         |                                                                 vpk180_ipb_axis_ila_slr1_0 |   2741(0.08%) |   2490(0.07%) | 0(0.00%) |  251(0.01%) |   5474(0.08%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                         vpk180_ipb_axis_ila_slr1_0_bd_9044 |   2741(0.08%) |   2490(0.07%) | 0(0.00%) |  251(0.01%) |   5474(0.08%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (U0)                                                                              |                                                         vpk180_ipb_axis_ila_slr1_0_bd_9044 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_cap_ctrl                                                                     |                                         vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_cap_ctrl_0 |    141(0.01%) |    141(0.01%) | 0(0.00%) |    0(0.00%) |     73(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                              vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |    141(0.01%) |    141(0.01%) | 0(0.00%) |    0(0.00%) |     73(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                              vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |     77(0.01%) |     77(0.01%) | 0(0.00%) |    0(0.00%) |     43(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_1                                                                      |                                      vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_case1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_2                                                                      |                                      vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_case2 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_3                                                                      |                                      vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_case3 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_4                                                                      |                                      vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_case4 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_5                                                                      |                                      vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_case5 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_6                                                                      |                                      vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_case6 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_7                                                                      |                                      vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_case7 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U_CASE_8                                                                      |                                      vpk180_ipb_axis_ila_slr1_0_axis_cap_ctrl_v1_0_1_case8 |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_stub                                                                     |                                         vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_dbg_stub_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                              vpk180_ipb_axis_ila_slr1_0_axis_dbg_stub_v1_0_1_axis_dbg_stub |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_2                                                                   |                                       vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_dbg_sync_2_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                              vpk180_ipb_axis_ila_slr1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_3.xpm_cdc_single_inst                                                 |                                                  vpk180_ipb_axis_ila_slr1_0_xpm_cdc_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_3                                                                   |                                       vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_dbg_sync_3_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |   vpk180_ipb_axis_ila_slr1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0__xdcDup__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                                            vpk180_ipb_axis_ila_slr1_0_xpm_cdc_array_single |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_4                                                                   |                                       vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_dbg_sync_4_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |              vpk180_ipb_axis_ila_slr1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                                         vpk180_ipb_axis_ila_slr1_0_xpm_cdc_array_single__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_5                                                                   |                                       vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_dbg_sync_5_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |              vpk180_ipb_axis_ila_slr1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1_2.xpm_cdc_array_single_inst                                           |                            vpk180_ipb_axis_ila_slr1_0_xpm_cdc_array_single__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_dbg_sync_6                                                                   |                                       vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_dbg_sync_6_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |              vpk180_ipb_axis_ila_slr1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               genblk1.xpm_cdc_async_rst_inst                                                |                                               vpk180_ipb_axis_ila_slr1_0_xpm_cdc_async_rst |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_ila_intf                                                                     |                                         vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_ila_intf_0 |   1204(0.04%) |   1204(0.04%) | 0(0.00%) |    0(0.00%) |   2096(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_ila_intf)                                                                 |                                         vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_ila_intf_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                              vpk180_ipb_axis_ila_slr1_0_axis_ila_intf_v1_0_2_axis_ila_intf |   1204(0.04%) |   1204(0.04%) | 0(0.00%) |    0(0.00%) |   2096(0.03%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                              vpk180_ipb_axis_ila_slr1_0_axis_ila_intf_v1_0_2_axis_ila_intf |    377(0.01%) |    377(0.01%) | 0(0.00%) |    0(0.00%) |   1587(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_clk_status                                                                  |                                 vpk180_ipb_axis_ila_slr1_0_axis_ila_intf_v1_0_2_clk_status |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_clk_status)                                                              |                                 vpk180_ipb_axis_ila_slr1_0_axis_ila_intf_v1_0_2_clk_status |     19(0.01%) |     19(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 axis_flag_0_sync_inst                                                       |   vpk180_ipb_axis_ila_slr1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (axis_flag_0_sync_inst)                                                   |   vpk180_ipb_axis_ila_slr1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                             |                               vpk180_ipb_axis_ila_slr1_0_xpm_cdc_single__parameterized0__2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 des_flag_0_sync_inst                                                        |              vpk180_ipb_axis_ila_slr1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (des_flag_0_sync_inst)                                                    |              vpk180_ipb_axis_ila_slr1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                             |                                  vpk180_ipb_axis_ila_slr1_0_xpm_cdc_single__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_core_reg                                                                    |                                  vpk180_ipb_axis_ila_slr1_0_axis_ila_intf_v1_0_2_reg_array |    809(0.02%) |    809(0.02%) | 0(0.00%) |    0(0.00%) |    489(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_core_reg)                                                                |                                  vpk180_ipb_axis_ila_slr1_0_axis_ila_intf_v1_0_2_reg_array |    806(0.02%) |    806(0.02%) | 0(0.00%) |    0(0.00%) |    413(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 u_done_sync                                                                 |                              vpk180_ipb_axis_ila_slr1_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (u_done_sync)                                                             |                              vpk180_ipb_axis_ila_slr1_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   genblk1_0.xpm_cdc_handshake_inst                                          |                                               vpk180_ipb_axis_ila_slr1_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     76(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (genblk1_0.xpm_cdc_handshake_inst)                                      |                                               vpk180_ipb_axis_ila_slr1_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     72(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     xpm_cdc_single_dest2src_inst                                            |                                               vpk180_ipb_axis_ila_slr1_0_xpm_cdc_single__5 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     xpm_cdc_single_src2dest_inst                                            |                                               vpk180_ipb_axis_ila_slr1_0_xpm_cdc_single__4 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_ila_pp                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_ila_pp)                                                                   |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                  vpk180_ipb_axis_ila_slr1_0_axis_ila_pp_v1_0_2_axis_ila_pp |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_itct                                                                         |                                             vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_itct_0 |     96(0.01%) |     96(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_itct)                                                                     |                                             vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_itct_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                      vpk180_ipb_axis_ila_slr1_0_axis_itct_v1_0_1_axis_itct |     96(0.01%) |     96(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                      vpk180_ipb_axis_ila_slr1_0_axis_itct_v1_0_1_axis_itct |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_mu_itct                                                                     |                                        vpk180_ipb_axis_ila_slr1_0_axis_itct_v1_0_1_mu_itct |     96(0.01%) |     96(0.01%) | 0(0.00%) |    0(0.00%) |     81(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_mu_itct)                                                                 |                                        vpk180_ipb_axis_ila_slr1_0_axis_itct_v1_0_1_mu_itct |     23(0.01%) |     23(0.01%) | 0(0.00%) |    0(0.00%) |     13(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 u_cfg_en                                                                    |                                         vpk180_ipb_axis_ila_slr1_0_axis_itct_v1_0_1_cfg_en |     73(0.01%) |     73(0.01%) | 0(0.00%) |    0(0.00%) |     68(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mem                                                                          |                                              vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mem_0 |    389(0.01%) |    387(0.01%) | 0(0.00%) |    2(0.01%) |   2350(0.03%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (axis_mem)                                                                      |                                              vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mem_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                        vpk180_ipb_axis_ila_slr1_0_axis_mem_v1_0_2_axis_mem |    389(0.01%) |    387(0.01%) | 0(0.00%) |    2(0.01%) |   2350(0.03%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                        vpk180_ipb_axis_ila_slr1_0_axis_mem_v1_0_2_axis_mem |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |   1530(0.02%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_generic_memrd                                                               |                                   vpk180_ipb_axis_ila_slr1_0_axis_mem_v1_0_2_generic_memrd |    197(0.01%) |    195(0.01%) | 0(0.00%) |    2(0.01%) |    424(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               u_trace_mem                                                                   |                                             vpk180_ipb_axis_ila_slr1_0_axis_mem_v1_0_2_mem |    191(0.01%) |    191(0.01%) | 0(0.00%) |    0(0.00%) |    394(0.01%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (u_trace_mem)                                                               |                                             vpk180_ipb_axis_ila_slr1_0_axis_mem_v1_0_2_mem |    191(0.01%) |    191(0.01%) | 0(0.00%) |    0(0.00%) |    394(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 BRAM.XPM_1.sdpram                                                           |                                               vpk180_ipb_axis_ila_slr1_0_xpm_memory_sdpram |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   xpm_memory_base_inst                                                      |                                                 vpk180_ipb_axis_ila_slr1_0_xpm_memory_base |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |   11(0.22%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               xpm_cdc_en_deep_strg_o                                                        |                                               vpk180_ipb_axis_ila_slr1_0_xpm_cdc_single__6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu0_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu0_0_0 |    110(0.01%) |     77(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu |    110(0.01%) |     77(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu |     22(0.01%) |     21(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_60 |     26(0.01%) |     10(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_61 |     26(0.01%) |     10(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic_62 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu10_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu10_0_0 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized0 |     24(0.01%) |     19(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized0 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized0_58 |      7(0.01%) |      3(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_59 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu11_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu11_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_56 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_57 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu12_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu12_0_0 |    111(0.01%) |     78(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__3 |    111(0.01%) |     78(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__3 |     23(0.01%) |     22(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_53 |     27(0.01%) |     11(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_54 |     27(0.01%) |     11(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic_55 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu13_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu13_0_0 |     23(0.01%) |     18(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized0__2 |     23(0.01%) |     18(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized0__2 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized0_51 |      7(0.01%) |      3(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_52 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu14_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu14_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized2_49 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_50 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu15_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu15_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                      vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__10 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                      vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__10 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_47 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_48 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu16_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu16_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized3 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized3_45 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_46 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu17_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu17_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized4_43 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_44 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu18_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu18_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__5 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__5 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized2_41 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_42 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu19_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu19_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__5 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__5 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized4_39 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_40 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu1_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu1_0_0 |     23(0.01%) |     18(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |     23(0.01%) |     18(0.01%) | 0(0.00%) |    5(0.01%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized0 |      6(0.01%) |      2(0.01%) | 0(0.00%) |    4(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                 vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu20_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu20_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__4 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__4 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized4_37 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_38 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu21_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu21_0_0 |    112(0.01%) |     79(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__2 |    112(0.01%) |     79(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__2 |     23(0.01%) |     22(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_34 |     29(0.01%) |     13(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_35 |     26(0.01%) |     10(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic_36 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu22_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu22_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__9 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__9 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_32 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_33 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu23_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu23_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__8 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__8 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_30 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_31 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu24_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu24_0_0 |     43(0.01%) |     33(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized5 |     43(0.01%) |     33(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized5 |     10(0.01%) |      9(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized5_28 |     16(0.01%) |      7(0.01%) | 0(0.00%) |    9(0.01%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized3_29 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu25_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu25_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__7 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__7 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_26 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_27 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu26_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu26_0_0 |     42(0.01%) |     32(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized5__1 |     42(0.01%) |     32(0.01%) | 0(0.00%) |   10(0.01%) |     31(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized5__1 |     10(0.01%) |      9(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized5 |     15(0.01%) |      6(0.01%) | 0(0.00%) |    9(0.01%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                 vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized3 |     17(0.01%) |     17(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu27_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu27_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__6 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__6 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_24 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_25 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu28_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu28_0_0 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__5 |     10(0.01%) |      8(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__5 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_22 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_23 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu29_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu29_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__4 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__4 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_20 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_21 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu2_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu2_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__4 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__4 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized2_18 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_19 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu30_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu30_0_0 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |     13(0.01%) |     10(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized2_16 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_17 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu31_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu31_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__3 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_14 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_15 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu32_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu32_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__2 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__2 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1_12 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_13 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu33_0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu33_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized2_10 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |              vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_11 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu3_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu3_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized1 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_9 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu4_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu4_0_0 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized3__1 |      9(0.01%) |      7(0.01%) | 0(0.00%) |    2(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized3__1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized3 |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                 vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu5_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu5_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__3 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__3 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized4_7 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_8 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu6_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu6_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized2 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_6 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu7_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu7_0_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__2 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__2 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                           vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized4_4 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |               vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2_5 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu8_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu8_0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__1 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized4__1 |      6(0.01%) |      5(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_NFULL.u_allx                                                          |                             vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx__parameterized4 |      3(0.01%) |      1(0.01%) | 0(0.00%) |    2(0.01%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                 vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized2 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           axis_mu9_0                                                                        |                                            vpk180_ipb_axis_ila_slr1_0_bd_9044_axis_mu9_0_0 |    111(0.01%) |     78(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__1 |    111(0.01%) |     78(0.01%) | 0(0.00%) |   33(0.01%) |    102(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__1 |     23(0.01%) |     22(0.01%) | 0(0.00%) |    1(0.01%) |     37(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[0].u_allx                                                        |                                             vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx |     25(0.01%) |      9(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.L2_FULL[1].u_allx                                                        |                                           vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_3 |     26(0.01%) |     10(0.01%) | 0(0.00%) |   16(0.01%) |     32(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               ALLX.u_allx_carry                                                             |                                 vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_allx_carry_logic |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_cc_axis_mu0_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized6 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized6 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_mu_eq_2 |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu1                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_cc_axis_mu1_0 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized6__3 |     11(0.01%) |      8(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized6__3 |      7(0.01%) |      6(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_mu_eq_1 |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu2                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_cc_axis_mu2_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized6__2 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized6__2 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_mu_eq_0 |      5(0.01%) |      3(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           cc_axis_mu3                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_cc_axis_mu3_0 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized6__1 |     12(0.01%) |      9(0.01%) | 0(0.00%) |    3(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                       vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized6__1 |      8(0.01%) |      7(0.01%) | 0(0.00%) |    1(0.01%) |      8(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                                            vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_mu_eq |      4(0.01%) |      2(0.01%) | 0(0.00%) |    2(0.01%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_ar                                                                         |                                             vpk180_ipb_axis_ila_slr1_0_bd_9044_slot_0_ar_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_aw                                                                         |                                             vpk180_ipb_axis_ila_slr1_0_bd_9044_slot_0_aw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_b                                                                          |                                              vpk180_ipb_axis_ila_slr1_0_bd_9044_slot_0_b_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_r                                                                          |                                              vpk180_ipb_axis_ila_slr1_0_bd_9044_slot_0_r_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           slot_0_w                                                                          |                                              vpk180_ipb_axis_ila_slr1_0_bd_9044_slot_0_w_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           tc_axis_mu0                                                                       |                                           vpk180_ipb_axis_ila_slr1_0_bd_9044_tc_axis_mu0_0 |     23(0.01%) |     15(0.01%) | 0(0.00%) |    8(0.01%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized7 |     23(0.01%) |     15(0.01%) | 0(0.00%) |    8(0.01%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               (inst)                                                                        |                          vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_axis_mu__parameterized7 |     10(0.01%) |      9(0.01%) | 0(0.00%) |    1(0.01%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               MU_EQ.L2_NFULL.u_eq                                                           |                            vpk180_ipb_axis_ila_slr1_0_axis_mu_v1_0_1_mu_eq__parameterized0 |     14(0.01%) |      7(0.01%) | 0(0.00%) |    7(0.01%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       proc_sys_reset_300MHz                                                                 |                                                         vpk180_ipb_proc_sys_reset_300MHz_0 |     21(0.01%) |     20(0.01%) | 0(0.00%) |    1(0.01%) |     35(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                          vpk180_ipb_proc_sys_reset_300MHz_0_proc_sys_reset |     21(0.01%) |     20(0.01%) | 0(0.00%) |    1(0.01%) |     35(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (U0)                                                                              |                                          vpk180_ipb_proc_sys_reset_300MHz_0_proc_sys_reset |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           EXT_LPF                                                                           |                                                     vpk180_ipb_proc_sys_reset_300MHz_0_lpf |      5(0.01%) |      4(0.01%) | 0(0.00%) |    1(0.01%) |     19(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (EXT_LPF)                                                                       |                                                     vpk180_ipb_proc_sys_reset_300MHz_0_lpf |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             ACTIVE_LOW_AUX.ACT_LO_AUX                                                       |                                                vpk180_ipb_proc_sys_reset_300MHz_0_cdc_sync |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             ACTIVE_LOW_EXT.ACT_LO_EXT                                                       |                                              vpk180_ipb_proc_sys_reset_300MHz_0_cdc_sync_0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           SEQ                                                                               |                                            vpk180_ipb_proc_sys_reset_300MHz_0_sequence_psr |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (SEQ)                                                                           |                                            vpk180_ipb_proc_sys_reset_300MHz_0_sequence_psr |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             SEQ_COUNTER                                                                     |                                                 vpk180_ipb_proc_sys_reset_300MHz_0_upcnt_n |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       proc_sys_reset_ipbus                                                                  |                                                          vpk180_ipb_proc_sys_reset_ipbus_0 |     23(0.01%) |     22(0.01%) | 0(0.00%) |    1(0.01%) |     47(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                           vpk180_ipb_proc_sys_reset_ipbus_0_proc_sys_reset |     23(0.01%) |     22(0.01%) | 0(0.00%) |    1(0.01%) |     47(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           (U0)                                                                              |                                           vpk180_ipb_proc_sys_reset_ipbus_0_proc_sys_reset |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |     10(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           EXT_LPF                                                                           |                                                      vpk180_ipb_proc_sys_reset_ipbus_0_lpf |      5(0.01%) |      4(0.01%) | 0(0.00%) |    1(0.01%) |     19(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (EXT_LPF)                                                                       |                                                      vpk180_ipb_proc_sys_reset_ipbus_0_lpf |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             ACTIVE_LOW_AUX.ACT_LO_AUX                                                       |                                                 vpk180_ipb_proc_sys_reset_ipbus_0_cdc_sync |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             ACTIVE_LOW_EXT.ACT_LO_EXT                                                       |                                               vpk180_ipb_proc_sys_reset_ipbus_0_cdc_sync_0 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           SEQ                                                                               |                                             vpk180_ipb_proc_sys_reset_ipbus_0_sequence_psr |     18(0.01%) |     18(0.01%) | 0(0.00%) |    0(0.00%) |     18(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (SEQ)                                                                           |                                             vpk180_ipb_proc_sys_reset_ipbus_0_sequence_psr |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             SEQ_COUNTER                                                                     |                                                  vpk180_ipb_proc_sys_reset_ipbus_0_upcnt_n |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       smartconnect_0                                                                        |                                                                vpk180_ipb_smartconnect_0_0 |    711(0.02%) |    710(0.02%) | 0(0.00%) |    1(0.01%) |    845(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         inst                                                                                |                                                        vpk180_ipb_smartconnect_0_0_bd_6c0a |    711(0.02%) |    710(0.02%) | 0(0.00%) |    1(0.01%) |    845(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           clk_map                                                                           |                                             vpk180_ipb_smartconnect_0_0_clk_map_imp_MMRO03 |     19(0.01%) |     18(0.01%) | 0(0.00%) |    1(0.01%) |     23(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             psr_aclk                                                                        |                                             vpk180_ipb_smartconnect_0_0_bd_6c0a_psr_aclk_0 |     19(0.01%) |     18(0.01%) | 0(0.00%) |    1(0.01%) |     23(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               U0                                                                            |                                                 vpk180_ipb_smartconnect_0_0_proc_sys_reset |     19(0.01%) |     18(0.01%) | 0(0.00%) |    1(0.01%) |     23(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (U0)                                                                        |                                                 vpk180_ipb_smartconnect_0_0_proc_sys_reset |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 EXT_LPF                                                                     |                                                            vpk180_ipb_smartconnect_0_0_lpf |      3(0.01%) |      2(0.01%) | 0(0.00%) |    1(0.01%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (EXT_LPF)                                                                 |                                                            vpk180_ipb_smartconnect_0_0_lpf |      2(0.01%) |      1(0.01%) | 0(0.00%) |    1(0.01%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   ACTIVE_LOW_AUX.ACT_LO_AUX                                                 |                                                       vpk180_ipb_smartconnect_0_0_cdc_sync |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 SEQ                                                                         |                                                   vpk180_ipb_smartconnect_0_0_sequence_psr |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |     15(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (SEQ)                                                                     |                                                   vpk180_ipb_smartconnect_0_0_sequence_psr |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   SEQ_COUNTER                                                               |                                                        vpk180_ipb_smartconnect_0_0_upcnt_n |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           m00_exit_pipeline                                                                 |                                  vpk180_ipb_smartconnect_0_0_m00_exit_pipeline_imp_1AYJ8GO |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m00_exit                                                                        |                                                 vpk180_ipb_smartconnect_0_0_bd_6c0a_m00e_0 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                                 vpk180_ipb_smartconnect_0_0_sc_exit_v1_0_16_top__xdcDup__1 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                                 vpk180_ipb_smartconnect_0_0_sc_exit_v1_0_16_top__xdcDup__1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 exit_inst                                                                   |                                        vpk180_ipb_smartconnect_0_0_sc_exit_v1_0_16_exit_18 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 xpm_cdc_async_rst_inst                                                      |                                           vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__7 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           m00_nodes                                                                         |                                          vpk180_ipb_smartconnect_0_0_m00_nodes_imp_1X3NNP0 |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     27(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m00_ar_node                                                                     |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_m00arn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__xdcDup__1 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__xdcDup__1 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                                  vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler_17 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                           vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__8 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m00_aw_node                                                                     |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_m00awn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized0__xdcDup__1 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized0__xdcDup__1 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                  vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized0_16 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__10 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m00_b_node                                                                      |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_m00bn_0 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized1__xdcDup__1 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized1__xdcDup__1 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                  vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized1_15 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__12 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m00_r_node                                                                      |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_m00rn_0 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized2__xdcDup__1 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized2__xdcDup__1 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                  vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized2_14 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__14 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m00_w_node                                                                      |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_m00wn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized3__xdcDup__1 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized3__xdcDup__1 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                  vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized3_13 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__16 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           m00_sc2axi                                                                        |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_m00s2a_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                       vpk180_ipb_smartconnect_0_0_sc_sc2axi_v1_0_10_top__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           m01_exit_pipeline                                                                 |                                  vpk180_ipb_smartconnect_0_0_m01_exit_pipeline_imp_1GQR2HK |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m01_exit                                                                        |                                                 vpk180_ipb_smartconnect_0_0_bd_6c0a_m01e_0 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                                            vpk180_ipb_smartconnect_0_0_sc_exit_v1_0_16_top |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |      9(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                                            vpk180_ipb_smartconnect_0_0_sc_exit_v1_0_16_top |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 exit_inst                                                                   |                                           vpk180_ipb_smartconnect_0_0_sc_exit_v1_0_16_exit |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 xpm_cdc_async_rst_inst                                                      |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__18 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           m01_nodes                                                                         |                                           vpk180_ipb_smartconnect_0_0_m01_nodes_imp_RR13NM |     22(0.01%) |     22(0.01%) | 0(0.00%) |    0(0.00%) |     27(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m01_ar_node                                                                     |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_m01arn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__19 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m01_aw_node                                                                     |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_m01awn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized0 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized0 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__21 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m01_b_node                                                                      |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_m01bn_0 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized1 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized1 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized1 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__23 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m01_r_node                                                                      |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_m01rn_0 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized2 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      6(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized2 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized2 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__25 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             m01_w_node                                                                      |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_m01wn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized3 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized3 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized3 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__27 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           m01_sc2axi                                                                        |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_m01s2a_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                          vpk180_ipb_smartconnect_0_0_sc_sc2axi_v1_0_10_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           s00_axi2sc                                                                        |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_s00a2s_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             inst                                                                            |                                          vpk180_ipb_smartconnect_0_0_sc_axi2sc_v1_0_10_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           s00_entry_pipeline                                                                |                                  vpk180_ipb_smartconnect_0_0_s00_entry_pipeline_imp_BOFUE3 |    518(0.02%) |    518(0.02%) | 0(0.00%) |    0(0.00%) |    565(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             s00_mmu                                                                         |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_s00mmu_0 |    211(0.01%) |    211(0.01%) | 0(0.00%) |    0(0.00%) |    223(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                                             vpk180_ipb_smartconnect_0_0_sc_mmu_v1_0_14_top |    211(0.01%) |    211(0.01%) | 0(0.00%) |    0(0.00%) |    223(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                                             vpk180_ipb_smartconnect_0_0_sc_mmu_v1_0_14_top |     74(0.01%) |     74(0.01%) | 0(0.00%) |    0(0.00%) |     21(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 ar_reg_stall                                                                |                   vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_axi_reg_stall__parameterized0 |     45(0.01%) |     45(0.01%) | 0(0.00%) |    0(0.00%) |     82(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 aw_reg_stall                                                                |                vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_axi_reg_stall__parameterized0_12 |     37(0.01%) |     37(0.01%) | 0(0.00%) |    0(0.00%) |     66(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 gen_endpoint.decerr_slave_inst                                              |                                    vpk180_ipb_smartconnect_0_0_sc_mmu_v1_0_14_decerr_slave |     45(0.01%) |     45(0.01%) | 0(0.00%) |    0(0.00%) |     49(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 gen_wroute_reg.wroute_split                                                 |                                    vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_axi_splitter |     12(0.01%) |     12(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 xpm_cdc_async_rst_inst                                                      |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__29 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             s00_si_converter                                                                |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_s00sic_0 |    299(0.01%) |    299(0.01%) | 0(0.00%) |    0(0.00%) |    302(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                                    vpk180_ipb_smartconnect_0_0_sc_si_converter_v1_0_14_top |    299(0.01%) |    299(0.01%) | 0(0.00%) |    0(0.00%) |    302(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                                    vpk180_ipb_smartconnect_0_0_sc_si_converter_v1_0_14_top |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 gen_axilite_conv.axilite_conv_inst                                          |                           vpk180_ipb_smartconnect_0_0_sc_si_converter_v1_0_14_axilite_conv |    298(0.01%) |    298(0.01%) | 0(0.00%) |    0(0.00%) |    298(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 xpm_cdc_async_rst_inst                                                      |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__30 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             s00_transaction_regulator                                                       |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_s00tr_0 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     40(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                           vpk180_ipb_smartconnect_0_0_sc_transaction_regulator_v1_0_11_top |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     40(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                           vpk180_ipb_smartconnect_0_0_sc_transaction_regulator_v1_0_11_top |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 gen_endpoint.gen_r_singleorder.r_singleorder                                |                   vpk180_ipb_smartconnect_0_0_sc_transaction_regulator_v1_0_11_singleorder |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |     17(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 gen_endpoint.gen_w_singleorder.w_singleorder                                |                vpk180_ipb_smartconnect_0_0_sc_transaction_regulator_v1_0_11_singleorder_11 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     19(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 xpm_cdc_async_rst_inst                                                      |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__31 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           s00_nodes                                                                         |                                           vpk180_ipb_smartconnect_0_0_s00_nodes_imp_HO31J5 |     20(0.01%) |     20(0.01%) | 0(0.00%) |    0(0.00%) |     25(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             s00_ar_node                                                                     |                                                 vpk180_ipb_smartconnect_0_0_bd_6c0a_sarn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized4 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized4 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized4 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__32 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             s00_aw_node                                                                     |                                                 vpk180_ipb_smartconnect_0_0_bd_6c0a_sawn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized5 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized5 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized5 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__34 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             s00_b_node                                                                      |                                                  vpk180_ipb_smartconnect_0_0_bd_6c0a_sbn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized6 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized6 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized6 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__36 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             s00_r_node                                                                      |                                                  vpk180_ipb_smartconnect_0_0_bd_6c0a_srn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized7 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized7 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized7 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__38 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             s00_w_node                                                                      |                                                  vpk180_ipb_smartconnect_0_0_bd_6c0a_swn_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized8 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      5(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 (inst)                                                                      |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized8 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst_mi_handler                                                             |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized8 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 s_sc_xpm_cdc_async_rst_inst                                                 |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__40 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           switchboards                                                                      |                                        vpk180_ipb_smartconnect_0_0_switchboards_imp_NEJUL1 |     95(0.01%) |     95(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             ar_la_in_swbd                                                                   |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_arinsw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                                   vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             ar_la_out_swbd                                                                  |                                              vpk180_ipb_smartconnect_0_0_bd_6c0a_aroutsw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                   vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized0__1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             aw_la_in_swbd                                                                   |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_awinsw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                                      vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             aw_la_out_swbd                                                                  |                                              vpk180_ipb_smartconnect_0_0_bd_6c0a_awoutsw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                      vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             b_la_in_swbd                                                                    |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_binsw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                      vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized1 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             b_la_out_swbd                                                                   |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_boutsw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                      vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized2 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             i_nodes                                                                         |                                            vpk180_ipb_smartconnect_0_0_i_nodes_imp_143BZ59 |     79(0.01%) |     79(0.01%) | 0(0.00%) |    0(0.00%) |    160(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               i_ar_node                                                                     |                                                 vpk180_ipb_smartconnect_0_0_bd_6c0a_arni_0 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst                                                                        |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized9 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (inst)                                                                    |                            vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized9 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   inst_mi_handler                                                           |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized9 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (inst_mi_handler)                                                       |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized9 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_normal_area.inst_fifo_node_payld                                    |                                         vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_fifo_8 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                       gen_reg_fifo.inst_reg_fifo                                            |                                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo_9 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         (gen_reg_fifo.inst_reg_fifo)                                        |                                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo_9 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         gen_single_rank.inst_cntr                                           |                      vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_counter__parameterized0_10 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   s_sc_xpm_cdc_async_rst_inst                                               |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__42 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               i_aw_node                                                                     |                                                 vpk180_ipb_smartconnect_0_0_bd_6c0a_awni_0 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst                                                                        |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized10 |     10(0.01%) |     10(0.01%) | 0(0.00%) |    0(0.00%) |     20(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (inst)                                                                    |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized10 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   inst_mi_handler                                                           |                    vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized10 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     16(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (inst_mi_handler)                                                       |                    vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized10 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_normal_area.inst_fifo_node_payld                                    |                                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_fifo |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                       gen_reg_fifo.inst_reg_fifo                                            |                                       vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     14(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         (gen_reg_fifo.inst_reg_fifo)                                        |                                       vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     12(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         gen_single_rank.inst_cntr                                           |                       vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_counter__parameterized0_7 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   s_sc_xpm_cdc_async_rst_inst                                               |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__44 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               i_b_node                                                                      |                                                  vpk180_ipb_smartconnect_0_0_bd_6c0a_bni_0 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |     22(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst                                                                        |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized11 |     25(0.01%) |     25(0.01%) | 0(0.00%) |    0(0.00%) |     22(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (inst)                                                                    |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized11 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   inst_mi_handler                                                           |                    vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized11 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |      7(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (inst_mi_handler)                                                       |                    vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized11 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_normal_area.gen_fi_regulator.inst_fi_regulator                      |                                 vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_fi_regulator_5 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_normal_area.inst_fifo_node_payld                                    |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_fifo__parameterized0 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                       gen_reg_fifo.inst_reg_fifo                                            |                       vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo__parameterized0 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         (gen_reg_fifo.inst_reg_fifo)                                        |                       vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo__parameterized0 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         gen_single_rank.inst_cntr                                           |                       vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_counter__parameterized0_6 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   inst_si_handler                                                           |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_si_handler__parameterized6 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (inst_si_handler)                                                       |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_si_handler__parameterized6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter                 |                                   vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_arb_alg_rr_2 |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_si_handler.gen_request_counters.gen_req_counter[0].inst_req_counter |                       vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_counter__parameterized1_3 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_si_handler.gen_request_counters.gen_req_counter[1].inst_req_counter |                       vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_counter__parameterized1_4 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   s_sc_xpm_cdc_async_rst_inst                                               |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__46 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               i_r_node                                                                      |                                                  vpk180_ipb_smartconnect_0_0_bd_6c0a_rni_0 |     24(0.01%) |     24(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst                                                                        |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized12 |     24(0.01%) |     24(0.01%) | 0(0.00%) |    0(0.00%) |     54(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (inst)                                                                    |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized12 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   inst_mi_handler                                                           |                    vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized12 |      7(0.01%) |      7(0.01%) | 0(0.00%) |    0(0.00%) |     39(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (inst_mi_handler)                                                       |                    vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized12 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_normal_area.gen_fi_regulator.inst_fi_regulator                      |                                   vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_fi_regulator |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_normal_area.inst_fifo_node_payld                                    |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_fifo__parameterized1 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |     36(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                       gen_reg_fifo.inst_reg_fifo                                            |                       vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo__parameterized1 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |     36(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         (gen_reg_fifo.inst_reg_fifo)                                        |                       vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo__parameterized1 |      1(0.01%) |      1(0.01%) | 0(0.00%) |    0(0.00%) |     34(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         gen_single_rank.inst_cntr                                           |                       vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_counter__parameterized0_1 |      5(0.01%) |      5(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   inst_si_handler                                                           |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_si_handler__parameterized7 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |     11(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (inst_si_handler)                                                       |                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_si_handler__parameterized7 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter                 |                                     vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_arb_alg_rr |      9(0.01%) |      9(0.01%) | 0(0.00%) |    0(0.00%) |      4(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_si_handler.gen_request_counters.gen_req_counter[0].inst_req_counter |                         vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_counter__parameterized1 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_si_handler.gen_request_counters.gen_req_counter[1].inst_req_counter |                       vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_counter__parameterized1_0 |      4(0.01%) |      4(0.01%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   s_sc_xpm_cdc_async_rst_inst                                               |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__48 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               i_w_node                                                                      |                                                  vpk180_ipb_smartconnect_0_0_bd_6c0a_wni_0 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |     44(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 inst                                                                        |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized13 |     11(0.01%) |     11(0.01%) | 0(0.00%) |    0(0.00%) |     44(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   (inst)                                                                    |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_top__parameterized13 |      3(0.01%) |      3(0.01%) | 0(0.00%) |    0(0.00%) |      1(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   inst_mi_handler                                                           |                    vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized13 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     40(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     (inst_mi_handler)                                                       |                    vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_mi_handler__parameterized13 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                     gen_normal_area.inst_fifo_node_payld                                    |                           vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_fifo__parameterized2 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     38(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                       gen_reg_fifo.inst_reg_fifo                                            |                       vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo__parameterized2 |      8(0.01%) |      8(0.01%) | 0(0.00%) |    0(0.00%) |     38(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         (gen_reg_fifo.inst_reg_fifo)                                        |                       vpk180_ipb_smartconnect_0_0_sc_node_v1_0_17_reg_fifo__parameterized2 |      2(0.01%) |      2(0.01%) | 0(0.00%) |    0(0.00%) |     36(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                         gen_single_rank.inst_cntr                                           |                         vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_counter__parameterized0 |      6(0.01%) |      6(0.01%) | 0(0.00%) |    0(0.00%) |      2(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                   s_sc_xpm_cdc_async_rst_inst                                               |                                          vpk180_ipb_smartconnect_0_0_xpm_cdc_async_rst__50 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      3(0.01%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             r_la_in_swbd                                                                    |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_rinsw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                      vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized3 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             r_la_out_swbd                                                                   |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_routsw_0 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                      vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized4 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|                 gen_mi[0].inst_mux_payld                                                    |                             vpk180_ipb_smartconnect_0_0_sc_util_v1_0_4_mux__parameterized3 |     16(0.01%) |     16(0.01%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             w_la_in_swbd                                                                    |                                                vpk180_ipb_smartconnect_0_0_bd_6c0a_winsw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                      vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized5 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             w_la_out_swbd                                                                   |                                               vpk180_ipb_smartconnect_0_0_bd_6c0a_woutsw_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|               inst                                                                          |                      vpk180_ipb_smartconnect_0_0_sc_switchboard_v1_0_8_top__parameterized6 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|       versal_cips_0                                                                         |                                                                 vpk180_ipb_versal_cips_0_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|         U0                                                                                  |                                                                                    bd_16ab |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|           pspmc_0                                                                           |                                                                          bd_16ab_pspmc_0_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             (pspmc_0)                                                                       |                                                                          bd_16ab_pspmc_0_0 |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
|             U0                                                                              |                                                                         pspmc_v1_4_4_pspmc |      0(0.00%) |      0(0.00%) | 0(0.00%) |    0(0.00%) |      0(0.00%) |    0(0.00%) |  0(0.00%) | 0(0.00%) |   0(0.00%) |
+---------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+---------------+---------------+----------+-------------+---------------+-------------+-----------+----------+------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining


