Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024
| Date         : Tue Jun  2 22:26:54 2026
| Host         : runner-knmyf9bh-project-89695-concurrent-0-11rf7mo2 running 64-bit Ubuntu 22.04.5 LTS
| Command      : report_utilization -hierarchical -hierarchical_percentages -file /builds/atlas-tdaq-p2-firmware/global-trigger/gep-fw/bin/Baby/IW4_GCM3-v0.159.51-3B610E1/reports/hierarchical_utilization.txt
| Design       : global_top
| Device       : xcvp1802-vsva5601-1LP-e-S
| Speed File   : -1LP
| Design State : Routed
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Utilization Design Information

Table of Contents
-----------------
1. Utilization by Hierarchy

1. Utilization by Hierarchy
---------------------------

+-------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------+---------------+------------+------------+---------------+------------+-----------+-----------+------------+
|                                             Instance                                            |                                          Module                                          |   Total LUTs  |   Logic LUTs  |   LUTRAMs  |    SRLs    |      FFs      |   RAMB36   |   RAMB18  |    URAM   | DSP Blocks |
+-------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------+---------------+------------+------------+---------------+------------+-----------+-----------+------------+
| global_top                                                                                      |                                                                                    (top) | 102515(3.05%) | 101255(3.01%) | 856(0.05%) | 404(0.02%) | 150829(2.24%) | 272(5.50%) | 11(0.11%) | 33(1.29%) |   4(0.03%) |
|   (global_top)                                                                                  |                                                                                    (top) |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|   U_infra                                                                                       |                                                                                    infra |   9025(0.27%) |   8622(0.26%) |   0(0.00%) | 403(0.02%) |  17031(0.25%) |  82(1.66%) |  2(0.02%) |  0(0.00%) |   0(0.00%) |
|     U_infravp1802clocks                                                                         |                                                                      infra_vp1802_clocks |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       U_clock0                                                                                  |                                                                                    clock |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       U_clock1                                                                                  |                                                                    clock__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     gcm_system_bd                                                                               |                                                                       gcm_system_wrapper |   5275(0.16%) |   4872(0.14%) |   0(0.00%) | 403(0.02%) |  13535(0.20%) |  18(0.36%) |  2(0.02%) |  0(0.00%) |   0(0.00%) |
|       (gcm_system_bd)                                                                           |                                                                       gcm_system_wrapper |     60(0.01%) |     60(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       gcm_system_i                                                                              |                                                                               gcm_system |   5215(0.16%) |   4812(0.14%) |   0(0.00%) | 403(0.02%) |  13535(0.20%) |  18(0.36%) |  2(0.02%) |  0(0.00%) |   0(0.00%) |
|         (gcm_system_i)                                                                          |                                                                               gcm_system |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         axi_noc_0                                                                               |                                                                   gcm_system_axi_noc_0_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           inst                                                                                  |                                                           gcm_system_axi_noc_0_0_bd_f494 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (inst)                                                                              |                                                           gcm_system_axi_noc_0_0_bd_f494 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             M00_AXI_nsu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_M00_AXI_nsu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_M00_AXI_nsu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_M00_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             M01_AXI_nsu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_M01_AXI_nsu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_M01_AXI_nsu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_M01_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             M02_AXI_nsu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_M02_AXI_nsu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_M02_AXI_nsu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_M02_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             M03_AXI_nsu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_M03_AXI_nsu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_M03_AXI_nsu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_M03_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             M04_AXI_nsu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_M04_AXI_nsu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_M04_AXI_nsu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_M04_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             MC0_ddrc                                                                            |                                                gcm_system_axi_noc_0_0_bd_f494_MC0_ddrc_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               inst                                                                              |                                        gcm_system_axi_noc_0_0_bd_f494_MC0_ddrc_0_wrapper |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 noc_ddr4_phy                                                                    |                                                                   bd_f494_MC0_ddrc_0_phy |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                                                           bd_f494_MC0_ddrc_0_phy_wrapper |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                                                           bd_f494_MC0_ddrc_0_phy_wrapper |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     BANK_WRAPPER_INST0                                                          |                                                 advanced_io_wizard_phy_v1_0_bank_wrapper |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     BANK_WRAPPER_INST1                                                          |                                 advanced_io_wizard_phy_v1_0_bank_wrapper__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     BANK_WRAPPER_INST2                                                          |                                               advanced_io_wizard_phy_v1_0_bank_wrapper_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             S00_AXI_nmu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_S00_AXI_nmu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_S00_AXI_nmu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_S00_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             S01_AXI_nmu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_S01_AXI_nmu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_S01_AXI_nmu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_S01_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             S02_AXI_nmu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_S02_AXI_nmu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_S02_AXI_nmu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_S02_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             S03_AXI_nmu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_S03_AXI_nmu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_S03_AXI_nmu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_S03_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             S04_AXI_rpu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_S04_AXI_rpu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_S04_AXI_rpu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_S04_AXI_rpu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             S05_AXI_nmu                                                                         |                                             gcm_system_axi_noc_0_0_bd_f494_S05_AXI_nmu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               bd_f494_S05_AXI_nmu_0_top_INST                                                    |                                         gcm_system_axi_noc_0_0_bd_f494_S05_AXI_nmu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             const_0                                                                             |                                                 gcm_system_axi_noc_0_0_bd_f494_const_0_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         hier_clk_rst_fbr                                                                        |                                                             hier_clk_rst_fbr_imp_1L68KEM |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           clk_wizard_noc                                                                        |                                                              gcm_system_clk_wizard_noc_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             inst                                                                                |                                                  gcm_system_clk_wizard_noc_0_clk_wiz_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               clock_primitive_inst                                                              |                                           gcm_system_clk_wizard_noc_0_clocking_structure |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         hier_gcm_uart                                                                           |                                                                hier_gcm_uart_imp_1RE3TGF |    777(0.02%) |    740(0.02%) |   0(0.00%) |  37(0.01%) |    947(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           axi_bram_ctrl_0                                                                       |                                                             gcm_system_axi_bram_ctrl_0_0 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             U0                                                                                  |                                               gcm_system_axi_bram_ctrl_0_0_axi_bram_ctrl |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gext_inst.abcv4_0_ext_inst                                                        |                                           gcm_system_axi_bram_ctrl_0_0_axi_bram_ctrl_top |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 GEN_AXI4LITE.I_AXI_LITE                                                         |                                                    gcm_system_axi_bram_ctrl_0_0_axi_lite |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           axi_uartlite_0                                                                        |                                                              gcm_system_axi_uartlite_0_0 |     93(0.01%) |     75(0.01%) |   0(0.00%) |  18(0.01%) |    118(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             U0                                                                                  |                                                 gcm_system_axi_uartlite_0_0_axi_uartlite |     93(0.01%) |     75(0.01%) |   0(0.00%) |  18(0.01%) |    118(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               AXI_LITE_IPIF_I                                                                   |                                                gcm_system_axi_uartlite_0_0_axi_lite_ipif |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 I_SLAVE_ATTACHMENT                                                              |                                             gcm_system_axi_uartlite_0_0_slave_attachment |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (I_SLAVE_ATTACHMENT)                                                          |                                             gcm_system_axi_uartlite_0_0_slave_attachment |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |     21(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   I_DECODER                                                                     |                                              gcm_system_axi_uartlite_0_0_address_decoder |     19(0.01%) |     19(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (I_DECODER)                                                                 |                                              gcm_system_axi_uartlite_0_0_address_decoder |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I               |                                                    gcm_system_axi_uartlite_0_0_pselect_f |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I               |                                    gcm_system_axi_uartlite_0_0_pselect_f__parameterized1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               UARTLITE_CORE_I                                                                   |                                                gcm_system_axi_uartlite_0_0_uartlite_core |     69(0.01%) |     51(0.01%) |   0(0.00%) |  18(0.01%) |     88(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (UARTLITE_CORE_I)                                                               |                                                gcm_system_axi_uartlite_0_0_uartlite_core |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BAUD_RATE_I                                                                     |                                                     gcm_system_axi_uartlite_0_0_baudrate |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 UARTLITE_RX_I                                                                   |                                                  gcm_system_axi_uartlite_0_0_uartlite_rx |     35(0.01%) |     26(0.01%) |   0(0.00%) |   9(0.01%) |     50(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (UARTLITE_RX_I)                                                               |                                                  gcm_system_axi_uartlite_0_0_uartlite_rx |     13(0.01%) |     12(0.01%) |   0(0.00%) |   1(0.01%) |     40(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   INPUT_DOUBLE_REGS3                                                            |                                                     gcm_system_axi_uartlite_0_0_cdc_sync |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   SRL_FIFO_I                                                                    |                                                 gcm_system_axi_uartlite_0_0_srl_fifo_f_0 |     19(0.01%) |     11(0.01%) |   0(0.00%) |   8(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     I_SRL_FIFO_RBU_F                                                            |                                             gcm_system_axi_uartlite_0_0_srl_fifo_rbu_f_1 |     19(0.01%) |     11(0.01%) |   0(0.00%) |   8(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (I_SRL_FIFO_RBU_F)                                                        |                                             gcm_system_axi_uartlite_0_0_srl_fifo_rbu_f_1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       CNTR_INCR_DECR_ADDN_F_I                                                   |                                      gcm_system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       DYNSHREG_F_I                                                              |                                                 gcm_system_axi_uartlite_0_0_dynshreg_f_3 |     11(0.01%) |      3(0.01%) |   0(0.00%) |   8(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 UARTLITE_TX_I                                                                   |                                                  gcm_system_axi_uartlite_0_0_uartlite_tx |     29(0.01%) |     20(0.01%) |   0(0.00%) |   9(0.01%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (UARTLITE_TX_I)                                                               |                                                  gcm_system_axi_uartlite_0_0_uartlite_tx |      8(0.01%) |      7(0.01%) |   0(0.00%) |   1(0.01%) |     14(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   SRL_FIFO_I                                                                    |                                                   gcm_system_axi_uartlite_0_0_srl_fifo_f |     21(0.01%) |     13(0.01%) |   0(0.00%) |   8(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     I_SRL_FIFO_RBU_F                                                            |                                               gcm_system_axi_uartlite_0_0_srl_fifo_rbu_f |     21(0.01%) |     13(0.01%) |   0(0.00%) |   8(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (I_SRL_FIFO_RBU_F)                                                        |                                               gcm_system_axi_uartlite_0_0_srl_fifo_rbu_f |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       CNTR_INCR_DECR_ADDN_F_I                                                   |                                        gcm_system_axi_uartlite_0_0_cntr_incr_decr_addn_f |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       DYNSHREG_F_I                                                              |                                                   gcm_system_axi_uartlite_0_0_dynshreg_f |     10(0.01%) |      2(0.01%) |   0(0.00%) |   8(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           axi_uartlite_0_smc                                                                    |                                                          gcm_system_axi_uartlite_0_smc_0 |    558(0.02%) |    557(0.02%) |   0(0.00%) |   1(0.01%) |    699(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             inst                                                                                |                                                  gcm_system_axi_uartlite_0_smc_0_bd_326c |    558(0.02%) |    557(0.02%) |   0(0.00%) |   1(0.01%) |    699(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               clk_map                                                                           |                                      gcm_system_axi_uartlite_0_smc_0_clk_map_imp_1DRYCF0 |     12(0.01%) |     11(0.01%) |   0(0.00%) |   1(0.01%) |     22(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 psr_aclk                                                                        |                                       gcm_system_axi_uartlite_0_smc_0_bd_326c_psr_aclk_0 |     12(0.01%) |     11(0.01%) |   0(0.00%) |   1(0.01%) |     22(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U0                                                                            |                                           gcm_system_axi_uartlite_0_smc_0_proc_sys_reset |     12(0.01%) |     11(0.01%) |   0(0.00%) |   1(0.01%) |     22(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (U0)                                                                        |                                           gcm_system_axi_uartlite_0_smc_0_proc_sys_reset |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     EXT_LPF                                                                     |                                                      gcm_system_axi_uartlite_0_smc_0_lpf |      3(0.01%) |      2(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (EXT_LPF)                                                                 |                                                      gcm_system_axi_uartlite_0_smc_0_lpf |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       ACTIVE_LOW_AUX.ACT_LO_AUX                                                 |                                                 gcm_system_axi_uartlite_0_smc_0_cdc_sync |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     SEQ                                                                         |                                             gcm_system_axi_uartlite_0_smc_0_sequence_psr |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (SEQ)                                                                     |                                             gcm_system_axi_uartlite_0_smc_0_sequence_psr |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       SEQ_COUNTER                                                               |                                                  gcm_system_axi_uartlite_0_smc_0_upcnt_n |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               m00_exit_pipeline                                                                 |                             gcm_system_axi_uartlite_0_smc_0_m00_exit_pipeline_imp_L12NPJ |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m00_exit                                                                        |                                           gcm_system_axi_uartlite_0_smc_0_bd_326c_m00e_0 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                           gcm_system_axi_uartlite_0_smc_0_sc_exit_v1_0_16_top__xdcDup__1 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                           gcm_system_axi_uartlite_0_smc_0_sc_exit_v1_0_16_top__xdcDup__1 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     exit_inst                                                                   |                                  gcm_system_axi_uartlite_0_smc_0_sc_exit_v1_0_16_exit_25 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     xpm_cdc_async_rst_inst                                                      |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__12 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               m00_nodes                                                                         |                                     gcm_system_axi_uartlite_0_smc_0_m00_nodes_imp_7RO33F |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     27(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m00_ar_node                                                                     |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_m00arn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__xdcDup__1 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__xdcDup__1 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |                            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler_24 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__13 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m00_aw_node                                                                     |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_m00awn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized0__xdcDup__1 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized0__xdcDup__1 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized0_23 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__15 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m00_b_node                                                                      |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_m00bn_0 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized1__xdcDup__1 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized1__xdcDup__1 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized1_22 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__17 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m00_r_node                                                                      |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_m00rn_0 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized2__xdcDup__1 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized2__xdcDup__1 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized2_21 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__19 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m00_w_node                                                                      |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_m00wn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized3__xdcDup__1 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized3__xdcDup__1 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized3_20 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__21 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               m00_sc2axi                                                                        |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_m00s2a_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                 gcm_system_axi_uartlite_0_smc_0_sc_sc2axi_v1_0_10_top__1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               m01_exit_pipeline                                                                 |                             gcm_system_axi_uartlite_0_smc_0_m01_exit_pipeline_imp_PRSYMF |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m01_exit                                                                        |                                           gcm_system_axi_uartlite_0_smc_0_bd_326c_m01e_0 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                                      gcm_system_axi_uartlite_0_smc_0_sc_exit_v1_0_16_top |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                                      gcm_system_axi_uartlite_0_smc_0_sc_exit_v1_0_16_top |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     exit_inst                                                                   |                                     gcm_system_axi_uartlite_0_smc_0_sc_exit_v1_0_16_exit |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     xpm_cdc_async_rst_inst                                                      |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__23 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               m01_nodes                                                                         |                                    gcm_system_axi_uartlite_0_smc_0_m01_nodes_imp_11FVEFX |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     27(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m01_ar_node                                                                     |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_m01arn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__xdcDup__2 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__xdcDup__2 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |                            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler_19 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__24 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m01_aw_node                                                                     |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_m01awn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized0__xdcDup__2 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized0__xdcDup__2 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized0_18 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__26 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m01_b_node                                                                      |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_m01bn_0 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized1__xdcDup__2 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized1__xdcDup__2 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized1_17 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__28 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m01_r_node                                                                      |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_m01rn_0 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized2__xdcDup__2 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized2__xdcDup__2 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized2_16 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__30 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m01_w_node                                                                      |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_m01wn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized3__xdcDup__2 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized3__xdcDup__2 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |            gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized3_15 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__32 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               m01_sc2axi                                                                        |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_m01s2a_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                    gcm_system_axi_uartlite_0_smc_0_sc_sc2axi_v1_0_10_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               m02_exit_pipeline                                                                 |                             gcm_system_axi_uartlite_0_smc_0_m02_exit_pipeline_imp_S6VKLJ |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m02_exit                                                                        |                                           gcm_system_axi_uartlite_0_smc_0_bd_326c_m02e_0 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_exit_v1_0_16_top__parameterized0 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_exit_v1_0_16_top__parameterized0 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     exit_inst                                                                   |                     gcm_system_axi_uartlite_0_smc_0_sc_exit_v1_0_16_exit__parameterized0 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     xpm_cdc_async_rst_inst                                                      |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__34 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               m02_nodes                                                                         |                                    gcm_system_axi_uartlite_0_smc_0_m02_nodes_imp_1XIUNEU |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     27(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m02_ar_node                                                                     |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_m02arn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |                               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__35 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m02_aw_node                                                                     |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_m02awn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized0 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized0 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__37 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m02_b_node                                                                      |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_m02bn_0 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized1 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized1 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized1 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__39 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m02_r_node                                                                      |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_m02rn_0 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized2 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized2 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized2 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__41 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 m02_w_node                                                                      |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_m02wn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized3 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized3 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized3 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__43 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               m02_sc2axi                                                                        |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_m02s2a_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                    gcm_system_axi_uartlite_0_smc_0_sc_sc2axi_v1_0_10_top__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               s00_axi2sc                                                                        |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_s00a2s_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                    gcm_system_axi_uartlite_0_smc_0_sc_axi2sc_v1_0_10_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               s00_entry_pipeline                                                                |                           gcm_system_axi_uartlite_0_smc_0_s00_entry_pipeline_imp_1JQLSHW |    337(0.01%) |    337(0.01%) |   0(0.00%) |   0(0.00%) |    358(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 s00_mmu                                                                         |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_s00mmu_0 |    158(0.01%) |    158(0.01%) |   0(0.00%) |   0(0.00%) |    153(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                                       gcm_system_axi_uartlite_0_smc_0_sc_mmu_v1_0_14_top |    158(0.01%) |    158(0.01%) |   0(0.00%) |   0(0.00%) |    153(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                                       gcm_system_axi_uartlite_0_smc_0_sc_mmu_v1_0_14_top |     26(0.01%) |     26(0.01%) |   0(0.00%) |   0(0.00%) |     19(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     ar_reg_stall                                                                |             gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_axi_reg_stall__parameterized0 |     51(0.01%) |     51(0.01%) |   0(0.00%) |   0(0.00%) |     62(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     aw_reg_stall                                                                |          gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_axi_reg_stall__parameterized0_14 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     gen_endpoint.decerr_slave_inst                                              |                              gcm_system_axi_uartlite_0_smc_0_sc_mmu_v1_0_14_decerr_slave |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     21(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     gen_wroute_reg.wroute_split                                                 |                              gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_axi_splitter |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     xpm_cdc_async_rst_inst                                                      |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__45 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 s00_si_converter                                                                |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_s00sic_0 |    175(0.01%) |    175(0.01%) |   0(0.00%) |   0(0.00%) |    193(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                              gcm_system_axi_uartlite_0_smc_0_sc_si_converter_v1_0_14_top |    175(0.01%) |    175(0.01%) |   0(0.00%) |   0(0.00%) |    193(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                              gcm_system_axi_uartlite_0_smc_0_sc_si_converter_v1_0_14_top |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     gen_axilite_conv.axilite_conv_inst                                          |                     gcm_system_axi_uartlite_0_smc_0_sc_si_converter_v1_0_14_axilite_conv |    175(0.01%) |    175(0.01%) |   0(0.00%) |   0(0.00%) |    189(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     xpm_cdc_async_rst_inst                                                      |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__46 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 s00_transaction_regulator                                                       |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_s00tr_0 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                     gcm_system_axi_uartlite_0_smc_0_sc_transaction_regulator_v1_0_11_top |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                     gcm_system_axi_uartlite_0_smc_0_sc_transaction_regulator_v1_0_11_top |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     gen_endpoint.gen_r_singleorder.r_singleorder                                |             gcm_system_axi_uartlite_0_smc_0_sc_transaction_regulator_v1_0_11_singleorder |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     gen_endpoint.gen_w_singleorder.w_singleorder                                |          gcm_system_axi_uartlite_0_smc_0_sc_transaction_regulator_v1_0_11_singleorder_13 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     xpm_cdc_async_rst_inst                                                      |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__47 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               s00_nodes                                                                         |                                    gcm_system_axi_uartlite_0_smc_0_s00_nodes_imp_1PF15EM |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |     25(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 s00_ar_node                                                                     |                                           gcm_system_axi_uartlite_0_smc_0_bd_326c_sarn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized4 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized4 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized4 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__48 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 s00_aw_node                                                                     |                                           gcm_system_axi_uartlite_0_smc_0_bd_326c_sawn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized5 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized5 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized5 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__50 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 s00_b_node                                                                      |                                            gcm_system_axi_uartlite_0_smc_0_bd_326c_sbn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized6 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized6 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized6 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__52 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 s00_r_node                                                                      |                                            gcm_system_axi_uartlite_0_smc_0_bd_326c_srn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized7 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized7 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized7 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__54 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 s00_w_node                                                                      |                                            gcm_system_axi_uartlite_0_smc_0_bd_326c_swn_0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized8 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (inst)                                                                      |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized8 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst_mi_handler                                                             |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized8 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     s_sc_xpm_cdc_async_rst_inst                                                 |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__56 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               switchboards                                                                      |                                 gcm_system_axi_uartlite_0_smc_0_switchboards_imp_1EOQAVE |    104(0.01%) |    104(0.01%) |   0(0.00%) |   0(0.00%) |    186(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 ar_la_in_swbd                                                                   |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_arinsw_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                             gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top__1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 ar_la_out_swbd                                                                  |                                        gcm_system_axi_uartlite_0_smc_0_bd_326c_aroutsw_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |             gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top__parameterized0__1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 aw_la_in_swbd                                                                   |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_awinsw_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                                gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 aw_la_out_swbd                                                                  |                                        gcm_system_axi_uartlite_0_smc_0_bd_326c_awoutsw_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 b_la_in_swbd                                                                    |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_binsw_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 b_la_out_swbd                                                                   |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_boutsw_0 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top__parameterized2 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     gen_mi[0].inst_mux_payld                                                    |                       gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_mux__parameterized1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 i_nodes                                                                         |                                       gcm_system_axi_uartlite_0_smc_0_i_nodes_imp_VS5N02 |     82(0.01%) |     82(0.01%) |   0(0.00%) |   0(0.00%) |    186(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   i_ar_node                                                                     |                                           gcm_system_axi_uartlite_0_smc_0_bd_326c_arni_0 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst                                                                        |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized9 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (inst)                                                                    |                      gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized9 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       inst_mi_handler                                                           |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized9 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         (inst_mi_handler)                                                       |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized9 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_normal_area.inst_fifo_node_payld                                    |                                  gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_fifo_10 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                           gen_reg_fifo.inst_reg_fifo                                            |                              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo_11 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             (gen_reg_fifo.inst_reg_fifo)                                        |                              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo_11 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             gen_single_rank.inst_cntr                                           |                gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized0_12 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       s_sc_xpm_cdc_async_rst_inst                                               |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__58 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   i_aw_node                                                                     |                                           gcm_system_axi_uartlite_0_smc_0_bd_326c_awni_0 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst                                                                        |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized10 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (inst)                                                                    |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized10 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       inst_mi_handler                                                           |              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized10 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         (inst_mi_handler)                                                       |              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized10 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_normal_area.inst_fifo_node_payld                                    |                                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_fifo |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                           gen_reg_fifo.inst_reg_fifo                                            |                                 gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             (gen_reg_fifo.inst_reg_fifo)                                        |                                 gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             gen_single_rank.inst_cntr                                           |                 gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized0_9 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       s_sc_xpm_cdc_async_rst_inst                                               |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__60 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   i_b_node                                                                      |                                            gcm_system_axi_uartlite_0_smc_0_bd_326c_bni_0 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |     29(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst                                                                        |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized11 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |     29(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (inst)                                                                    |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized11 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       inst_mi_handler                                                           |              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized11 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         (inst_mi_handler)                                                       |              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized11 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_normal_area.gen_fi_regulator.inst_fi_regulator                      |                           gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_fi_regulator_7 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_normal_area.inst_fifo_node_payld                                    |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_fifo__parameterized0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                           gen_reg_fifo.inst_reg_fifo                                            |                 gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo__parameterized0 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             (gen_reg_fifo.inst_reg_fifo)                                        |                 gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo__parameterized0 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             gen_single_rank.inst_cntr                                           |                 gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized0_8 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       inst_si_handler                                                           |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_si_handler__parameterized6 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         (inst_si_handler)                                                       |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_si_handler__parameterized6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter                 |                             gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_arb_alg_rr_3 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_si_handler.gen_request_counters.gen_req_counter[0].inst_req_counter |                 gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized1_4 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_si_handler.gen_request_counters.gen_req_counter[1].inst_req_counter |                 gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized1_5 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_si_handler.gen_request_counters.gen_req_counter[2].inst_req_counter |                 gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized1_6 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       s_sc_xpm_cdc_async_rst_inst                                               |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__62 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   i_r_node                                                                      |                                            gcm_system_axi_uartlite_0_smc_0_bd_326c_rni_0 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     60(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst                                                                        |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized12 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     60(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (inst)                                                                    |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized12 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       inst_mi_handler                                                           |              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized12 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     40(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         (inst_mi_handler)                                                       |              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized12 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_normal_area.gen_fi_regulator.inst_fi_regulator                      |                             gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_fi_regulator |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_normal_area.inst_fifo_node_payld                                    |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_fifo__parameterized1 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |     37(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                           gen_reg_fifo.inst_reg_fifo                                            |                 gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo__parameterized1 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |     37(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             (gen_reg_fifo.inst_reg_fifo)                                        |                 gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo__parameterized1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     35(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             gen_single_rank.inst_cntr                                           |                 gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized0_2 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       inst_si_handler                                                           |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_si_handler__parameterized7 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         (inst_si_handler)                                                       |               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_si_handler__parameterized7 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_si_handler.gen_arbiter_rr_minimal_area.inst_arbiter                 |                               gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_arb_alg_rr |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_si_handler.gen_request_counters.gen_req_counter[0].inst_req_counter |                   gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized1 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_si_handler.gen_request_counters.gen_req_counter[1].inst_req_counter |                 gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized1_0 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_si_handler.gen_request_counters.gen_req_counter[2].inst_req_counter |                 gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized1_1 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       s_sc_xpm_cdc_async_rst_inst                                               |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__64 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   i_w_node                                                                      |                                            gcm_system_axi_uartlite_0_smc_0_bd_326c_wni_0 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |     49(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     inst                                                                        |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized13 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |     49(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (inst)                                                                    |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_top__parameterized13 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       inst_mi_handler                                                           |              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized13 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     45(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         (inst_mi_handler)                                                       |              gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_mi_handler__parameterized13 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         gen_normal_area.inst_fifo_node_payld                                    |                     gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_fifo__parameterized2 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     43(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                           gen_reg_fifo.inst_reg_fifo                                            |                 gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo__parameterized2 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     43(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             (gen_reg_fifo.inst_reg_fifo)                                        |                 gcm_system_axi_uartlite_0_smc_0_sc_node_v1_0_17_reg_fifo__parameterized2 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     41(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                             gen_single_rank.inst_cntr                                           |                   gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_counter__parameterized0 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       s_sc_xpm_cdc_async_rst_inst                                               |                                    gcm_system_axi_uartlite_0_smc_0_xpm_cdc_async_rst__66 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 r_la_in_swbd                                                                    |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_rinsw_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 r_la_out_swbd                                                                   |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_routsw_0 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top__parameterized4 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     gen_mi[0].inst_mux_payld                                                    |                       gcm_system_axi_uartlite_0_smc_0_sc_util_v1_0_4_mux__parameterized3 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 w_la_in_swbd                                                                    |                                          gcm_system_axi_uartlite_0_smc_0_bd_326c_winsw_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top__parameterized5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 w_la_out_swbd                                                                   |                                         gcm_system_axi_uartlite_0_smc_0_bd_326c_woutsw_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   inst                                                                          |                gcm_system_axi_uartlite_0_smc_0_sc_switchboard_v1_0_8_top__parameterized6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           axi_uartlite_1                                                                        |                                                              gcm_system_axi_uartlite_1_0 |     92(0.01%) |     74(0.01%) |   0(0.00%) |  18(0.01%) |    118(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             U0                                                                                  |                                                 gcm_system_axi_uartlite_1_0_axi_uartlite |     92(0.01%) |     74(0.01%) |   0(0.00%) |  18(0.01%) |    118(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               AXI_LITE_IPIF_I                                                                   |                                                gcm_system_axi_uartlite_1_0_axi_lite_ipif |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 I_SLAVE_ATTACHMENT                                                              |                                             gcm_system_axi_uartlite_1_0_slave_attachment |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (I_SLAVE_ATTACHMENT)                                                          |                                             gcm_system_axi_uartlite_1_0_slave_attachment |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |     21(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   I_DECODER                                                                     |                                              gcm_system_axi_uartlite_1_0_address_decoder |     19(0.01%) |     19(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (I_DECODER)                                                                 |                                              gcm_system_axi_uartlite_1_0_address_decoder |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I               |                                                    gcm_system_axi_uartlite_1_0_pselect_f |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I               |                                    gcm_system_axi_uartlite_1_0_pselect_f__parameterized1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               UARTLITE_CORE_I                                                                   |                                                gcm_system_axi_uartlite_1_0_uartlite_core |     68(0.01%) |     50(0.01%) |   0(0.00%) |  18(0.01%) |     88(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (UARTLITE_CORE_I)                                                               |                                                gcm_system_axi_uartlite_1_0_uartlite_core |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BAUD_RATE_I                                                                     |                                                     gcm_system_axi_uartlite_1_0_baudrate |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 UARTLITE_RX_I                                                                   |                                                  gcm_system_axi_uartlite_1_0_uartlite_rx |     34(0.01%) |     25(0.01%) |   0(0.00%) |   9(0.01%) |     50(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (UARTLITE_RX_I)                                                               |                                                  gcm_system_axi_uartlite_1_0_uartlite_rx |     13(0.01%) |     12(0.01%) |   0(0.00%) |   1(0.01%) |     40(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   INPUT_DOUBLE_REGS3                                                            |                                                     gcm_system_axi_uartlite_1_0_cdc_sync |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   SRL_FIFO_I                                                                    |                                                 gcm_system_axi_uartlite_1_0_srl_fifo_f_0 |     19(0.01%) |     11(0.01%) |   0(0.00%) |   8(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     I_SRL_FIFO_RBU_F                                                            |                                             gcm_system_axi_uartlite_1_0_srl_fifo_rbu_f_1 |     19(0.01%) |     11(0.01%) |   0(0.00%) |   8(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (I_SRL_FIFO_RBU_F)                                                        |                                             gcm_system_axi_uartlite_1_0_srl_fifo_rbu_f_1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       CNTR_INCR_DECR_ADDN_F_I                                                   |                                      gcm_system_axi_uartlite_1_0_cntr_incr_decr_addn_f_2 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       DYNSHREG_F_I                                                              |                                                 gcm_system_axi_uartlite_1_0_dynshreg_f_3 |     11(0.01%) |      3(0.01%) |   0(0.00%) |   8(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 UARTLITE_TX_I                                                                   |                                                  gcm_system_axi_uartlite_1_0_uartlite_tx |     28(0.01%) |     19(0.01%) |   0(0.00%) |   9(0.01%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (UARTLITE_TX_I)                                                               |                                                  gcm_system_axi_uartlite_1_0_uartlite_tx |      8(0.01%) |      7(0.01%) |   0(0.00%) |   1(0.01%) |     14(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   SRL_FIFO_I                                                                    |                                                   gcm_system_axi_uartlite_1_0_srl_fifo_f |     21(0.01%) |     13(0.01%) |   0(0.00%) |   8(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     I_SRL_FIFO_RBU_F                                                            |                                               gcm_system_axi_uartlite_1_0_srl_fifo_rbu_f |     21(0.01%) |     13(0.01%) |   0(0.00%) |   8(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (I_SRL_FIFO_RBU_F)                                                        |                                               gcm_system_axi_uartlite_1_0_srl_fifo_rbu_f |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       CNTR_INCR_DECR_ADDN_F_I                                                   |                                        gcm_system_axi_uartlite_1_0_cntr_incr_decr_addn_f |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       DYNSHREG_F_I                                                              |                                                   gcm_system_axi_uartlite_1_0_dynshreg_f |     10(0.01%) |      2(0.01%) |   0(0.00%) |   8(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           emb_mem_gen_0                                                                         |                                                               gcm_system_emb_mem_gen_0_0 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             inst                                                                                |                                           gcm_system_emb_mem_gen_0_0_emb_mem_gen_v1_0_10 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_xpm.gen_base.xpm_memory_base_inst                                             |                                               gcm_system_emb_mem_gen_0_0_xpm_memory_base |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         hier_noc_rdo                                                                            |                                                                  hier_noc_rdo_imp_TR5CPU |   4407(0.13%) |   4043(0.12%) |   0(0.00%) | 364(0.02%) |  12498(0.19%) |  16(0.32%) |  2(0.02%) |  0(0.00%) |   0(0.00%) |
|           ila_rdo_noc_0                                                                         |                                                               gcm_system_ila_rdo_noc_0_0 |   2205(0.07%) |   2023(0.06%) |   0(0.00%) | 182(0.01%) |   6249(0.09%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|             U0                                                                                  |                                                       gcm_system_ila_rdo_noc_0_0_bd_2b34 |   2205(0.07%) |   2023(0.06%) |   0(0.00%) | 182(0.01%) |   6249(0.09%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|               (U0)                                                                              |                                                       gcm_system_ila_rdo_noc_0_0_bd_2b34 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_cap_ctrl                                                                     |                                       gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_cap_ctrl_0 |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |     73(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                            gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |     73(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                            gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |     49(0.01%) |     49(0.01%) |   0(0.00%) |   0(0.00%) |     43(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_1                                                                      |                                    gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_case1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_2                                                                      |                                    gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_case2 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_3                                                                      |                                    gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_case3 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_4                                                                      |                                    gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_case4 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_5                                                                      |                                    gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_case5 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_6                                                                      |                                    gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_case6 |     14(0.01%) |     14(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_7                                                                      |                                    gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_case7 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_8                                                                      |                                    gcm_system_ila_rdo_noc_0_0_axis_cap_ctrl_v1_0_1_case8 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_stub                                                                     |                                       gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_dbg_stub_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                            gcm_system_ila_rdo_noc_0_0_axis_dbg_stub_v1_0_1_axis_dbg_stub |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_2                                                                   |                                     gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_dbg_sync_2_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                            gcm_system_ila_rdo_noc_0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                                 |                                                gcm_system_ila_rdo_noc_0_0_xpm_cdc_single |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_3                                                                   |                                     gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_dbg_sync_3_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            | gcm_system_ila_rdo_noc_0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0__xdcDup__1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1_2.xpm_cdc_array_single_inst                                           |                                          gcm_system_ila_rdo_noc_0_0_xpm_cdc_array_single |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_4                                                                   |                                     gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_dbg_sync_4_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |            gcm_system_ila_rdo_noc_0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1_2.xpm_cdc_array_single_inst                                           |                                       gcm_system_ila_rdo_noc_0_0_xpm_cdc_array_single__2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_5                                                                   |                                     gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_dbg_sync_5_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |            gcm_system_ila_rdo_noc_0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1_2.xpm_cdc_array_single_inst                                           |                          gcm_system_ila_rdo_noc_0_0_xpm_cdc_array_single__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_6                                                                   |                                     gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_dbg_sync_6_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |            gcm_system_ila_rdo_noc_0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1.xpm_cdc_async_rst_inst                                                |                                             gcm_system_ila_rdo_noc_0_0_xpm_cdc_async_rst |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_ila_intf                                                                     |                                       gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_ila_intf_0 |   1119(0.03%) |   1119(0.03%) |   0(0.00%) |   0(0.00%) |   1916(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (axis_ila_intf)                                                                 |                                       gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_ila_intf_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                            gcm_system_ila_rdo_noc_0_0_axis_ila_intf_v1_0_2_axis_ila_intf |   1119(0.03%) |   1119(0.03%) |   0(0.00%) |   0(0.00%) |   1916(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                            gcm_system_ila_rdo_noc_0_0_axis_ila_intf_v1_0_2_axis_ila_intf |    326(0.01%) |    326(0.01%) |   0(0.00%) |   0(0.00%) |   1407(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_clk_status                                                                  |                               gcm_system_ila_rdo_noc_0_0_axis_ila_intf_v1_0_2_clk_status |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (u_clk_status)                                                              |                               gcm_system_ila_rdo_noc_0_0_axis_ila_intf_v1_0_2_clk_status |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     14(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     axis_flag_0_sync_inst                                                       | gcm_system_ila_rdo_noc_0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (axis_flag_0_sync_inst)                                                   | gcm_system_ila_rdo_noc_0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       genblk1_3.xpm_cdc_single_inst                                             |                             gcm_system_ila_rdo_noc_0_0_xpm_cdc_single__parameterized0__2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     des_flag_0_sync_inst                                                        |            gcm_system_ila_rdo_noc_0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (des_flag_0_sync_inst)                                                    |            gcm_system_ila_rdo_noc_0_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       genblk1_3.xpm_cdc_single_inst                                             |                                gcm_system_ila_rdo_noc_0_0_xpm_cdc_single__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_core_reg                                                                    |                                gcm_system_ila_rdo_noc_0_0_axis_ila_intf_v1_0_2_reg_array |    783(0.02%) |    783(0.02%) |   0(0.00%) |   0(0.00%) |    489(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (u_core_reg)                                                                |                                gcm_system_ila_rdo_noc_0_0_axis_ila_intf_v1_0_2_reg_array |    780(0.02%) |    780(0.02%) |   0(0.00%) |   0(0.00%) |    413(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     u_done_sync                                                                 |                            gcm_system_ila_rdo_noc_0_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     76(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (u_done_sync)                                                             |                            gcm_system_ila_rdo_noc_0_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       genblk1_0.xpm_cdc_handshake_inst                                          |                                             gcm_system_ila_rdo_noc_0_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     76(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         (genblk1_0.xpm_cdc_handshake_inst)                                      |                                             gcm_system_ila_rdo_noc_0_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     72(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         xpm_cdc_single_dest2src_inst                                            |                                             gcm_system_ila_rdo_noc_0_0_xpm_cdc_single__5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         xpm_cdc_single_src2dest_inst                                            |                                             gcm_system_ila_rdo_noc_0_0_xpm_cdc_single__4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_ila_pp                                                                       |                                         gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1776(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (axis_ila_pp)                                                                   |                                         gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                gcm_system_ila_rdo_noc_0_0_axis_ila_pp_v1_0_2_axis_ila_pp |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1776(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_itct                                                                         |                                           gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_itct_0 |     42(0.01%) |     42(0.01%) |   0(0.00%) |   0(0.00%) |     37(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (axis_itct)                                                                     |                                           gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_itct_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                    gcm_system_ila_rdo_noc_0_0_axis_itct_v1_0_1_axis_itct |     42(0.01%) |     42(0.01%) |   0(0.00%) |   0(0.00%) |     37(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                    gcm_system_ila_rdo_noc_0_0_axis_itct_v1_0_1_axis_itct |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_mu_itct                                                                     |                                      gcm_system_ila_rdo_noc_0_0_axis_itct_v1_0_1_mu_itct |     42(0.01%) |     42(0.01%) |   0(0.00%) |   0(0.00%) |     37(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (u_mu_itct)                                                                 |                                      gcm_system_ila_rdo_noc_0_0_axis_itct_v1_0_1_mu_itct |     14(0.01%) |     14(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     u_cfg_en                                                                    |                                       gcm_system_ila_rdo_noc_0_0_axis_itct_v1_0_1_cfg_en |     29(0.01%) |     29(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mem                                                                          |                                            gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mem_0 |    296(0.01%) |    294(0.01%) |   0(0.00%) |   2(0.01%) |   1834(0.03%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                 (axis_mem)                                                                      |                                            gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mem_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                      gcm_system_ila_rdo_noc_0_0_axis_mem_v1_0_2_axis_mem |    296(0.01%) |    294(0.01%) |   0(0.00%) |   2(0.01%) |   1834(0.03%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                      gcm_system_ila_rdo_noc_0_0_axis_mem_v1_0_2_axis_mem |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |   1186(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_generic_memrd                                                               |                                 gcm_system_ila_rdo_noc_0_0_axis_mem_v1_0_2_generic_memrd |    147(0.01%) |    145(0.01%) |   0(0.00%) |   2(0.01%) |    338(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_trace_mem                                                                   |                                           gcm_system_ila_rdo_noc_0_0_axis_mem_v1_0_2_mem |    148(0.01%) |    148(0.01%) |   0(0.00%) |   0(0.00%) |    308(0.01%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                     (u_trace_mem)                                                               |                                           gcm_system_ila_rdo_noc_0_0_axis_mem_v1_0_2_mem |    148(0.01%) |    148(0.01%) |   0(0.00%) |   0(0.00%) |    308(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     BRAM.XPM_1.sdpram                                                           |                                             gcm_system_ila_rdo_noc_0_0_xpm_memory_sdpram |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                       xpm_memory_base_inst                                                      |                                               gcm_system_ila_rdo_noc_0_0_xpm_memory_base |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                   xpm_cdc_en_deep_strg_o                                                        |                                             gcm_system_ila_rdo_noc_0_0_xpm_cdc_single__6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu0_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu0_0_0 |      8(0.01%) |      6(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu |      8(0.01%) |      6(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_25 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic_26 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu10_0                                                                       |                                         gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu10_0_0 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__7 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__7 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_23 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic_24 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu11_0                                                                       |                                         gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu11_0_0 |     10(0.01%) |      8(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__6 |     10(0.01%) |      8(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__6 |      7(0.01%) |      6(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_21 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic_22 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu1_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu1_0_0 |    215(0.01%) |    150(0.01%) |   0(0.00%) |  65(0.01%) |    198(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized0 |    215(0.01%) |    150(0.01%) |   0(0.00%) |  65(0.01%) |    198(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized0 |     38(0.01%) |     37(0.01%) |   0(0.00%) |   1(0.01%) |     69(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[0].u_allx                                                        |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized0_16 |     27(0.01%) |     11(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[1].u_allx                                                        |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized0_17 |     25(0.01%) |      9(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[2].u_allx                                                        |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized0_18 |     28(0.01%) |     12(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[3].u_allx                                                        |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized0_19 |     29(0.01%) |     13(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |            gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_20 |     69(0.01%) |     69(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu2_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu2_0_0 |     37(0.01%) |     28(0.01%) |   0(0.00%) |   9(0.01%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized1 |     37(0.01%) |     28(0.01%) |   0(0.00%) |   9(0.01%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized1 |     10(0.01%) |      9(0.01%) |   0(0.00%) |   1(0.01%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized1_14 |     14(0.01%) |      6(0.01%) |   0(0.00%) |   8(0.01%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |            gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_15 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu3_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu3_0_0 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__5 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__5 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_12 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic_13 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu4_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu4_0_0 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__4 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__4 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_10 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic_11 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu5_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu5_0_0 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__3 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__3 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                         gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_8 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                             gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic_9 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu6_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu6_0_0 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__2 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__2 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                         gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_6 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                             gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic_7 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu7_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu7_0_0 |    216(0.01%) |    151(0.01%) |   0(0.00%) |  65(0.01%) |    198(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |    216(0.01%) |    151(0.01%) |   0(0.00%) |  65(0.01%) |    198(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |     39(0.01%) |     38(0.01%) |   0(0.00%) |   1(0.01%) |     69(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[0].u_allx                                                        |                           gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized0 |     28(0.01%) |     12(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[1].u_allx                                                        |                         gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized0_3 |     31(0.01%) |     15(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[2].u_allx                                                        |                         gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized0_4 |     28(0.01%) |     12(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[3].u_allx                                                        |                         gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized0_5 |     25(0.01%) |      9(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |               gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0 |     69(0.01%) |     69(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu8_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu8_0_0 |     35(0.01%) |     26(0.01%) |   0(0.00%) |   9(0.01%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |     35(0.01%) |     26(0.01%) |   0(0.00%) |   9(0.01%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |     10(0.01%) |      9(0.01%) |   0(0.00%) |   1(0.01%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                           gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx__parameterized1 |     12(0.01%) |      4(0.01%) |   0(0.00%) |   8(0.01%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |               gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu9_0                                                                        |                                          gcm_system_ila_rdo_noc_0_0_bd_2b34_axis_mu9_0_0 |     10(0.01%) |      8(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__1 |     10(0.01%) |      8(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__1 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                           gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                               gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_allx_carry_logic |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               cc_axis_mu0                                                                       |                                         gcm_system_ila_rdo_noc_0_0_bd_2b34_cc_axis_mu0_0 |     11(0.01%) |      8(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized2 |     11(0.01%) |      8(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized2 |      7(0.01%) |      6(0.01%) |   0(0.00%) |   1(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_mu_eq_2 |      4(0.01%) |      2(0.01%) |   0(0.00%) |   2(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               cc_axis_mu1                                                                       |                                         gcm_system_ila_rdo_noc_0_0_bd_2b34_cc_axis_mu1_0 |     12(0.01%) |      9(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |     12(0.01%) |      9(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |      8(0.01%) |      7(0.01%) |   0(0.00%) |   1(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_mu_eq_1 |      4(0.01%) |      2(0.01%) |   0(0.00%) |   2(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               cc_axis_mu2                                                                       |                                         gcm_system_ila_rdo_noc_0_0_bd_2b34_cc_axis_mu2_0 |     14(0.01%) |     11(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |     14(0.01%) |     11(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |      9(0.01%) |      8(0.01%) |   0(0.00%) |   1(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_mu_eq_0 |      5(0.01%) |      3(0.01%) |   0(0.00%) |   2(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               cc_axis_mu3                                                                       |                                         gcm_system_ila_rdo_noc_0_0_bd_2b34_cc_axis_mu3_0 |     13(0.01%) |     10(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |     13(0.01%) |     10(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |      8(0.01%) |      7(0.01%) |   0(0.00%) |   1(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                                          gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_mu_eq |      5(0.01%) |      3(0.01%) |   0(0.00%) |   2(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               tc_axis_mu0                                                                       |                                         gcm_system_ila_rdo_noc_0_0_bd_2b34_tc_axis_mu0_0 |     13(0.01%) |      9(0.01%) |   0(0.00%) |   4(0.01%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized3 |     13(0.01%) |      9(0.01%) |   0(0.00%) |   4(0.01%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                        gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_axis_mu__parameterized3 |      8(0.01%) |      7(0.01%) |   0(0.00%) |   1(0.01%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                          gcm_system_ila_rdo_noc_0_0_axis_mu_v1_0_1_mu_eq__parameterized0 |      6(0.01%) |      3(0.01%) |   0(0.00%) |   3(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           ila_rdo_noc_1                                                                         |                                                               gcm_system_ila_rdo_noc_1_0 |   2202(0.07%) |   2020(0.06%) |   0(0.00%) | 182(0.01%) |   6249(0.09%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|             U0                                                                                  |                                                       gcm_system_ila_rdo_noc_1_0_bd_eb65 |   2202(0.07%) |   2020(0.06%) |   0(0.00%) | 182(0.01%) |   6249(0.09%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|               (U0)                                                                              |                                                       gcm_system_ila_rdo_noc_1_0_bd_eb65 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_cap_ctrl                                                                     |                                       gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_cap_ctrl_0 |    119(0.01%) |    119(0.01%) |   0(0.00%) |   0(0.00%) |     73(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                            gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |    119(0.01%) |    119(0.01%) |   0(0.00%) |   0(0.00%) |     73(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                            gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_axis_cap_ctrl |     49(0.01%) |     49(0.01%) |   0(0.00%) |   0(0.00%) |     43(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_1                                                                      |                                    gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_case1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_2                                                                      |                                    gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_case2 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_3                                                                      |                                    gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_case3 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_4                                                                      |                                    gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_case4 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_5                                                                      |                                    gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_case5 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_6                                                                      |                                    gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_case6 |     14(0.01%) |     14(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_7                                                                      |                                    gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_case7 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   U_CASE_8                                                                      |                                    gcm_system_ila_rdo_noc_1_0_axis_cap_ctrl_v1_0_1_case8 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_stub                                                                     |                                       gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_dbg_stub_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                            gcm_system_ila_rdo_noc_1_0_axis_dbg_stub_v1_0_1_axis_dbg_stub |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_2                                                                   |                                     gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_dbg_sync_2_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                            gcm_system_ila_rdo_noc_1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1_3.xpm_cdc_single_inst                                                 |                                                gcm_system_ila_rdo_noc_1_0_xpm_cdc_single |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_3                                                                   |                                     gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_dbg_sync_3_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            | gcm_system_ila_rdo_noc_1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0__xdcDup__1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1_2.xpm_cdc_array_single_inst                                           |                                          gcm_system_ila_rdo_noc_1_0_xpm_cdc_array_single |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_4                                                                   |                                     gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_dbg_sync_4_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |            gcm_system_ila_rdo_noc_1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1_2.xpm_cdc_array_single_inst                                           |                                       gcm_system_ila_rdo_noc_1_0_xpm_cdc_array_single__2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_5                                                                   |                                     gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_dbg_sync_5_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |            gcm_system_ila_rdo_noc_1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1_2.xpm_cdc_array_single_inst                                           |                          gcm_system_ila_rdo_noc_1_0_xpm_cdc_array_single__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_dbg_sync_6                                                                   |                                     gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_dbg_sync_6_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |            gcm_system_ila_rdo_noc_1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   genblk1.xpm_cdc_async_rst_inst                                                |                                             gcm_system_ila_rdo_noc_1_0_xpm_cdc_async_rst |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_ila_intf                                                                     |                                       gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_ila_intf_0 |   1118(0.03%) |   1118(0.03%) |   0(0.00%) |   0(0.00%) |   1916(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (axis_ila_intf)                                                                 |                                       gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_ila_intf_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                            gcm_system_ila_rdo_noc_1_0_axis_ila_intf_v1_0_2_axis_ila_intf |   1118(0.03%) |   1118(0.03%) |   0(0.00%) |   0(0.00%) |   1916(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                            gcm_system_ila_rdo_noc_1_0_axis_ila_intf_v1_0_2_axis_ila_intf |    326(0.01%) |    326(0.01%) |   0(0.00%) |   0(0.00%) |   1407(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_clk_status                                                                  |                               gcm_system_ila_rdo_noc_1_0_axis_ila_intf_v1_0_2_clk_status |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     20(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (u_clk_status)                                                              |                               gcm_system_ila_rdo_noc_1_0_axis_ila_intf_v1_0_2_clk_status |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     14(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     axis_flag_0_sync_inst                                                       | gcm_system_ila_rdo_noc_1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (axis_flag_0_sync_inst)                                                   | gcm_system_ila_rdo_noc_1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3__xdcDup__1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       genblk1_3.xpm_cdc_single_inst                                             |                             gcm_system_ila_rdo_noc_1_0_xpm_cdc_single__parameterized0__2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     des_flag_0_sync_inst                                                        |            gcm_system_ila_rdo_noc_1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (des_flag_0_sync_inst)                                                    |            gcm_system_ila_rdo_noc_1_0_axis_dbg_sync_v1_0_1_axis_dbg_sync__parameterized3 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       genblk1_3.xpm_cdc_single_inst                                             |                                gcm_system_ila_rdo_noc_1_0_xpm_cdc_single__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_core_reg                                                                    |                                gcm_system_ila_rdo_noc_1_0_axis_ila_intf_v1_0_2_reg_array |    785(0.02%) |    785(0.02%) |   0(0.00%) |   0(0.00%) |    489(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (u_core_reg)                                                                |                                gcm_system_ila_rdo_noc_1_0_axis_ila_intf_v1_0_2_reg_array |    782(0.02%) |    782(0.02%) |   0(0.00%) |   0(0.00%) |    413(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     u_done_sync                                                                 |                            gcm_system_ila_rdo_noc_1_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     76(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       (u_done_sync)                                                             |                            gcm_system_ila_rdo_noc_1_0_axis_ila_intf_v1_0_2_axis_dbg_sync |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                       genblk1_0.xpm_cdc_handshake_inst                                          |                                             gcm_system_ila_rdo_noc_1_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     76(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         (genblk1_0.xpm_cdc_handshake_inst)                                      |                                             gcm_system_ila_rdo_noc_1_0_xpm_cdc_handshake |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     72(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         xpm_cdc_single_dest2src_inst                                            |                                             gcm_system_ila_rdo_noc_1_0_xpm_cdc_single__5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                         xpm_cdc_single_src2dest_inst                                            |                                             gcm_system_ila_rdo_noc_1_0_xpm_cdc_single__4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_ila_pp                                                                       |                                         gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1776(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (axis_ila_pp)                                                                   |                                         gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_ila_pp_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                gcm_system_ila_rdo_noc_1_0_axis_ila_pp_v1_0_2_axis_ila_pp |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1776(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_itct                                                                         |                                           gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_itct_0 |     43(0.01%) |     43(0.01%) |   0(0.00%) |   0(0.00%) |     37(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (axis_itct)                                                                     |                                           gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_itct_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                    gcm_system_ila_rdo_noc_1_0_axis_itct_v1_0_1_axis_itct |     43(0.01%) |     43(0.01%) |   0(0.00%) |   0(0.00%) |     37(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                    gcm_system_ila_rdo_noc_1_0_axis_itct_v1_0_1_axis_itct |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_mu_itct                                                                     |                                      gcm_system_ila_rdo_noc_1_0_axis_itct_v1_0_1_mu_itct |     43(0.01%) |     43(0.01%) |   0(0.00%) |   0(0.00%) |     37(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     (u_mu_itct)                                                                 |                                      gcm_system_ila_rdo_noc_1_0_axis_itct_v1_0_1_mu_itct |     14(0.01%) |     14(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     u_cfg_en                                                                    |                                       gcm_system_ila_rdo_noc_1_0_axis_itct_v1_0_1_cfg_en |     29(0.01%) |     29(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mem                                                                          |                                            gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mem_0 |    296(0.01%) |    294(0.01%) |   0(0.00%) |   2(0.01%) |   1834(0.03%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                 (axis_mem)                                                                      |                                            gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mem_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                      gcm_system_ila_rdo_noc_1_0_axis_mem_v1_0_2_axis_mem |    296(0.01%) |    294(0.01%) |   0(0.00%) |   2(0.01%) |   1834(0.03%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                      gcm_system_ila_rdo_noc_1_0_axis_mem_v1_0_2_axis_mem |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |   1186(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_generic_memrd                                                               |                                 gcm_system_ila_rdo_noc_1_0_axis_mem_v1_0_2_generic_memrd |    147(0.01%) |    145(0.01%) |   0(0.00%) |   2(0.01%) |    338(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   u_trace_mem                                                                   |                                           gcm_system_ila_rdo_noc_1_0_axis_mem_v1_0_2_mem |    148(0.01%) |    148(0.01%) |   0(0.00%) |   0(0.00%) |    308(0.01%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                     (u_trace_mem)                                                               |                                           gcm_system_ila_rdo_noc_1_0_axis_mem_v1_0_2_mem |    148(0.01%) |    148(0.01%) |   0(0.00%) |   0(0.00%) |    308(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                     BRAM.XPM_1.sdpram                                                           |                                             gcm_system_ila_rdo_noc_1_0_xpm_memory_sdpram |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                       xpm_memory_base_inst                                                      |                                               gcm_system_ila_rdo_noc_1_0_xpm_memory_base |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|                   xpm_cdc_en_deep_strg_o                                                        |                                             gcm_system_ila_rdo_noc_1_0_xpm_cdc_single__6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu0_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu0_0_0 |     10(0.01%) |      8(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu |     10(0.01%) |      8(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_25 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic_26 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu10_0                                                                       |                                         gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu10_0_0 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__7 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__7 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_23 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic_24 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu11_0                                                                       |                                         gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu11_0_0 |     11(0.01%) |      9(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__6 |     11(0.01%) |      9(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__6 |      7(0.01%) |      6(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_21 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic_22 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu1_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu1_0_0 |    214(0.01%) |    149(0.01%) |   0(0.00%) |  65(0.01%) |    198(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized0 |    214(0.01%) |    149(0.01%) |   0(0.00%) |  65(0.01%) |    198(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized0 |     37(0.01%) |     36(0.01%) |   0(0.00%) |   1(0.01%) |     69(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[0].u_allx                                                        |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized0_16 |     26(0.01%) |     10(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[1].u_allx                                                        |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized0_17 |     26(0.01%) |     10(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[2].u_allx                                                        |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized0_18 |     29(0.01%) |     13(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[3].u_allx                                                        |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized0_19 |     29(0.01%) |     13(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |            gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0_20 |     69(0.01%) |     69(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu2_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu2_0_0 |     36(0.01%) |     27(0.01%) |   0(0.00%) |   9(0.01%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized1 |     36(0.01%) |     27(0.01%) |   0(0.00%) |   9(0.01%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized1 |     10(0.01%) |      9(0.01%) |   0(0.00%) |   1(0.01%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized1_14 |     14(0.01%) |      6(0.01%) |   0(0.00%) |   8(0.01%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |            gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1_15 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu3_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu3_0_0 |     10(0.01%) |      8(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__5 |     10(0.01%) |      8(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__5 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_12 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic_13 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu4_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu4_0_0 |     11(0.01%) |      9(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__4 |     11(0.01%) |      9(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__4 |      7(0.01%) |      6(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_10 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                            gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic_11 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu5_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu5_0_0 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__3 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__3 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                         gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_8 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                             gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic_9 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu6_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu6_0_0 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__2 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__2 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                         gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_6 |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                             gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic_7 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu7_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu7_0_0 |    215(0.01%) |    150(0.01%) |   0(0.00%) |  65(0.01%) |    198(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |    215(0.01%) |    150(0.01%) |   0(0.00%) |  65(0.01%) |    198(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized0__1 |     39(0.01%) |     38(0.01%) |   0(0.00%) |   1(0.01%) |     69(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[0].u_allx                                                        |                           gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized0 |     28(0.01%) |     12(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[1].u_allx                                                        |                         gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized0_3 |     28(0.01%) |     12(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[2].u_allx                                                        |                         gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized0_4 |     27(0.01%) |     11(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_FULL[3].u_allx                                                        |                         gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized0_5 |     27(0.01%) |     11(0.01%) |   0(0.00%) |  16(0.01%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |               gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized0 |     69(0.01%) |     69(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu8_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu8_0_0 |     34(0.01%) |     25(0.01%) |   0(0.00%) |   9(0.01%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |     34(0.01%) |     25(0.01%) |   0(0.00%) |   9(0.01%) |     30(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized1__1 |     10(0.01%) |      9(0.01%) |   0(0.00%) |   1(0.01%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                           gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx__parameterized1 |     13(0.01%) |      5(0.01%) |   0(0.00%) |   8(0.01%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |               gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic__parameterized1 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               axis_mu9_0                                                                        |                                          gcm_system_ila_rdo_noc_1_0_bd_eb65_axis_mu9_0_0 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__1 |      9(0.01%) |      7(0.01%) |   0(0.00%) |   2(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__1 |      6(0.01%) |      5(0.01%) |   0(0.00%) |   1(0.01%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.L2_NFULL.u_allx                                                          |                                           gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   ALLX.u_allx_carry                                                             |                               gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_allx_carry_logic |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               cc_axis_mu0                                                                       |                                         gcm_system_ila_rdo_noc_1_0_bd_eb65_cc_axis_mu0_0 |     13(0.01%) |     10(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized2 |     13(0.01%) |     10(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized2 |      9(0.01%) |      8(0.01%) |   0(0.00%) |   1(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_mu_eq_2 |      5(0.01%) |      3(0.01%) |   0(0.00%) |   2(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               cc_axis_mu1                                                                       |                                         gcm_system_ila_rdo_noc_1_0_bd_eb65_cc_axis_mu1_0 |     11(0.01%) |      8(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |     11(0.01%) |      8(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized2__3 |      7(0.01%) |      6(0.01%) |   0(0.00%) |   1(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_mu_eq_1 |      5(0.01%) |      3(0.01%) |   0(0.00%) |   2(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               cc_axis_mu2                                                                       |                                         gcm_system_ila_rdo_noc_1_0_bd_eb65_cc_axis_mu2_0 |     13(0.01%) |     10(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |     13(0.01%) |     10(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized2__2 |      8(0.01%) |      7(0.01%) |   0(0.00%) |   1(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_mu_eq_0 |      5(0.01%) |      3(0.01%) |   0(0.00%) |   2(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               cc_axis_mu3                                                                       |                                         gcm_system_ila_rdo_noc_1_0_bd_eb65_cc_axis_mu3_0 |     13(0.01%) |     10(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |     13(0.01%) |     10(0.01%) |   0(0.00%) |   3(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                     gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized2__1 |      9(0.01%) |      8(0.01%) |   0(0.00%) |   1(0.01%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                                          gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_mu_eq |      5(0.01%) |      3(0.01%) |   0(0.00%) |   2(0.01%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               tc_axis_mu0                                                                       |                                         gcm_system_ila_rdo_noc_1_0_bd_eb65_tc_axis_mu0_0 |     14(0.01%) |     10(0.01%) |   0(0.00%) |   4(0.01%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 inst                                                                            |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized3 |     14(0.01%) |     10(0.01%) |   0(0.00%) |   4(0.01%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   (inst)                                                                        |                        gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_axis_mu__parameterized3 |      9(0.01%) |      8(0.01%) |   0(0.00%) |   1(0.01%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                   MU_EQ.L2_NFULL.u_eq                                                           |                          gcm_system_ila_rdo_noc_1_0_axis_mu_v1_0_1_mu_eq__parameterized0 |      7(0.01%) |      4(0.01%) |   0(0.00%) |   3(0.01%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rdo_noc                                                                               |                                                                     gcm_system_rdo_noc_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             inst                                                                                |                                                             gcm_system_rdo_noc_0_bd_97d3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (inst)                                                                            |                                                             gcm_system_rdo_noc_0_bd_97d3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               M00_AXIS_nsu                                                                      |                                              gcm_system_rdo_noc_0_bd_97d3_M00_AXIS_nsu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 bd_97d3_M00_AXIS_nsu_0_top_INST                                                 |                                          gcm_system_rdo_noc_0_bd_97d3_M00_AXIS_nsu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               M01_AXIS_nsu                                                                      |                                              gcm_system_rdo_noc_0_bd_97d3_M01_AXIS_nsu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 bd_97d3_M01_AXIS_nsu_0_top_INST                                                 |                                          gcm_system_rdo_noc_0_bd_97d3_M01_AXIS_nsu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               S00_AXIS_nmu                                                                      |                                              gcm_system_rdo_noc_0_bd_97d3_S00_AXIS_nmu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 bd_97d3_S00_AXIS_nmu_0_top_INST                                                 |                                          gcm_system_rdo_noc_0_bd_97d3_S00_AXIS_nmu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               S01_AXIS_nmu                                                                      |                                              gcm_system_rdo_noc_0_bd_97d3_S01_AXIS_nmu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 bd_97d3_S01_AXIS_nmu_0_top_INST                                                 |                                          gcm_system_rdo_noc_0_bd_97d3_S01_AXIS_nmu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               const_0                                                                           |                                                   gcm_system_rdo_noc_0_bd_97d3_const_0_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         proc_sys_reset_0                                                                        |                                                            gcm_system_proc_sys_reset_0_0 |     14(0.01%) |     13(0.01%) |   0(0.00%) |   1(0.01%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           U0                                                                                    |                                             gcm_system_proc_sys_reset_0_0_proc_sys_reset |     14(0.01%) |     13(0.01%) |   0(0.00%) |   1(0.01%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (U0)                                                                                |                                             gcm_system_proc_sys_reset_0_0_proc_sys_reset |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     17(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             EXT_LPF                                                                             |                                                        gcm_system_proc_sys_reset_0_0_lpf |      5(0.01%) |      4(0.01%) |   0(0.00%) |   1(0.01%) |     19(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (EXT_LPF)                                                                         |                                                        gcm_system_proc_sys_reset_0_0_lpf |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               ACTIVE_LOW_AUX.ACT_LO_AUX                                                         |                                                   gcm_system_proc_sys_reset_0_0_cdc_sync |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               ACTIVE_LOW_EXT.ACT_LO_EXT                                                         |                                                 gcm_system_proc_sys_reset_0_0_cdc_sync_0 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             SEQ                                                                                 |                                               gcm_system_proc_sys_reset_0_0_sequence_psr |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (SEQ)                                                                             |                                               gcm_system_proc_sys_reset_0_0_sequence_psr |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               SEQ_COUNTER                                                                       |                                                    gcm_system_proc_sys_reset_0_0_upcnt_n |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         proc_sys_reset_1                                                                        |                                                            gcm_system_proc_sys_reset_1_0 |     17(0.01%) |     16(0.01%) |   0(0.00%) |   1(0.01%) |     39(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           U0                                                                                    |                                             gcm_system_proc_sys_reset_1_0_proc_sys_reset |     17(0.01%) |     16(0.01%) |   0(0.00%) |   1(0.01%) |     39(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (U0)                                                                                |                                             gcm_system_proc_sys_reset_1_0_proc_sys_reset |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             EXT_LPF                                                                             |                                                        gcm_system_proc_sys_reset_1_0_lpf |      5(0.01%) |      4(0.01%) |   0(0.00%) |   1(0.01%) |     19(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (EXT_LPF)                                                                         |                                                        gcm_system_proc_sys_reset_1_0_lpf |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               ACTIVE_LOW_AUX.ACT_LO_AUX                                                         |                                                   gcm_system_proc_sys_reset_1_0_cdc_sync |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               ACTIVE_LOW_EXT.ACT_LO_EXT                                                         |                                                 gcm_system_proc_sys_reset_1_0_cdc_sync_0 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             SEQ                                                                                 |                                               gcm_system_proc_sys_reset_1_0_sequence_psr |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (SEQ)                                                                             |                                               gcm_system_proc_sys_reset_1_0_sequence_psr |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               SEQ_COUNTER                                                                       |                                                    gcm_system_proc_sys_reset_1_0_upcnt_n |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         versal_cips_0                                                                           |                                                               gcm_system_versal_cips_0_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           U0                                                                                    |                                                                                  bd_94f0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             pspmc_0                                                                             |                                                                        bd_94f0_pspmc_0_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (pspmc_0)                                                                         |                                                                        bd_94f0_pspmc_0_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               U0                                                                                |                                                                       pspmc_v1_4_4_pspmc |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     ipb_axi_inst_IN_SLR0                                                                        |                                                                   ipbus_transport_axi_if |    454(0.01%) |    454(0.01%) |   0(0.00%) |   0(0.00%) |    519(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       ram_to_trans                                                                              |                                                              ipbus_transport_ram_if_1223 |    116(0.01%) |    116(0.01%) |   0(0.00%) |   0(0.00%) |    121(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (ram_to_trans)                                                                          |                                                              ipbus_transport_ram_if_1223 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |     79(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         multibuffer_if                                                                          |                                                      ipbus_transport_multibuffer_if_1233 |     76(0.01%) |     76(0.01%) |   0(0.00%) |   0(0.00%) |     42(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (multibuffer_if)                                                                      |                                                      ipbus_transport_multibuffer_if_1233 |     16(0.01%) |     16(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           cdc                                                                                   |                                                     ipbus_transport_multibuffer_cdc_1234 |     14(0.01%) |     14(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rx_ram                                                                                |                                                ipbus_transport_multibuffer_rx_dpram_1235 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           tx_ram                                                                                |                                                ipbus_transport_multibuffer_tx_dpram_1236 |     34(0.01%) |     34(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       versal_decl_test.axi_bram_ctrl_versal                                                     |                                                              axi_bram_ctrl_versal_0_1224 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         U0                                                                                      |                                                                       axi_bram_ctrl_1225 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           gext_inst.abcv4_0_ext_inst                                                            |                                                                   axi_bram_ctrl_top_1226 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             GEN_AXI4.I_FULL_AXI                                                                 |                                                                            full_axi_1227 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               I_RD_CHNL                                                                         |                                                                             rd_chnl_1228 |    228(0.01%) |    228(0.01%) |   0(0.00%) |   0(0.00%) |    243(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (I_RD_CHNL)                                                                     |                                                                             rd_chnl_1228 |    184(0.01%) |    184(0.01%) |   0(0.00%) |   0(0.00%) |    228(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 GEN_NO_RD_CMD_OPT.I_WRAP_BRST                                                   |                                                                           wrap_brst_1232 |     45(0.01%) |     45(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               I_WR_CHNL                                                                         |                                                                             wr_chnl_1229 |    110(0.01%) |    110(0.01%) |   0(0.00%) |   0(0.00%) |    155(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (I_WR_CHNL)                                                                     |                                                                             wr_chnl_1229 |     74(0.01%) |     74(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BID_FIFO                                                                        |                                                                            SRL_FIFO_1230 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 I_WRAP_BRST                                                                     |                                                                           wrap_brst_1231 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |     14(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     ipb_axi_inst_IN_SLR1                                                                        |                                                              ipbus_transport_axi_if_1182 |    455(0.01%) |    455(0.01%) |   0(0.00%) |   0(0.00%) |    519(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       ram_to_trans                                                                              |                                                              ipbus_transport_ram_if_1209 |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |    121(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (ram_to_trans)                                                                          |                                                              ipbus_transport_ram_if_1209 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |     79(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         multibuffer_if                                                                          |                                                      ipbus_transport_multibuffer_if_1219 |     77(0.01%) |     77(0.01%) |   0(0.00%) |   0(0.00%) |     42(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (multibuffer_if)                                                                      |                                                      ipbus_transport_multibuffer_if_1219 |     16(0.01%) |     16(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           cdc                                                                                   |                                                     ipbus_transport_multibuffer_cdc_1220 |     14(0.01%) |     14(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rx_ram                                                                                |                                                ipbus_transport_multibuffer_rx_dpram_1221 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           tx_ram                                                                                |                                                ipbus_transport_multibuffer_tx_dpram_1222 |     34(0.01%) |     34(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       versal_decl_test.axi_bram_ctrl_versal                                                     |                                                              axi_bram_ctrl_versal_0_1210 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         U0                                                                                      |                                                                       axi_bram_ctrl_1211 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           gext_inst.abcv4_0_ext_inst                                                            |                                                                   axi_bram_ctrl_top_1212 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             GEN_AXI4.I_FULL_AXI                                                                 |                                                                            full_axi_1213 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               I_RD_CHNL                                                                         |                                                                             rd_chnl_1214 |    227(0.01%) |    227(0.01%) |   0(0.00%) |   0(0.00%) |    243(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (I_RD_CHNL)                                                                     |                                                                             rd_chnl_1214 |    184(0.01%) |    184(0.01%) |   0(0.00%) |   0(0.00%) |    228(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 GEN_NO_RD_CMD_OPT.I_WRAP_BRST                                                   |                                                                           wrap_brst_1218 |     46(0.01%) |     46(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               I_WR_CHNL                                                                         |                                                                             wr_chnl_1215 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    155(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (I_WR_CHNL)                                                                     |                                                                             wr_chnl_1215 |     73(0.01%) |     73(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BID_FIFO                                                                        |                                                                            SRL_FIFO_1216 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 I_WRAP_BRST                                                                     |                                                                           wrap_brst_1217 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |     14(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     ipb_axi_inst_IN_SLR2                                                                        |                                                              ipbus_transport_axi_if_1183 |    455(0.01%) |    455(0.01%) |   0(0.00%) |   0(0.00%) |    519(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       ram_to_trans                                                                              |                                                              ipbus_transport_ram_if_1195 |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |    121(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (ram_to_trans)                                                                          |                                                              ipbus_transport_ram_if_1195 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |     79(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         multibuffer_if                                                                          |                                                      ipbus_transport_multibuffer_if_1205 |     77(0.01%) |     77(0.01%) |   0(0.00%) |   0(0.00%) |     42(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (multibuffer_if)                                                                      |                                                      ipbus_transport_multibuffer_if_1205 |     16(0.01%) |     16(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           cdc                                                                                   |                                                     ipbus_transport_multibuffer_cdc_1206 |     14(0.01%) |     14(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rx_ram                                                                                |                                                ipbus_transport_multibuffer_rx_dpram_1207 |     15(0.01%) |     15(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           tx_ram                                                                                |                                                ipbus_transport_multibuffer_tx_dpram_1208 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       versal_decl_test.axi_bram_ctrl_versal                                                     |                                                              axi_bram_ctrl_versal_0_1196 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         U0                                                                                      |                                                                       axi_bram_ctrl_1197 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           gext_inst.abcv4_0_ext_inst                                                            |                                                                   axi_bram_ctrl_top_1198 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             GEN_AXI4.I_FULL_AXI                                                                 |                                                                            full_axi_1199 |    338(0.01%) |    338(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               I_RD_CHNL                                                                         |                                                                             rd_chnl_1200 |    227(0.01%) |    227(0.01%) |   0(0.00%) |   0(0.00%) |    243(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (I_RD_CHNL)                                                                     |                                                                             rd_chnl_1200 |    183(0.01%) |    183(0.01%) |   0(0.00%) |   0(0.00%) |    228(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 GEN_NO_RD_CMD_OPT.I_WRAP_BRST                                                   |                                                                           wrap_brst_1204 |     45(0.01%) |     45(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               I_WR_CHNL                                                                         |                                                                             wr_chnl_1201 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    155(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (I_WR_CHNL)                                                                     |                                                                             wr_chnl_1201 |     73(0.01%) |     73(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BID_FIFO                                                                        |                                                                            SRL_FIFO_1202 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 I_WRAP_BRST                                                                     |                                                                           wrap_brst_1203 |     33(0.01%) |     33(0.01%) |   0(0.00%) |   0(0.00%) |     14(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     ipb_axi_inst_IN_SLR3                                                                        |                                                              ipbus_transport_axi_if_1184 |    464(0.01%) |    464(0.01%) |   0(0.00%) |   0(0.00%) |    519(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       ram_to_trans                                                                              |                                                                   ipbus_transport_ram_if |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |    121(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (ram_to_trans)                                                                          |                                                                   ipbus_transport_ram_if |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |     79(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         multibuffer_if                                                                          |                                                           ipbus_transport_multibuffer_if |     77(0.01%) |     77(0.01%) |   0(0.00%) |   0(0.00%) |     42(0.01%) |  16(0.32%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (multibuffer_if)                                                                      |                                                           ipbus_transport_multibuffer_if |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           cdc                                                                                   |                                                          ipbus_transport_multibuffer_cdc |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rx_ram                                                                                |                                                     ipbus_transport_multibuffer_rx_dpram |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           tx_ram                                                                                |                                                     ipbus_transport_multibuffer_tx_dpram |     34(0.01%) |     34(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   8(0.16%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       versal_decl_test.axi_bram_ctrl_versal                                                     |                                                                   axi_bram_ctrl_versal_0 |    348(0.01%) |    348(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         U0                                                                                      |                                                                            axi_bram_ctrl |    348(0.01%) |    348(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           gext_inst.abcv4_0_ext_inst                                                            |                                                                        axi_bram_ctrl_top |    348(0.01%) |    348(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             GEN_AXI4.I_FULL_AXI                                                                 |                                                                                 full_axi |    348(0.01%) |    348(0.01%) |   0(0.00%) |   0(0.00%) |    398(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               I_RD_CHNL                                                                         |                                                                                  rd_chnl |    230(0.01%) |    230(0.01%) |   0(0.00%) |   0(0.00%) |    243(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (I_RD_CHNL)                                                                     |                                                                                  rd_chnl |    183(0.01%) |    183(0.01%) |   0(0.00%) |   0(0.00%) |    228(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 GEN_NO_RD_CMD_OPT.I_WRAP_BRST                                                   |                                                                           wrap_brst_1194 |     48(0.01%) |     48(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               I_WR_CHNL                                                                         |                                                                                  wr_chnl |    118(0.01%) |    118(0.01%) |   0(0.00%) |   0(0.00%) |    155(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (I_WR_CHNL)                                                                     |                                                                                  wr_chnl |     77(0.01%) |     77(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BID_FIFO                                                                        |                                                                                 SRL_FIFO |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 I_WRAP_BRST                                                                     |                                                                                wrap_brst |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     14(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     ipb_trans_inst_IN_SLR0                                                                      |                                                                               transactor |    467(0.01%) |    467(0.01%) |   0(0.00%) |   0(0.00%) |    355(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       iface                                                                                     |                                                                       transactor_if_1192 |    184(0.01%) |    184(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sm                                                                                        |                                                                       transactor_sm_1193 |    284(0.01%) |    284(0.01%) |   0(0.00%) |   0(0.00%) |    214(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     ipb_trans_inst_IN_SLR1                                                                      |                                                                          transactor_1185 |    435(0.01%) |    435(0.01%) |   0(0.00%) |   0(0.00%) |    355(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       iface                                                                                     |                                                                       transactor_if_1190 |    186(0.01%) |    186(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sm                                                                                        |                                                                       transactor_sm_1191 |    250(0.01%) |    250(0.01%) |   0(0.00%) |   0(0.00%) |    214(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     ipb_trans_inst_IN_SLR2                                                                      |                                                                          transactor_1186 |    270(0.01%) |    270(0.01%) |   0(0.00%) |   0(0.00%) |    226(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       iface                                                                                     |                                                                       transactor_if_1188 |    170(0.01%) |    170(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sm                                                                                        |                                                                       transactor_sm_1189 |    101(0.01%) |    101(0.01%) |   0(0.00%) |   0(0.00%) |     85(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     ipb_trans_inst_IN_SLR3                                                                      |                                                                          transactor_1187 |    756(0.02%) |    756(0.02%) |   0(0.00%) |   0(0.00%) |    484(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       iface                                                                                     |                                                                            transactor_if |    206(0.01%) |    206(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sm                                                                                        |                                                                            transactor_sm |    550(0.02%) |    550(0.02%) |   0(0.00%) |   0(0.00%) |    343(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|   U_mgt                                                                                         |                                                                                      mgt |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     if_sim.fabric_IN_SLR0                                                                       |                                                         ipbus_fabric_sel__parameterized1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|   U_payload                                                                                     |                                                                                  payload |  92838(2.76%) |  91982(2.74%) | 856(0.05%) |   0(0.00%) | 132812(1.98%) | 190(3.85%) |  9(0.09%) | 33(1.29%) |   4(0.03%) |
|     (U_payload)                                                                                 |                                                                                  payload |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     CELL_BUFFER_IN_SLR3                                                                         |                                                                  nibbler__parameterized0 |   1707(0.05%) |   1707(0.05%) |   0(0.00%) |   0(0.00%) |   3866(0.06%) |  28(0.57%) |  2(0.02%) |  0(0.00%) |   0(0.00%) |
|       (CELL_BUFFER_IN_SLR3)                                                                     |                                                                  nibbler__parameterized0 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     17(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                                 pipeline__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1626(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       SOURCE_OR_SINK.TGEN_VERILOG                                                               |                                                                     tgen__parameterized1 |    328(0.01%) |    328(0.01%) |   0(0.00%) |   0(0.00%) |     57(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       SOURCE_OR_SINK.timer_source                                                               |                                                             time_nibbler__parameterized0 |    129(0.01%) |    129(0.01%) |   0(0.00%) |   0(0.00%) |    108(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|         (SOURCE_OR_SINK.timer_source)                                                           |                                                             time_nibbler__parameterized0 |    119(0.01%) |    119(0.01%) |   0(0.00%) |   0(0.00%) |     98(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         DESTINATION_TGEN.mem                                                                    |                                                               dp_ram_ipb__parameterized1 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           (DESTINATION_TGEN.mem)                                                                |                                                               dp_ram_ipb__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                     dual_port_bram_infer__parameterized1 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                            syncreg_w_260 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mem                                                                                       |                                                               dp_ram_ipb__parameterized2 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |  28(0.57%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|         (mem)                                                                                   |                                                               dp_ram_ipb__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         memory                                                                                  |                                                     dual_port_bram_infer__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |  28(0.57%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                            syncreg_w_259 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sim.FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sim.nibbler_registers                                                                     |                                                      ipbus_ctrlreg_v__parameterized1_258 |   1248(0.04%) |   1248(0.04%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     EGAMMA1BDT_APP_IN_SLR3                                                                      |                                                                      app__parameterized3 |   3304(0.10%) |   3272(0.10%) |  32(0.01%) |   0(0.00%) |   7970(0.12%) |  11(0.22%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|       (EGAMMA1BDT_APP_IN_SLR3)                                                                  |                                                                      app__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     63(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                              pipeline__parameterized1__5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       acc_error_2t_inst                                                                         |                                                                         acc_error_2t_733 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_rx2t_inst                                                                            |                                                                           BCID_rx_2t_734 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_0                                                                            |                                                            reg_array__parameterized2_821 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_1                                                                            |                                                            reg_array__parameterized2_822 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       data_out_mux                                                                              |                                                                mux21__parameterized6_735 |     48(0.01%) |     48(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                        |                                                                               logger_736 |    246(0.01%) |    246(0.01%) |   0(0.00%) |   0(0.00%) |    255(0.01%) |   9(0.18%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                    |                                                                               logger_736 |     70(0.01%) |     70(0.01%) |   0(0.00%) |   0(0.00%) |    184(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         APU_RAM                                                                                 |                                                                    ipbus_ram_wrapper_810 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (APU_RAM)                                                                             |                                                                    ipbus_ram_wrapper_810 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_820 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                                |                                                                    ipbus_ram_wrapper_811 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                            |                                                                    ipbus_ram_wrapper_811 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_819 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ERROR_RAM                                                                               |                                                    ipbus_ram_wrapper__parameterized1_812 |     47(0.01%) |     47(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (ERROR_RAM)                                                                           |                                                    ipbus_ram_wrapper__parameterized1_812 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized4_818 |     37(0.01%) |     37(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                            |                                                    ipbus_ram_wrapper__parameterized0_813 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                        |                                                    ipbus_ram_wrapper__parameterized0_813 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_817 |     39(0.01%) |     39(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[0].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_814 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[0].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_814 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_816 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         logger_registers                                                                        |                                                      ipbus_ctrlreg_v__parameterized2_815 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                                 |                                                      ipbus_ctrlreg_v__parameterized1_737 |   1231(0.04%) |   1231(0.04%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[0].input0_hf_rxtx                                                                 |                                                                         sync_hf_rxtx_738 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                               dmux14__parameterized1_799 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                mux41__parameterized3_800 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                            reg_array__parameterized1_801 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_802 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_803 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_804 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                mux41__parameterized2_805 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                            reg_array__parameterized0_806 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_807 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_808 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_809 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd1                                                                                  |                                                                             edge_reg_740 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd2                                                                                  |                                                                             edge_reg_741 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd3                                                                                  |                                                                             edge_reg_742 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       err_fsm                                                                                   |                                                                            error_fsm_743 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     27(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       hf_fsm                                                                                    |                                                            head_foot_fsm__parameterized7 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |     70(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__18 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1602(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                          sync_mt_fifo_v2__parameterized1 |    210(0.01%) |    210(0.01%) |   0(0.00%) |   0(0.00%) |    717(0.01%) |   0(0.00%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                          sync_mt_fifo_v2__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    513(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_771 |     48(0.01%) |     48(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_771 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_793 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_794 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_795 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_796 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_797 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_798 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_772 |     49(0.01%) |     49(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_772 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_787 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_788 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_789 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_790 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_791 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_792 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_773 |     66(0.01%) |     66(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_773 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_781 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_782 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_783 |     33(0.01%) |     33(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_784 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_785 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_786 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_774 |     47(0.01%) |     47(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_774 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_775 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_776 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_777 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_778 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_779 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_780 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                               dp_bram_v2__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|       output_nibbler                                                                            |                                                                  nibbler__parameterized5 |   1291(0.04%) |   1259(0.04%) |  32(0.01%) |   0(0.00%) |   2715(0.04%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (output_nibbler)                                                                        |                                                                  nibbler__parameterized5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         FREE_FROM_SLR_output_pipeline                                                           |                                                                             pipeline__17 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    260(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.TGEN_VERILOG                                                             |                                                                    tgen__parameterized11 |     92(0.01%) |     92(0.01%) |   0(0.00%) |   0(0.00%) |     53(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.timer_source                                                             |                                                         time_nibbler__parameterized1_762 |    151(0.01%) |    119(0.01%) |  32(0.01%) |   0(0.00%) |    116(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCE_OR_SINK.timer_source)                                                         |                                                         time_nibbler__parameterized1_762 |     97(0.01%) |     97(0.01%) |   0(0.00%) |   0(0.00%) |     90(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           DESTINATION_TGEN.mem                                                                  |                                                           dp_ram_ipb__parameterized4_768 |     54(0.01%) |     22(0.01%) |  32(0.01%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (DESTINATION_TGEN.mem)                                                              |                                                           dp_ram_ipb__parameterized4_768 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             memory                                                                              |                                                 dual_port_bram_infer__parameterized6_769 |     51(0.01%) |     19(0.01%) |  32(0.01%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             syncreg_w_inst                                                                      |                                                                            syncreg_w_770 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mem                                                                                     |                                                           dp_ram_ipb__parameterized5_763 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (mem)                                                                                 |                                                           dp_ram_ipb__parameterized5_763 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized7_766 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                            syncreg_w_767 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         perf_count_inst                                                                         |                                                           perf_count__parameterized7_764 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.FREE_FROM_SLR_input_pipeline                                                        |                                                                             pipeline__16 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    204(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.nibbler_registers                                                                   |                                                      ipbus_ctrlreg_v__parameterized1_765 |   1036(0.03%) |   1036(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       pulse_we                                                                                  |                                                                            pulse_cdc_745 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                              |                                                                            pulse_cdc_745 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                            syncreg_w_761 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       rd_done_cda                                                                               |                                                                  cooldown_arbiter_v2_746 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sync_inst                                                                                 |                                                                          sync_fsm_v6_747 |     19(0.01%) |     19(0.01%) |   0(0.00%) |   0(0.00%) |     17(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd1                                                                                       |                                                                      watch_dog_timer_748 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (wd1)                                                                                   |                                                                      watch_dog_timer_748 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         pc1                                                                                     |                                                           perf_count__parameterized3_760 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd2                                                                                       |                                                                   watch_dog_timer_2t_749 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_756 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_756 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_759 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_757 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_757 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_758 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd3                                                                                       |                                                                   watch_dog_timer_2t_750 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_752 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_752 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_755 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_753 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_753 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_754 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wr_done_cda                                                                               |                                                                  cooldown_arbiter_v2_751 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     EGAMMA1BDT_APU_IN_SLR3                                                                      |                                                                       egamma1bdt_lib_apu |   4011(0.12%) |   4011(0.12%) |   0(0.00%) |   0(0.00%) |   3781(0.06%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (EGAMMA1BDT_APU_IN_SLR3)                                                                  |                                                                       egamma1bdt_lib_apu |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       U_egammaBDT                                                                               |                                                                                egammaBDT |   3977(0.12%) |   3977(0.12%) |   0(0.00%) |   0(0.00%) |   3648(0.05%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (U_egammaBDT)                                                                           |                                                                                egammaBDT |    272(0.01%) |    272(0.01%) |   0(0.00%) |   0(0.00%) |    445(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         bdt_core                                                                                |                                                                                   my_prj |   3705(0.11%) |   3705(0.11%) |   0(0.00%) |   0(0.00%) |   3203(0.05%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (bdt_core)                                                                            |                                                                                   my_prj |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           grp_decision_function_94_fu_179                                                       |                                                              my_prj_decision_function_94 |   3703(0.11%) |   3703(0.11%) |   0(0.00%) |   0(0.00%) |   3198(0.05%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (grp_decision_function_94_fu_179)                                                   |                                                              my_prj_decision_function_94 |    450(0.01%) |    450(0.01%) |   0(0.00%) |   0(0.00%) |   1784(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             grp_reduce_ap_fixed_18_8_5_3_0_16_OpAdd_ap_fixed_18_8_5_3_0_s_fu_198                |                         my_prj_reduce_ap_fixed_18_8_5_3_0_16_OpAdd_ap_fixed_18_8_5_3_0_s |    257(0.01%) |    257(0.01%) |   0(0.00%) |   0(0.00%) |    159(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             grp_reduce_ap_fixed_18_8_5_3_0_16_OpAdd_ap_fixed_18_8_5_3_0_s_fu_268                |                     my_prj_reduce_ap_fixed_18_8_5_3_0_16_OpAdd_ap_fixed_18_8_5_3_0_s_255 |    255(0.01%) |    255(0.01%) |   0(0.00%) |   0(0.00%) |    159(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             grp_reduce_ap_fixed_18_8_5_3_0_16_OpAdd_ap_fixed_18_8_5_3_0_s_fu_338                |                     my_prj_reduce_ap_fixed_18_8_5_3_0_16_OpAdd_ap_fixed_18_8_5_3_0_s_256 |    255(0.01%) |    255(0.01%) |   0(0.00%) |   0(0.00%) |    159(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             grp_reduce_ap_fixed_18_8_5_3_0_16_OpAdd_ap_fixed_18_8_5_3_0_s_fu_408                |                     my_prj_reduce_ap_fixed_18_8_5_3_0_16_OpAdd_ap_fixed_18_8_5_3_0_s_257 |    264(0.01%) |    264(0.01%) |   0(0.00%) |   0(0.00%) |    159(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             grp_tree_scores_fu_158                                                              |                                                                       my_prj_tree_scores |   2229(0.07%) |   2229(0.07%) |   0(0.00%) |   0(0.00%) |    778(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (grp_tree_scores_fu_158)                                                          |                                                                       my_prj_tree_scores |    290(0.01%) |    290(0.01%) |   0(0.00%) |   0(0.00%) |    126(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_10_fu_1816                                                  |                                                              my_prj_decision_function_10 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_13_fu_1766                                                  |                                                              my_prj_decision_function_13 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_15_fu_478                                                   |                                                              my_prj_decision_function_15 |     34(0.01%) |     34(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_16_fu_1736                                                  |                                                              my_prj_decision_function_16 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_19_fu_1686                                                  |                                                              my_prj_decision_function_19 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_1_fu_1944                                                   |                                                               my_prj_decision_function_1 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_20_fu_1668                                                  |                                                              my_prj_decision_function_20 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_26_fu_462                                                   |                                                              my_prj_decision_function_26 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_29_fu_1536                                                  |                                                              my_prj_decision_function_29 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_30_fu_1520                                                  |                                                              my_prj_decision_function_30 |     37(0.01%) |     37(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_32_fu_1490                                                  |                                                              my_prj_decision_function_32 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_34_fu_1454                                                  |                                                              my_prj_decision_function_34 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_35_fu_1432                                                  |                                                              my_prj_decision_function_35 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_36_fu_1418                                                  |                                                              my_prj_decision_function_36 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_37_fu_444                                                   |                                                              my_prj_decision_function_37 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_38_fu_1398                                                  |                                                              my_prj_decision_function_38 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_39_fu_1386                                                  |                                                              my_prj_decision_function_39 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_40_fu_1366                                                  |                                                              my_prj_decision_function_40 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_41_fu_1346                                                  |                                                              my_prj_decision_function_41 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_42_fu_1324                                                  |                                                              my_prj_decision_function_42 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_43_fu_1310                                                  |                                                              my_prj_decision_function_43 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_44_fu_1296                                                  |                                                              my_prj_decision_function_44 |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_45_fu_1278                                                  |                                                              my_prj_decision_function_45 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_46_fu_1260                                                  |                                                              my_prj_decision_function_46 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_47_fu_1240                                                  |                                                              my_prj_decision_function_47 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_48_fu_428                                                   |                                                              my_prj_decision_function_48 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_49_fu_1226                                                  |                                                              my_prj_decision_function_49 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_4_fu_494                                                    |                                                               my_prj_decision_function_4 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_50_fu_1206                                                  |                                                              my_prj_decision_function_50 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_51_fu_1186                                                  |                                                              my_prj_decision_function_51 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_52_fu_1168                                                  |                                                              my_prj_decision_function_52 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_53_fu_1150                                                  |                                                              my_prj_decision_function_53 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_54_fu_1130                                                  |                                                              my_prj_decision_function_54 |     29(0.01%) |     29(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_55_fu_1114                                                  |                                                              my_prj_decision_function_55 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_56_fu_1094                                                  |                                                              my_prj_decision_function_56 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_57_fu_1074                                                  |                                                              my_prj_decision_function_57 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_58_fu_1058                                                  |                                                              my_prj_decision_function_58 |     34(0.01%) |     34(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_59_fu_408                                                   |                                                              my_prj_decision_function_59 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_60_fu_1042                                                  |                                                              my_prj_decision_function_60 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_61_fu_1022                                                  |                                                              my_prj_decision_function_61 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_62_fu_1004                                                  |                                                              my_prj_decision_function_62 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_63_fu_984                                                   |                                                              my_prj_decision_function_63 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_64_fu_970                                                   |                                                              my_prj_decision_function_64 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_65_fu_954                                                   |                                                              my_prj_decision_function_65 |     26(0.01%) |     26(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_66_fu_938                                                   |                                                              my_prj_decision_function_66 |     29(0.01%) |     29(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_67_fu_916                                                   |                                                              my_prj_decision_function_67 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_68_fu_898                                                   |                                                              my_prj_decision_function_68 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_69_fu_878                                                   |                                                              my_prj_decision_function_69 |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_6_fu_1888                                                   |                                                               my_prj_decision_function_6 |     38(0.01%) |     38(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_70_fu_390                                                   |                                                              my_prj_decision_function_70 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_71_fu_858                                                   |                                                              my_prj_decision_function_71 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_72_fu_838                                                   |                                                              my_prj_decision_function_72 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_73_fu_820                                                   |                                                              my_prj_decision_function_73 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_74_fu_802                                                   |                                                              my_prj_decision_function_74 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_75_fu_786                                                   |                                                              my_prj_decision_function_75 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_76_fu_770                                                   |                                                              my_prj_decision_function_76 |     26(0.01%) |     26(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_77_fu_752                                                   |                                                              my_prj_decision_function_77 |     37(0.01%) |     37(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_78_fu_734                                                   |                                                              my_prj_decision_function_78 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_79_fu_714                                                   |                                                              my_prj_decision_function_79 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_7_fu_1868                                                   |                                                               my_prj_decision_function_7 |     41(0.01%) |     41(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_80_fu_696                                                   |                                                              my_prj_decision_function_80 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_81_fu_370                                                   |                                                              my_prj_decision_function_81 |     42(0.01%) |     42(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_82_fu_680                                                   |                                                              my_prj_decision_function_82 |     26(0.01%) |     26(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_83_fu_660                                                   |                                                              my_prj_decision_function_83 |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_84_fu_644                                                   |                                                              my_prj_decision_function_84 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_85_fu_628                                                   |                                                              my_prj_decision_function_85 |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_86_fu_610                                                   |                                                              my_prj_decision_function_86 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_87_fu_590                                                   |                                                              my_prj_decision_function_87 |     33(0.01%) |     33(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_88_fu_574                                                   |                                                              my_prj_decision_function_88 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_89_fu_554                                                   |                                                              my_prj_decision_function_89 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_8_fu_1850                                                   |                                                               my_prj_decision_function_8 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_90_fu_534                                                   |                                                              my_prj_decision_function_90 |     26(0.01%) |     26(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_91_fu_514                                                   |                                                              my_prj_decision_function_91 |     29(0.01%) |     29(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_92_fu_352                                                   |                                                              my_prj_decision_function_92 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_93_fu_336                                                   |                                                              my_prj_decision_function_93 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               grp_decision_function_9_fu_1836                                                   |                                                               my_prj_decision_function_9 |     16(0.01%) |     16(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       apu_registers                                                                             |                                                      ipbus_ctrlreg_v__parameterized3_254 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     EGAMMA1_APP_IN_SLR3                                                                         |                                                                      app__parameterized2 |   3294(0.10%) |   3262(0.10%) |  32(0.01%) |   0(0.00%) |   7980(0.12%) |  11(0.22%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|       (EGAMMA1_APP_IN_SLR3)                                                                     |                                                                      app__parameterized2 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |     64(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                              pipeline__parameterized1__4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       acc_error_2t_inst                                                                         |                                                                         acc_error_2t_823 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_rx2t_inst                                                                            |                                                                           BCID_rx_2t_824 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_0                                                                            |                                                            reg_array__parameterized2_913 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_1                                                                            |                                                            reg_array__parameterized2_914 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       data_out_mux                                                                              |                                                                mux21__parameterized6_825 |     46(0.01%) |     46(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                        |                                                                               logger_826 |    246(0.01%) |    246(0.01%) |   0(0.00%) |   0(0.00%) |    255(0.01%) |   9(0.18%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                    |                                                                               logger_826 |     70(0.01%) |     70(0.01%) |   0(0.00%) |   0(0.00%) |    184(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         APU_RAM                                                                                 |                                                                    ipbus_ram_wrapper_902 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (APU_RAM)                                                                             |                                                                    ipbus_ram_wrapper_902 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_912 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                                |                                                                    ipbus_ram_wrapper_903 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                            |                                                                    ipbus_ram_wrapper_903 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_911 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ERROR_RAM                                                                               |                                                    ipbus_ram_wrapper__parameterized1_904 |     47(0.01%) |     47(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (ERROR_RAM)                                                                           |                                                    ipbus_ram_wrapper__parameterized1_904 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized4_910 |     37(0.01%) |     37(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                            |                                                    ipbus_ram_wrapper__parameterized0_905 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                        |                                                    ipbus_ram_wrapper__parameterized0_905 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_909 |     39(0.01%) |     39(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[0].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_906 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[0].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_906 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_908 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         logger_registers                                                                        |                                                      ipbus_ctrlreg_v__parameterized2_907 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                                 |                                                      ipbus_ctrlreg_v__parameterized1_827 |   1232(0.04%) |   1232(0.04%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[0].input0_hf_rxtx                                                                 |                                                                         sync_hf_rxtx_828 |    125(0.01%) |    125(0.01%) |   0(0.00%) |   0(0.00%) |    320(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                               dmux14__parameterized1_891 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                mux41__parameterized3_892 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                            reg_array__parameterized1_893 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_894 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_895 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_896 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                mux41__parameterized2_897 |     15(0.01%) |     15(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                            reg_array__parameterized0_898 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_899 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_900 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_901 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd1                                                                                  |                                                                             edge_reg_830 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd2                                                                                  |                                                                             edge_reg_831 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd3                                                                                  |                                                                             edge_reg_832 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       err_fsm                                                                                   |                                                                            error_fsm_833 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     28(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       hf_fsm                                                                                    |                                                            head_foot_fsm__parameterized5 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     72(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__15 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1602(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                      sync_mt_fifo_v2__parameterized1_834 |    218(0.01%) |    218(0.01%) |   0(0.00%) |   0(0.00%) |    717(0.01%) |   0(0.00%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                      sync_mt_fifo_v2__parameterized1_834 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    513(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_862 |     49(0.01%) |     49(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_862 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_885 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_886 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_887 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_888 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_889 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_890 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_863 |     50(0.01%) |     50(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_863 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_879 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_880 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_881 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_882 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_883 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_884 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_864 |     71(0.01%) |     71(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_864 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_873 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_874 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_875 |     36(0.01%) |     36(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_876 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_877 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_878 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_865 |     48(0.01%) |     48(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_865 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_867 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_868 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_869 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_870 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_871 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_872 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                           dp_bram_v2__parameterized0_866 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|       output_nibbler                                                                            |                                                                  nibbler__parameterized4 |   1251(0.04%) |   1219(0.04%) |  32(0.01%) |   0(0.00%) |   2713(0.04%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (output_nibbler)                                                                        |                                                                  nibbler__parameterized4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         FREE_FROM_SLR_output_pipeline                                                           |                                                                             pipeline__14 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.TGEN_VERILOG                                                             |                                                                     tgen__parameterized9 |     91(0.01%) |     91(0.01%) |   0(0.00%) |   0(0.00%) |     53(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.timer_source                                                             |                                                         time_nibbler__parameterized1_853 |    153(0.01%) |    121(0.01%) |  32(0.01%) |   0(0.00%) |    116(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCE_OR_SINK.timer_source)                                                         |                                                         time_nibbler__parameterized1_853 |     98(0.01%) |     98(0.01%) |   0(0.00%) |   0(0.00%) |     90(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           DESTINATION_TGEN.mem                                                                  |                                                           dp_ram_ipb__parameterized4_859 |     55(0.01%) |     23(0.01%) |  32(0.01%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (DESTINATION_TGEN.mem)                                                              |                                                           dp_ram_ipb__parameterized4_859 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             memory                                                                              |                                                 dual_port_bram_infer__parameterized6_860 |     51(0.01%) |     19(0.01%) |  32(0.01%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             syncreg_w_inst                                                                      |                                                                            syncreg_w_861 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mem                                                                                     |                                                           dp_ram_ipb__parameterized5_854 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (mem)                                                                                 |                                                           dp_ram_ipb__parameterized5_854 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized7_857 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                            syncreg_w_858 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         perf_count_inst                                                                         |                                                           perf_count__parameterized7_855 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.FREE_FROM_SLR_input_pipeline                                                        |                                                                             pipeline__13 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    204(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.nibbler_registers                                                                   |                                                      ipbus_ctrlreg_v__parameterized1_856 |    998(0.03%) |    998(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       pulse_we                                                                                  |                                                                            pulse_cdc_836 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                              |                                                                            pulse_cdc_836 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                            syncreg_w_852 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       rd_done_cda                                                                               |                                                                  cooldown_arbiter_v2_837 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sync_inst                                                                                 |                                                                          sync_fsm_v6_838 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |     17(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd1                                                                                       |                                                                      watch_dog_timer_839 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (wd1)                                                                                   |                                                                      watch_dog_timer_839 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         pc1                                                                                     |                                                           perf_count__parameterized3_851 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd2                                                                                       |                                                                   watch_dog_timer_2t_840 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_847 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_847 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_850 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_848 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_848 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_849 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd3                                                                                       |                                                                   watch_dog_timer_2t_841 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_843 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_843 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_846 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_844 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_844 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_845 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wr_done_cda                                                                               |                                                                  cooldown_arbiter_v2_842 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     EGAMMA1_APU_IN_SLR3                                                                         |                                                                    egamma1eratio_lib_apu |    524(0.02%) |    524(0.02%) |   0(0.00%) |   0(0.00%) |    769(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (EGAMMA1_APU_IN_SLR3)                                                                     |                                                                    egamma1eratio_lib_apu |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |    469(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       ipbus_debug.apu_registers                                                                 |                                                      ipbus_ctrlreg_v__parameterized3_253 |     53(0.01%) |     53(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       max_finding_1                                                                             |                                                                      max_finding_paralel |    408(0.01%) |    408(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       threshold_check_1                                                                         |                                                                          threshold_check |     58(0.01%) |     58(0.01%) |   0(0.00%) |   0(0.00%) |     44(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     JET1_APP_IN_SLR1                                                                            |                                                                      app__parameterized4 |   3019(0.09%) |   3003(0.09%) |  16(0.01%) |   0(0.00%) |   6566(0.10%) |  13(0.26%) |  0(0.00%) |  1(0.04%) |   0(0.00%) |
|       (JET1_APP_IN_SLR1)                                                                        |                                                                      app__parameterized4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     64(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                                 pipeline__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       acc_error_2t_inst                                                                         |                                                                         acc_error_2t_653 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_rx2t_inst                                                                            |                                                                           BCID_rx_2t_654 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_0                                                                            |                                                            reg_array__parameterized2_731 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_1                                                                            |                                                            reg_array__parameterized2_732 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       data_out_mux                                                                              |                                                               mux21__parameterized11_655 |     38(0.01%) |     38(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                        |                                                                   logger__parameterized0 |    247(0.01%) |    247(0.01%) |   0(0.00%) |   0(0.00%) |    255(0.01%) |   9(0.18%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                    |                                                                   logger__parameterized0 |     67(0.01%) |     67(0.01%) |   0(0.00%) |   0(0.00%) |    184(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         APU_RAM                                                                                 |                                                                    ipbus_ram_wrapper_720 |     29(0.01%) |     29(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (APU_RAM)                                                                             |                                                                    ipbus_ram_wrapper_720 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_730 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                                |                                                                    ipbus_ram_wrapper_721 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                            |                                                                    ipbus_ram_wrapper_721 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_729 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ERROR_RAM                                                                               |                                                    ipbus_ram_wrapper__parameterized1_722 |     49(0.01%) |     49(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (ERROR_RAM)                                                                           |                                                    ipbus_ram_wrapper__parameterized1_722 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized4_728 |     39(0.01%) |     39(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                            |                                                    ipbus_ram_wrapper__parameterized0_723 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                        |                                                    ipbus_ram_wrapper__parameterized0_723 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_727 |     16(0.01%) |     16(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[0].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_724 |     41(0.01%) |     41(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[0].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_724 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_726 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         logger_registers                                                                        |                                                      ipbus_ctrlreg_v__parameterized2_725 |     42(0.01%) |     42(0.01%) |   0(0.00%) |   0(0.00%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                                 |                                                      ipbus_ctrlreg_v__parameterized1_656 |    877(0.03%) |    877(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[0].input0_hf_rxtx                                                                 |                                                                         sync_hf_rxtx_657 |    119(0.01%) |    119(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                               dmux14__parameterized1_709 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                mux41__parameterized3_710 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                            reg_array__parameterized1_711 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_712 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_713 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_714 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                mux41__parameterized2_715 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                            reg_array__parameterized0_716 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_717 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_718 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_719 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd1                                                                                  |                                                                             edge_reg_659 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd2                                                                                  |                                                                             edge_reg_660 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd3                                                                                  |                                                                             edge_reg_661 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       err_fsm                                                                                   |                                                                            error_fsm_662 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     27(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       hf_fsm                                                                                    |                                                            head_foot_fsm__parameterized9 |     38(0.01%) |     38(0.01%) |   0(0.00%) |   0(0.00%) |     69(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__20 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                          sync_mt_fifo_v2__parameterized3 |    223(0.01%) |    223(0.01%) |   0(0.00%) |   0(0.00%) |    269(0.01%) |   0(0.00%) |  0(0.00%) |  1(0.04%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                          sync_mt_fifo_v2__parameterized3 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                       sync_fifo_cntrl_v2__parameterized0 |     49(0.01%) |     49(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                       sync_fifo_cntrl_v2__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_703 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_704 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_705 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_706 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_707 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_708 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_685 |     51(0.01%) |     51(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_685 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_697 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_698 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_699 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_700 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_701 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_702 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_686 |     71(0.01%) |     71(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_686 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_691 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_692 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_693 |     36(0.01%) |     36(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_694 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_695 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_696 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_687 |     50(0.01%) |     50(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_687 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                                reg_array__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_688 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                       fifo_addr_count_v2__parameterized0 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                                 sync_rd_side_roll_detect__parameterized0 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_689 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_690 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                               dp_bram_v2__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  1(0.04%) |   0(0.00%) |
|       output_nibbler                                                                            |                                                                  nibbler__parameterized6 |   1318(0.04%) |   1302(0.04%) |  16(0.01%) |   0(0.00%) |   3105(0.05%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (output_nibbler)                                                                        |                                                                  nibbler__parameterized6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         FREE_FROM_SLR_output_pipeline                                                           |                                                                 pipeline__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    462(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.TGEN_VERILOG                                                             |                                                                    tgen__parameterized13 |    122(0.01%) |    122(0.01%) |   0(0.00%) |   0(0.00%) |     52(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.timer_source                                                             |                                                             time_nibbler__parameterized2 |    125(0.01%) |    109(0.01%) |  16(0.01%) |   0(0.00%) |    114(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCE_OR_SINK.timer_source)                                                         |                                                             time_nibbler__parameterized2 |     95(0.01%) |     95(0.01%) |   0(0.00%) |   0(0.00%) |     88(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           DESTINATION_TGEN.mem                                                                  |                                                               dp_ram_ipb__parameterized6 |     30(0.01%) |     14(0.01%) |  16(0.01%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (DESTINATION_TGEN.mem)                                                              |                                                               dp_ram_ipb__parameterized6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             memory                                                                              |                                                     dual_port_bram_infer__parameterized8 |     23(0.01%) |      7(0.01%) |  16(0.01%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             syncreg_w_inst                                                                      |                                                                            syncreg_w_684 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mem                                                                                     |                                                               dp_ram_ipb__parameterized7 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (mem)                                                                                 |                                                               dp_ram_ipb__parameterized7 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                     dual_port_bram_infer__parameterized9 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                            syncreg_w_683 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         perf_count_inst                                                                         |                                                           perf_count__parameterized5_681 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.FREE_FROM_SLR_input_pipeline                                                        |                                                                             pipeline__19 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    396(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.nibbler_registers                                                                   |                                                      ipbus_ctrlreg_v__parameterized1_682 |   1061(0.03%) |   1061(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       pulse_we                                                                                  |                                                                            pulse_cdc_664 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                              |                                                                            pulse_cdc_664 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                            syncreg_w_680 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       rd_done_cda                                                                               |                                                                  cooldown_arbiter_v2_665 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sync_inst                                                                                 |                                                                          sync_fsm_v6_666 |     19(0.01%) |     19(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd1                                                                                       |                                                                      watch_dog_timer_667 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (wd1)                                                                                   |                                                                      watch_dog_timer_667 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         pc1                                                                                     |                                                           perf_count__parameterized3_679 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd2                                                                                       |                                                                   watch_dog_timer_2t_668 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_675 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_675 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_678 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_676 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_676 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_677 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd3                                                                                       |                                                                   watch_dog_timer_2t_669 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_671 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_671 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_674 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_672 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_672 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_673 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wr_done_cda                                                                               |                                                                  cooldown_arbiter_v2_670 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     JET1_APU_IN_SLR1                                                                            |                                                                             jet1_lib_apu |  54838(1.63%) |  54134(1.61%) | 704(0.04%) |   0(0.00%) |  51679(0.77%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       SIM.apu_registers                                                                         |                                                       ipbus_ctrlreg_v__parameterized3_14 |    761(0.02%) |    761(0.02%) |   0(0.00%) |   0(0.00%) |    133(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       jet1_apu_0                                                                                |                                                                                 jet1_apu |  54077(1.61%) |  53373(1.59%) | 704(0.04%) |   0(0.00%) |  51546(0.77%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (jet1_apu_0)                                                                            |                                                                                 jet1_apu |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     64(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         atb_0                                                                                   |                                                                 jet1_assign_tob_to_block |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         jet1_algo_fsm_inst                                                                      |                                                                            jet1_algo_fsm |     26(0.01%) |     26(0.01%) |   0(0.00%) |   0(0.00%) |     33(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sp0                                                                                     |                                                                           jet1_spit_jets |   4874(0.15%) |   4874(0.15%) |   0(0.00%) |   0(0.00%) |   7085(0.11%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (sp0)                                                                                 |                                                                           jet1_spit_jets |    167(0.01%) |    167(0.01%) |   0(0.00%) |   0(0.00%) |     49(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[0].ss                                                                             |                                                         jet1_stagesort__parameterized159 |    678(0.02%) |    678(0.02%) |   0(0.00%) |   0(0.00%) |    767(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[1].ss                                                                             |                                                     jet1_stagesort__parameterized159_244 |    480(0.01%) |    480(0.01%) |   0(0.00%) |   0(0.00%) |    767(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[2].ss                                                                             |                                                     jet1_stagesort__parameterized159_245 |    481(0.01%) |    481(0.01%) |   0(0.00%) |   0(0.00%) |    661(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[3].ss                                                                             |                                                     jet1_stagesort__parameterized159_246 |    475(0.01%) |    475(0.01%) |   0(0.00%) |   0(0.00%) |    709(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[4].ss                                                                             |                                                     jet1_stagesort__parameterized159_247 |    475(0.01%) |    475(0.01%) |   0(0.00%) |   0(0.00%) |    696(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[5].ss                                                                             |                                                     jet1_stagesort__parameterized159_248 |    474(0.01%) |    474(0.01%) |   0(0.00%) |   0(0.00%) |    682(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[6].ss                                                                             |                                                     jet1_stagesort__parameterized159_249 |    474(0.01%) |    474(0.01%) |   0(0.00%) |   0(0.00%) |    707(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[7].ss                                                                             |                                                     jet1_stagesort__parameterized159_250 |    474(0.01%) |    474(0.01%) |   0(0.00%) |   0(0.00%) |    767(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[8].ss                                                                             |                                                     jet1_stagesort__parameterized159_251 |    474(0.01%) |    474(0.01%) |   0(0.00%) |   0(0.00%) |    767(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           JET[9].ss                                                                             |                                                     jet1_stagesort__parameterized159_252 |    222(0.01%) |    222(0.01%) |   0(0.00%) |   0(0.00%) |    513(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wp_0                                                                                    |                                                                    jet1_wrapper_parallel |  49166(1.46%) |  48462(1.44%) | 704(0.04%) |   0(0.00%) |  44351(0.66%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wp_0)                                                                                |                                                                    jet1_wrapper_parallel |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           cwr_0                                                                                 |                                                                jet1_compute_wta_in_ready |     15(0.01%) |     15(0.01%) |   0(0.00%) |   0(0.00%) |     14(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           spit_go_0                                                                             |                                                                     jet1_compute_spit_go |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wta_block[0].wta_in_0                                                                 |                                                                              jet1_wta_in |   9241(0.27%) |   9065(0.27%) | 176(0.01%) |   0(0.00%) |   9490(0.14%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (wta_block[0].wta_in_0)                                                             |                                                                              jet1_wta_in |    749(0.02%) |    749(0.02%) |   0(0.00%) |   0(0.00%) |    119(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             sb_0                                                                                |                                                                      jet1_stageblock_197 |   8495(0.25%) |   8319(0.25%) | 176(0.01%) |   0(0.00%) |   9371(0.14%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (sb_0)                                                                            |                                                                      jet1_stageblock_197 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |   1440(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               clf_m                                                                             |                                                                      jet1_clist_fifo_198 |    146(0.01%) |     58(0.01%) |  88(0.01%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (clf_m)                                                                         |                                                                      jet1_clist_fifo_198 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[0].sdoc                                                               |                                                           jet1_simple_dual_one_clock_242 |     54(0.01%) |     10(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[1].sdoc                                                               |                                                           jet1_simple_dual_one_clock_243 |     65(0.01%) |     21(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               olf_m                                                                             |                                                                      jet1_clist_fifo_199 |    168(0.01%) |     80(0.01%) |  88(0.01%) |   0(0.00%) |     78(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (olf_m)                                                                         |                                                                      jet1_clist_fifo_199 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |     78(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[0].sdoc                                                               |                                                           jet1_simple_dual_one_clock_240 |     45(0.01%) |      1(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[1].sdoc                                                               |                                                           jet1_simple_dual_one_clock_241 |    102(0.01%) |     58(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[0].ss                                                                       |                                                                       jet1_stagesort_200 |    262(0.01%) |    262(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[10].ss                                                                      |                                                                       jet1_stagesort_201 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[11].ss                                                                      |                                                                       jet1_stagesort_202 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[12].ss                                                                      |                                                                       jet1_stagesort_203 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[13].ss                                                                      |                                                                       jet1_stagesort_204 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[14].ss                                                                      |                                                                       jet1_stagesort_205 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[15].ss                                                                      |                                                                       jet1_stagesort_206 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[16].ss                                                                      |                                                                       jet1_stagesort_207 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[17].ss                                                                      |                                                                       jet1_stagesort_208 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[18].ss                                                                      |                                                                       jet1_stagesort_209 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[19].ss                                                                      |                                                                       jet1_stagesort_210 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[1].ss                                                                       |                                                                       jet1_stagesort_211 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[20].ss                                                                      |                                                                       jet1_stagesort_212 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[21].ss                                                                      |                                                                       jet1_stagesort_213 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[22].ss                                                                      |                                                                       jet1_stagesort_214 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[23].ss                                                                      |                                                                       jet1_stagesort_215 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[24].ss                                                                      |                                                                       jet1_stagesort_216 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[25].ss                                                                      |                                                                       jet1_stagesort_217 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[26].ss                                                                      |                                                                       jet1_stagesort_218 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[27].ss                                                                      |                                                                       jet1_stagesort_219 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[28].ss                                                                      |                                                                       jet1_stagesort_220 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[29].ss                                                                      |                                                                       jet1_stagesort_221 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[2].ss                                                                       |                                                                       jet1_stagesort_222 |    250(0.01%) |    250(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[30].ss                                                                      |                                                                       jet1_stagesort_223 |    198(0.01%) |    198(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[31].ss                                                                      |                                                                       jet1_stagesort_224 |    104(0.01%) |    104(0.01%) |   0(0.00%) |   0(0.00%) |    350(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[32].ss                                                                      |                                                                       jet1_stagesort_225 |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |    446(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[33].ss                                                                      |                                                                       jet1_stagesort_226 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    444(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[34].ss                                                                      |                                                                       jet1_stagesort_227 |    112(0.01%) |    112(0.01%) |   0(0.00%) |   0(0.00%) |    443(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[35].ss                                                                      |                                                                       jet1_stagesort_228 |    112(0.01%) |    112(0.01%) |   0(0.00%) |   0(0.00%) |    443(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[36].ss                                                                      |                                                                       jet1_stagesort_229 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    444(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[37].ss                                                                      |                                                                       jet1_stagesort_230 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    444(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[38].ss                                                                      |                                                                       jet1_stagesort_231 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    443(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[39].ss                                                                      |                                                                       jet1_stagesort_232 |    128(0.01%) |    128(0.01%) |   0(0.00%) |   0(0.00%) |    351(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[3].ss                                                                       |                                                                       jet1_stagesort_233 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[4].ss                                                                       |                                                                       jet1_stagesort_234 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[5].ss                                                                       |                                                                       jet1_stagesort_235 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[6].ss                                                                       |                                                                       jet1_stagesort_236 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[7].ss                                                                       |                                                                       jet1_stagesort_237 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[8].ss                                                                       |                                                                       jet1_stagesort_238 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[9].ss                                                                       |                                                                       jet1_stagesort_239 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wta_block[0].wta_out_0                                                                |                                                                             jet1_wta_out |   3061(0.09%) |   3061(0.09%) |   0(0.00%) |   0(0.00%) |   1603(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (wta_block[0].wta_out_0)                                                            |                                                                             jet1_wta_out |     43(0.01%) |     43(0.01%) |   0(0.00%) |   0(0.00%) |     95(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             sbo_0                                                                               |                                                                  jet1_stageblock_out_186 |   3018(0.09%) |   3018(0.09%) |   0(0.00%) |   0(0.00%) |   1508(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (sbo_0)                                                                           |                                                                  jet1_stageblock_out_186 |    179(0.01%) |    179(0.01%) |   0(0.00%) |   0(0.00%) |    218(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[0].sto_0                                                                  |                                                                       jet1_stage_out_187 |    234(0.01%) |    234(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[1].sto_0                                                                  |                                                                       jet1_stage_out_188 |    235(0.01%) |    235(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[2].sto_0                                                                  |                                                                       jet1_stage_out_189 |    255(0.01%) |    255(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[3].sto_0                                                                  |                                                                       jet1_stage_out_190 |    420(0.01%) |    420(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[4].sto_0                                                                  |                                                                       jet1_stage_out_191 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[5].sto_0                                                                  |                                                                       jet1_stage_out_192 |    218(0.01%) |    218(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[6].sto_0                                                                  |                                                                       jet1_stage_out_193 |    214(0.01%) |    214(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[7].sto_0                                                                  |                                                                       jet1_stage_out_194 |    383(0.01%) |    383(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[8].sto_0                                                                  |                                                                       jet1_stage_out_195 |    260(0.01%) |    260(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[9].sto_0                                                                  |                                                                       jet1_stage_out_196 |    396(0.01%) |    396(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wta_block[1].wta_in_0                                                                 |                                                                           jet1_wta_in_15 |   9236(0.27%) |   9060(0.27%) | 176(0.01%) |   0(0.00%) |   9472(0.14%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (wta_block[1].wta_in_0)                                                             |                                                                           jet1_wta_in_15 |    749(0.02%) |    749(0.02%) |   0(0.00%) |   0(0.00%) |     91(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             sb_0                                                                                |                                                                      jet1_stageblock_139 |   8490(0.25%) |   8314(0.25%) | 176(0.01%) |   0(0.00%) |   9381(0.14%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (sb_0)                                                                            |                                                                      jet1_stageblock_139 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |   1440(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               clf_m                                                                             |                                                                      jet1_clist_fifo_140 |    145(0.01%) |     57(0.01%) |  88(0.01%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (clf_m)                                                                         |                                                                      jet1_clist_fifo_140 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[0].sdoc                                                               |                                                           jet1_simple_dual_one_clock_184 |     54(0.01%) |     10(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[1].sdoc                                                               |                                                           jet1_simple_dual_one_clock_185 |     64(0.01%) |     20(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               olf_m                                                                             |                                                                      jet1_clist_fifo_141 |    167(0.01%) |     79(0.01%) |  88(0.01%) |   0(0.00%) |     78(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (olf_m)                                                                         |                                                                      jet1_clist_fifo_141 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |     78(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[0].sdoc                                                               |                                                           jet1_simple_dual_one_clock_182 |     45(0.01%) |      1(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[1].sdoc                                                               |                                                           jet1_simple_dual_one_clock_183 |    101(0.01%) |     57(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[0].ss                                                                       |                                                                       jet1_stagesort_142 |    262(0.01%) |    262(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[10].ss                                                                      |                                                                       jet1_stagesort_143 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[11].ss                                                                      |                                                                       jet1_stagesort_144 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[12].ss                                                                      |                                                                       jet1_stagesort_145 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[13].ss                                                                      |                                                                       jet1_stagesort_146 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[14].ss                                                                      |                                                                       jet1_stagesort_147 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[15].ss                                                                      |                                                                       jet1_stagesort_148 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[16].ss                                                                      |                                                                       jet1_stagesort_149 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[17].ss                                                                      |                                                                       jet1_stagesort_150 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[18].ss                                                                      |                                                                       jet1_stagesort_151 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[19].ss                                                                      |                                                                       jet1_stagesort_152 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[1].ss                                                                       |                                                                       jet1_stagesort_153 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[20].ss                                                                      |                                                                       jet1_stagesort_154 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[21].ss                                                                      |                                                                       jet1_stagesort_155 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[22].ss                                                                      |                                                                       jet1_stagesort_156 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[23].ss                                                                      |                                                                       jet1_stagesort_157 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[24].ss                                                                      |                                                                       jet1_stagesort_158 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[25].ss                                                                      |                                                                       jet1_stagesort_159 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[26].ss                                                                      |                                                                       jet1_stagesort_160 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[27].ss                                                                      |                                                                       jet1_stagesort_161 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[28].ss                                                                      |                                                                       jet1_stagesort_162 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[29].ss                                                                      |                                                                       jet1_stagesort_163 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[2].ss                                                                       |                                                                       jet1_stagesort_164 |    250(0.01%) |    250(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[30].ss                                                                      |                                                                       jet1_stagesort_165 |    198(0.01%) |    198(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[31].ss                                                                      |                                                                       jet1_stagesort_166 |    104(0.01%) |    104(0.01%) |   0(0.00%) |   0(0.00%) |    350(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[32].ss                                                                      |                                                                       jet1_stagesort_167 |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |    441(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[33].ss                                                                      |                                                                       jet1_stagesort_168 |    112(0.01%) |    112(0.01%) |   0(0.00%) |   0(0.00%) |    444(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[34].ss                                                                      |                                                                       jet1_stagesort_169 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    447(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[35].ss                                                                      |                                                                       jet1_stagesort_170 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    446(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[36].ss                                                                      |                                                                       jet1_stagesort_171 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    445(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[37].ss                                                                      |                                                                       jet1_stagesort_172 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    447(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[38].ss                                                                      |                                                                       jet1_stagesort_173 |    114(0.01%) |    114(0.01%) |   0(0.00%) |   0(0.00%) |    447(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[39].ss                                                                      |                                                                       jet1_stagesort_174 |    125(0.01%) |    125(0.01%) |   0(0.00%) |   0(0.00%) |    351(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[3].ss                                                                       |                                                                       jet1_stagesort_175 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[4].ss                                                                       |                                                                       jet1_stagesort_176 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[5].ss                                                                       |                                                                       jet1_stagesort_177 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[6].ss                                                                       |                                                                       jet1_stagesort_178 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[7].ss                                                                       |                                                                       jet1_stagesort_179 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[8].ss                                                                       |                                                                       jet1_stagesort_180 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[9].ss                                                                       |                                                                       jet1_stagesort_181 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wta_block[1].wta_out_0                                                                |                                                             jet1_wta_out__parameterized0 |   3059(0.09%) |   3059(0.09%) |   0(0.00%) |   0(0.00%) |   1589(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (wta_block[1].wta_out_0)                                                            |                                                             jet1_wta_out__parameterized0 |     44(0.01%) |     44(0.01%) |   0(0.00%) |   0(0.00%) |     81(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             sbo_0                                                                               |                                                                  jet1_stageblock_out_128 |   3016(0.09%) |   3016(0.09%) |   0(0.00%) |   0(0.00%) |   1508(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (sbo_0)                                                                           |                                                                  jet1_stageblock_out_128 |    181(0.01%) |    181(0.01%) |   0(0.00%) |   0(0.00%) |    218(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[0].sto_0                                                                  |                                                                       jet1_stage_out_129 |    234(0.01%) |    234(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[1].sto_0                                                                  |                                                                       jet1_stage_out_130 |    234(0.01%) |    234(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[2].sto_0                                                                  |                                                                       jet1_stage_out_131 |    254(0.01%) |    254(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[3].sto_0                                                                  |                                                                       jet1_stage_out_132 |    430(0.01%) |    430(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[4].sto_0                                                                  |                                                                       jet1_stage_out_133 |    224(0.01%) |    224(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[5].sto_0                                                                  |                                                                       jet1_stage_out_134 |    212(0.01%) |    212(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[6].sto_0                                                                  |                                                                       jet1_stage_out_135 |    218(0.01%) |    218(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[7].sto_0                                                                  |                                                                       jet1_stage_out_136 |    384(0.01%) |    384(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[8].sto_0                                                                  |                                                                       jet1_stage_out_137 |    266(0.01%) |    266(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[9].sto_0                                                                  |                                                                       jet1_stage_out_138 |    394(0.01%) |    394(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wta_block[2].wta_in_0                                                                 |                                                                           jet1_wta_in_16 |   9237(0.27%) |   9061(0.27%) | 176(0.01%) |   0(0.00%) |   9498(0.14%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (wta_block[2].wta_in_0)                                                             |                                                                           jet1_wta_in_16 |    749(0.02%) |    749(0.02%) |   0(0.00%) |   0(0.00%) |    122(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             sb_0                                                                                |                                                                       jet1_stageblock_81 |   8492(0.25%) |   8316(0.25%) | 176(0.01%) |   0(0.00%) |   9376(0.14%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (sb_0)                                                                            |                                                                       jet1_stageblock_81 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |   1440(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               clf_m                                                                             |                                                                       jet1_clist_fifo_82 |    145(0.01%) |     57(0.01%) |  88(0.01%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (clf_m)                                                                         |                                                                       jet1_clist_fifo_82 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[0].sdoc                                                               |                                                           jet1_simple_dual_one_clock_126 |     54(0.01%) |     10(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[1].sdoc                                                               |                                                           jet1_simple_dual_one_clock_127 |     65(0.01%) |     21(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               olf_m                                                                             |                                                                       jet1_clist_fifo_83 |    168(0.01%) |     80(0.01%) |  88(0.01%) |   0(0.00%) |     78(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (olf_m)                                                                         |                                                                       jet1_clist_fifo_83 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |     78(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[0].sdoc                                                               |                                                           jet1_simple_dual_one_clock_124 |     45(0.01%) |      1(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[1].sdoc                                                               |                                                           jet1_simple_dual_one_clock_125 |    102(0.01%) |     58(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[0].ss                                                                       |                                                                        jet1_stagesort_84 |    262(0.01%) |    262(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[10].ss                                                                      |                                                                        jet1_stagesort_85 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[11].ss                                                                      |                                                                        jet1_stagesort_86 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[12].ss                                                                      |                                                                        jet1_stagesort_87 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[13].ss                                                                      |                                                                        jet1_stagesort_88 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[14].ss                                                                      |                                                                        jet1_stagesort_89 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[15].ss                                                                      |                                                                        jet1_stagesort_90 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[16].ss                                                                      |                                                                        jet1_stagesort_91 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[17].ss                                                                      |                                                                        jet1_stagesort_92 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[18].ss                                                                      |                                                                        jet1_stagesort_93 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[19].ss                                                                      |                                                                        jet1_stagesort_94 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[1].ss                                                                       |                                                                        jet1_stagesort_95 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[20].ss                                                                      |                                                                        jet1_stagesort_96 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[21].ss                                                                      |                                                                        jet1_stagesort_97 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[22].ss                                                                      |                                                                        jet1_stagesort_98 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[23].ss                                                                      |                                                                        jet1_stagesort_99 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[24].ss                                                                      |                                                                       jet1_stagesort_100 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[25].ss                                                                      |                                                                       jet1_stagesort_101 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[26].ss                                                                      |                                                                       jet1_stagesort_102 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[27].ss                                                                      |                                                                       jet1_stagesort_103 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[28].ss                                                                      |                                                                       jet1_stagesort_104 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[29].ss                                                                      |                                                                       jet1_stagesort_105 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[2].ss                                                                       |                                                                       jet1_stagesort_106 |    250(0.01%) |    250(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[30].ss                                                                      |                                                                       jet1_stagesort_107 |    198(0.01%) |    198(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[31].ss                                                                      |                                                                       jet1_stagesort_108 |    103(0.01%) |    103(0.01%) |   0(0.00%) |   0(0.00%) |    350(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[32].ss                                                                      |                                                                       jet1_stagesort_109 |    116(0.01%) |    116(0.01%) |   0(0.00%) |   0(0.00%) |    443(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[33].ss                                                                      |                                                                       jet1_stagesort_110 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    444(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[34].ss                                                                      |                                                                       jet1_stagesort_111 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    446(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[35].ss                                                                      |                                                                       jet1_stagesort_112 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    446(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[36].ss                                                                      |                                                                       jet1_stagesort_113 |    112(0.01%) |    112(0.01%) |   0(0.00%) |   0(0.00%) |    445(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[37].ss                                                                      |                                                                       jet1_stagesort_114 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    446(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[38].ss                                                                      |                                                                       jet1_stagesort_115 |    114(0.01%) |    114(0.01%) |   0(0.00%) |   0(0.00%) |    442(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[39].ss                                                                      |                                                                       jet1_stagesort_116 |    126(0.01%) |    126(0.01%) |   0(0.00%) |   0(0.00%) |    351(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[3].ss                                                                       |                                                                       jet1_stagesort_117 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[4].ss                                                                       |                                                                       jet1_stagesort_118 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[5].ss                                                                       |                                                                       jet1_stagesort_119 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[6].ss                                                                       |                                                                       jet1_stagesort_120 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[7].ss                                                                       |                                                                       jet1_stagesort_121 |    230(0.01%) |    230(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[8].ss                                                                       |                                                                       jet1_stagesort_122 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[9].ss                                                                       |                                                                       jet1_stagesort_123 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wta_block[2].wta_out_0                                                                |                                                             jet1_wta_out__parameterized1 |   3043(0.09%) |   3043(0.09%) |   0(0.00%) |   0(0.00%) |   1590(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (wta_block[2].wta_out_0)                                                            |                                                             jet1_wta_out__parameterized1 |     43(0.01%) |     43(0.01%) |   0(0.00%) |   0(0.00%) |     79(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             sbo_0                                                                               |                                                                   jet1_stageblock_out_70 |   3000(0.09%) |   3000(0.09%) |   0(0.00%) |   0(0.00%) |   1511(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (sbo_0)                                                                           |                                                                   jet1_stageblock_out_70 |    178(0.01%) |    178(0.01%) |   0(0.00%) |   0(0.00%) |    221(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[0].sto_0                                                                  |                                                                        jet1_stage_out_71 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[1].sto_0                                                                  |                                                                        jet1_stage_out_72 |    233(0.01%) |    233(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[2].sto_0                                                                  |                                                                        jet1_stage_out_73 |    254(0.01%) |    254(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[3].sto_0                                                                  |                                                                        jet1_stage_out_74 |    422(0.01%) |    422(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[4].sto_0                                                                  |                                                                        jet1_stage_out_75 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[5].sto_0                                                                  |                                                                        jet1_stage_out_76 |    216(0.01%) |    216(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[6].sto_0                                                                  |                                                                        jet1_stage_out_77 |    209(0.01%) |    209(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[7].sto_0                                                                  |                                                                        jet1_stage_out_78 |    378(0.01%) |    378(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[8].sto_0                                                                  |                                                                        jet1_stage_out_79 |    262(0.01%) |    262(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[9].sto_0                                                                  |                                                                        jet1_stage_out_80 |    399(0.01%) |    399(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wta_block[3].wta_in_0                                                                 |                                                                           jet1_wta_in_17 |   9239(0.27%) |   9063(0.27%) | 176(0.01%) |   0(0.00%) |   9497(0.14%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (wta_block[3].wta_in_0)                                                             |                                                                           jet1_wta_in_17 |    749(0.02%) |    749(0.02%) |   0(0.00%) |   0(0.00%) |    121(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             sb_0                                                                                |                                                                          jet1_stageblock |   8496(0.25%) |   8320(0.25%) | 176(0.01%) |   0(0.00%) |   9376(0.14%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (sb_0)                                                                            |                                                                          jet1_stageblock |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |   1440(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               clf_m                                                                             |                                                                          jet1_clist_fifo |    145(0.01%) |     57(0.01%) |  88(0.01%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (clf_m)                                                                         |                                                                          jet1_clist_fifo |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[0].sdoc                                                               |                                                            jet1_simple_dual_one_clock_68 |     54(0.01%) |     10(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[1].sdoc                                                               |                                                            jet1_simple_dual_one_clock_69 |     65(0.01%) |     21(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               olf_m                                                                             |                                                                       jet1_clist_fifo_27 |    167(0.01%) |     79(0.01%) |  88(0.01%) |   0(0.00%) |     78(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 (olf_m)                                                                         |                                                                       jet1_clist_fifo_27 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |     78(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[0].sdoc                                                               |                                                               jet1_simple_dual_one_clock |     45(0.01%) |      1(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|                 BUFFERNUM[1].sdoc                                                               |                                                            jet1_simple_dual_one_clock_67 |    101(0.01%) |     57(0.01%) |  44(0.01%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[0].ss                                                                       |                                                                           jet1_stagesort |    262(0.01%) |    262(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[10].ss                                                                      |                                                                        jet1_stagesort_28 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[11].ss                                                                      |                                                                        jet1_stagesort_29 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[12].ss                                                                      |                                                                        jet1_stagesort_30 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[13].ss                                                                      |                                                                        jet1_stagesort_31 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[14].ss                                                                      |                                                                        jet1_stagesort_32 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[15].ss                                                                      |                                                                        jet1_stagesort_33 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[16].ss                                                                      |                                                                        jet1_stagesort_34 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[17].ss                                                                      |                                                                        jet1_stagesort_35 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[18].ss                                                                      |                                                                        jet1_stagesort_36 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[19].ss                                                                      |                                                                        jet1_stagesort_37 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[1].ss                                                                       |                                                                        jet1_stagesort_38 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[20].ss                                                                      |                                                                        jet1_stagesort_39 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[21].ss                                                                      |                                                                        jet1_stagesort_40 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[22].ss                                                                      |                                                                        jet1_stagesort_41 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[23].ss                                                                      |                                                                        jet1_stagesort_42 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[24].ss                                                                      |                                                                        jet1_stagesort_43 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[25].ss                                                                      |                                                                        jet1_stagesort_44 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[26].ss                                                                      |                                                                        jet1_stagesort_45 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[27].ss                                                                      |                                                                        jet1_stagesort_46 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[28].ss                                                                      |                                                                        jet1_stagesort_47 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[29].ss                                                                      |                                                                        jet1_stagesort_48 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[2].ss                                                                       |                                                                        jet1_stagesort_49 |    250(0.01%) |    250(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[30].ss                                                                      |                                                                        jet1_stagesort_50 |    198(0.01%) |    198(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[31].ss                                                                      |                                                                        jet1_stagesort_51 |    104(0.01%) |    104(0.01%) |   0(0.00%) |   0(0.00%) |    350(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[32].ss                                                                      |                                                                        jet1_stagesort_52 |    116(0.01%) |    116(0.01%) |   0(0.00%) |   0(0.00%) |    445(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[33].ss                                                                      |                                                                        jet1_stagesort_53 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    446(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[34].ss                                                                      |                                                                        jet1_stagesort_54 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    445(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[35].ss                                                                      |                                                                        jet1_stagesort_55 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    445(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[36].ss                                                                      |                                                                        jet1_stagesort_56 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    444(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[37].ss                                                                      |                                                                        jet1_stagesort_57 |    113(0.01%) |    113(0.01%) |   0(0.00%) |   0(0.00%) |    444(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[38].ss                                                                      |                                                                        jet1_stagesort_58 |    114(0.01%) |    114(0.01%) |   0(0.00%) |   0(0.00%) |    443(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[39].ss                                                                      |                                                                        jet1_stagesort_59 |    126(0.01%) |    126(0.01%) |   0(0.00%) |   0(0.00%) |    351(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[3].ss                                                                       |                                                                        jet1_stagesort_60 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[4].ss                                                                       |                                                                        jet1_stagesort_61 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[5].ss                                                                       |                                                                        jet1_stagesort_62 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[6].ss                                                                       |                                                                        jet1_stagesort_63 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[7].ss                                                                       |                                                                        jet1_stagesort_64 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[8].ss                                                                       |                                                                        jet1_stagesort_65 |    232(0.01%) |    232(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               stage[9].ss                                                                       |                                                                        jet1_stagesort_66 |    231(0.01%) |    231(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wta_block[3].wta_out_0                                                                |                                                             jet1_wta_out__parameterized2 |   3032(0.09%) |   3032(0.09%) |   0(0.00%) |   0(0.00%) |   1588(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (wta_block[3].wta_out_0)                                                            |                                                             jet1_wta_out__parameterized2 |     45(0.01%) |     45(0.01%) |   0(0.00%) |   0(0.00%) |     80(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             sbo_0                                                                               |                                                                      jet1_stageblock_out |   2988(0.09%) |   2988(0.09%) |   0(0.00%) |   0(0.00%) |   1508(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (sbo_0)                                                                           |                                                                      jet1_stageblock_out |    179(0.01%) |    179(0.01%) |   0(0.00%) |   0(0.00%) |    218(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[0].sto_0                                                                  |                                                                           jet1_stage_out |    236(0.01%) |    236(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[1].sto_0                                                                  |                                                                        jet1_stage_out_18 |    233(0.01%) |    233(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[2].sto_0                                                                  |                                                                        jet1_stage_out_19 |    253(0.01%) |    253(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[3].sto_0                                                                  |                                                                        jet1_stage_out_20 |    420(0.01%) |    420(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[4].sto_0                                                                  |                                                                        jet1_stage_out_21 |    230(0.01%) |    230(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[5].sto_0                                                                  |                                                                        jet1_stage_out_22 |    209(0.01%) |    209(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[6].sto_0                                                                  |                                                                        jet1_stage_out_23 |    208(0.01%) |    208(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[7].sto_0                                                                  |                                                                        jet1_stage_out_24 |    379(0.01%) |    379(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[8].sto_0                                                                  |                                                                        jet1_stage_out_25 |    263(0.01%) |    263(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               genblk1[9].sto_0                                                                  |                                                                        jet1_stage_out_26 |    400(0.01%) |    400(0.01%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     JET_MET_APP_IN_SLR1                                                                         |                                                                      app__parameterized5 |   2836(0.08%) |   2804(0.08%) |  32(0.01%) |   0(0.00%) |   6331(0.09%) |  15(0.30%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (JET_MET_APP_IN_SLR1)                                                                     |                                                                      app__parameterized5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     64(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                              pipeline__parameterized1__6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       acc_error_2t_inst                                                                         |                                                                         acc_error_2t_568 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_rx2t_inst                                                                            |                                                                           BCID_rx_2t_569 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_0                                                                            |                                                            reg_array__parameterized2_651 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_1                                                                            |                                                            reg_array__parameterized2_652 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       data_out_mux                                                                              |                                                                    mux21__parameterized6 |     38(0.01%) |     38(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                        |                                                                                   logger |    247(0.01%) |    247(0.01%) |   0(0.00%) |   0(0.00%) |    255(0.01%) |   9(0.18%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                    |                                                                                   logger |     71(0.01%) |     71(0.01%) |   0(0.00%) |   0(0.00%) |    184(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         APU_RAM                                                                                 |                                                                    ipbus_ram_wrapper_640 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (APU_RAM)                                                                             |                                                                    ipbus_ram_wrapper_640 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_650 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                                |                                                                    ipbus_ram_wrapper_641 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                            |                                                                    ipbus_ram_wrapper_641 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_649 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ERROR_RAM                                                                               |                                                    ipbus_ram_wrapper__parameterized1_642 |     47(0.01%) |     47(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (ERROR_RAM)                                                                           |                                                    ipbus_ram_wrapper__parameterized1_642 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized4_648 |     37(0.01%) |     37(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                            |                                                    ipbus_ram_wrapper__parameterized0_643 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                        |                                                    ipbus_ram_wrapper__parameterized0_643 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_647 |     39(0.01%) |     39(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[0].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_644 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[0].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_644 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_646 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         logger_registers                                                                        |                                                      ipbus_ctrlreg_v__parameterized2_645 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                                 |                                                      ipbus_ctrlreg_v__parameterized1_570 |    948(0.03%) |    948(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[0].input0_hf_rxtx                                                                 |                                                                         sync_hf_rxtx_571 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                               dmux14__parameterized1_629 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                mux41__parameterized3_630 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                            reg_array__parameterized1_631 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_632 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_633 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_634 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                mux41__parameterized2_635 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                            reg_array__parameterized0_636 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_637 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_638 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_639 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd1                                                                                  |                                                                             edge_reg_573 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd2                                                                                  |                                                                             edge_reg_574 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd3                                                                                  |                                                                             edge_reg_575 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       err_fsm                                                                                   |                                                                            error_fsm_576 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     28(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       hf_fsm                                                                                    |                                                           head_foot_fsm__parameterized11 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |     69(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__23 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    450(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                      sync_mt_fifo_v2__parameterized5_577 |     96(0.01%) |     96(0.01%) |   0(0.00%) |   0(0.00%) |    233(0.01%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                      sync_mt_fifo_v2__parameterized5_577 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    129(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                   sync_fifo_cntrl_v2__parameterized1_600 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized1_600 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized4_623 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized4_624 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_625 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized1_626 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_627 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized5_628 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized1_601 |     26(0.01%) |     26(0.01%) |   0(0.00%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized1_601 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized4_617 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized4_618 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_619 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized1_620 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_621 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized5_622 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized1_602 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized1_602 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized4_611 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized4_612 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_613 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized1_614 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_615 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized5_616 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized1_603 |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized1_603 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized4_605 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized4_606 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_607 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized1_608 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_609 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized5_610 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                           dp_bram_v2__parameterized2_604 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       output_nibbler                                                                            |                                                                  nibbler__parameterized7 |   1231(0.04%) |   1199(0.04%) |  32(0.01%) |   0(0.00%) |   2713(0.04%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (output_nibbler)                                                                        |                                                                  nibbler__parameterized7 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         FREE_FROM_SLR_output_pipeline                                                           |                                                                             pipeline__22 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.TGEN_VERILOG                                                             |                                                                    tgen__parameterized15 |     91(0.01%) |     91(0.01%) |   0(0.00%) |   0(0.00%) |     53(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.timer_source                                                             |                                                             time_nibbler__parameterized1 |    150(0.01%) |    118(0.01%) |  32(0.01%) |   0(0.00%) |    116(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCE_OR_SINK.timer_source)                                                         |                                                             time_nibbler__parameterized1 |     96(0.01%) |     96(0.01%) |   0(0.00%) |   0(0.00%) |     90(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           DESTINATION_TGEN.mem                                                                  |                                                               dp_ram_ipb__parameterized4 |     54(0.01%) |     22(0.01%) |  32(0.01%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (DESTINATION_TGEN.mem)                                                              |                                                               dp_ram_ipb__parameterized4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             memory                                                                              |                                                     dual_port_bram_infer__parameterized6 |     51(0.01%) |     19(0.01%) |  32(0.01%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             syncreg_w_inst                                                                      |                                                                            syncreg_w_599 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mem                                                                                     |                                                               dp_ram_ipb__parameterized5 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (mem)                                                                                 |                                                               dp_ram_ipb__parameterized5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                     dual_port_bram_infer__parameterized7 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                            syncreg_w_598 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         perf_count_inst                                                                         |                                                           perf_count__parameterized7_596 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.FREE_FROM_SLR_input_pipeline                                                        |                                                                             pipeline__21 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    204(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.nibbler_registers                                                                   |                                                      ipbus_ctrlreg_v__parameterized1_597 |    983(0.03%) |    983(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       pulse_we                                                                                  |                                                                            pulse_cdc_579 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                              |                                                                            pulse_cdc_579 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                            syncreg_w_595 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       rd_done_cda                                                                               |                                                                  cooldown_arbiter_v2_580 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sync_inst                                                                                 |                                                                          sync_fsm_v6_581 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd1                                                                                       |                                                                      watch_dog_timer_582 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (wd1)                                                                                   |                                                                      watch_dog_timer_582 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         pc1                                                                                     |                                                           perf_count__parameterized3_594 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd2                                                                                       |                                                                   watch_dog_timer_2t_583 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_590 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_590 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_593 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_591 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_591 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_592 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd3                                                                                       |                                                                   watch_dog_timer_2t_584 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_586 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_586 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_589 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_587 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_587 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_588 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wr_done_cda                                                                               |                                                                  cooldown_arbiter_v2_585 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     JET_MET_APU_IN_SLR1                                                                         |                                                                          jet_met_lib_apu |    281(0.01%) |    281(0.01%) |   0(0.00%) |   0(0.00%) |    305(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   4(0.03%) |
|       apu_registers                                                                             |                                                       ipbus_ctrlreg_v__parameterized3_13 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       u_met_engine                                                                              |                                                                               MET_Engine |    249(0.01%) |    249(0.01%) |   0(0.00%) |   0(0.00%) |    177(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   4(0.03%) |
|         (u_met_engine)                                                                          |                                                                               MET_Engine |     42(0.01%) |     42(0.01%) |   0(0.00%) |   0(0.00%) |     77(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         jet_latch                                                                               |                                                                                MET_Latch |     16(0.01%) |     16(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sum_square                                                                              |                                                                           MET_SUM_SQUARE |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   2(0.01%) |
|         vector_accum                                                                            |                                                                            MET_XY_Vector |    183(0.01%) |    183(0.01%) |   0(0.00%) |   0(0.00%) |     91(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   2(0.01%) |
|           (vector_accum)                                                                        |                                                                            MET_XY_Vector |    183(0.01%) |    183(0.01%) |   0(0.00%) |   0(0.00%) |     91(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   2(0.01%) |
|           trig_inst                                                                             |                                                                                     trig |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     LAR_PREPROC1_IN_SLR3                                                                        |                                                                                  nibbler |   1344(0.04%) |   1344(0.04%) |   0(0.00%) |   0(0.00%) |   3070(0.05%) |   7(0.14%) |  2(0.02%) |  0(0.00%) |   0(0.00%) |
|       (LAR_PREPROC1_IN_SLR3)                                                                    |                                                                                  nibbler |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     17(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                                              pipeline__2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    834(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       SOURCE_OR_SINK.TGEN_VERILOG                                                               |                                                                                     tgen |    195(0.01%) |    195(0.01%) |   0(0.00%) |   0(0.00%) |     55(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       SOURCE_OR_SINK.timer_source                                                               |                                                                             time_nibbler |    119(0.01%) |    119(0.01%) |   0(0.00%) |   0(0.00%) |    106(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|         (SOURCE_OR_SINK.timer_source)                                                           |                                                                             time_nibbler |    109(0.01%) |    109(0.01%) |   0(0.00%) |   0(0.00%) |     96(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         DESTINATION_TGEN.mem                                                                    |                                                                               dp_ram_ipb |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           (DESTINATION_TGEN.mem)                                                                |                                                                               dp_ram_ipb |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                                     dual_port_bram_infer |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                             syncreg_w_12 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mem                                                                                       |                                                               dp_ram_ipb__parameterized0 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   7(0.14%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|         (mem)                                                                                   |                                                               dp_ram_ipb__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         memory                                                                                  |                                                     dual_port_bram_infer__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   7(0.14%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                             syncreg_w_11 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sim.FREE_FROM_SLR_input_pipeline                                                          |                                                                              pipeline__1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sim.nibbler_registers                                                                     |                                                       ipbus_ctrlreg_v__parameterized1_10 |   1026(0.03%) |   1026(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     MINI_HYPO_APP_IN_SLR0                                                                       |                                                                      app__parameterized6 |   4268(0.13%) |   4260(0.13%) |   8(0.01%) |   0(0.00%) |   9657(0.14%) |  33(0.67%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (MINI_HYPO_APP_IN_SLR0)                                                                   |                                                                      app__parameterized6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     61(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                                 pipeline__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       acc_error_2t_inst                                                                         |                                                                             acc_error_2t |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_priority_sel                                                                         |                                                                         priority_encoder |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_reg                                                                                  |                                                                           bcid_error_reg |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_rx2t_inst                                                                            |                                                                               BCID_rx_2t |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_0                                                                            |                                                                reg_array__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_1                                                                            |                                                            reg_array__parameterized2_567 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       data_out_mux                                                                              |                                                                   mux21__parameterized11 |     38(0.01%) |     38(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                        |                                                                   logger__parameterized1 |    377(0.01%) |    377(0.01%) |   0(0.00%) |   0(0.00%) |    563(0.01%) |  17(0.34%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                    |                                                                   logger__parameterized1 |    125(0.01%) |    125(0.01%) |   0(0.00%) |   0(0.00%) |    448(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         APU_RAM                                                                                 |                                                                        ipbus_ram_wrapper |     33(0.01%) |     33(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (APU_RAM)                                                                             |                                                                        ipbus_ram_wrapper |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_566 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                                |                                                                    ipbus_ram_wrapper_554 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                            |                                                                    ipbus_ram_wrapper_554 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_565 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ERROR_RAM                                                                               |                                                        ipbus_ram_wrapper__parameterized1 |     44(0.01%) |     44(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (ERROR_RAM)                                                                           |                                                        ipbus_ram_wrapper__parameterized1 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                     dual_port_bram_infer__parameterized4 |     34(0.01%) |     34(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                            |                                                        ipbus_ram_wrapper__parameterized0 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                        |                                                        ipbus_ram_wrapper__parameterized0 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_564 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[0].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_555 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[0].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_555 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_563 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[1].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_556 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[1].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_556 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_562 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[2].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_557 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[2].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_557 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_561 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[3].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_558 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[3].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_558 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized3_560 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[4].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_559 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[4].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_559 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                     dual_port_bram_infer__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         logger_registers                                                                        |                                                          ipbus_ctrlreg_v__parameterized2 |    121(0.01%) |    121(0.01%) |   0(0.00%) |   0(0.00%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                                 |                                                      ipbus_ctrlreg_v__parameterized1_341 |   1213(0.04%) |   1213(0.04%) |   0(0.00%) |   0(0.00%) |   2051(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[0].input0_hf_rxtx                                                                 |                                                                             sync_hf_rxtx |    144(0.01%) |    144(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                               dmux14__parameterized1_543 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                mux41__parameterized3_544 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                            reg_array__parameterized1_545 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_546 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_547 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_548 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                mux41__parameterized2_549 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                            reg_array__parameterized0_550 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_551 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_552 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_553 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[1].input0_hf_rxtx                                                                 |                                                                         sync_hf_rxtx_342 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                               dmux14__parameterized1_532 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                mux41__parameterized3_533 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                            reg_array__parameterized1_534 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_535 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_536 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_537 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                mux41__parameterized2_538 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                            reg_array__parameterized0_539 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_540 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_541 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_542 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[2].input0_hf_rxtx                                                                 |                                                                         sync_hf_rxtx_343 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                               dmux14__parameterized1_521 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                mux41__parameterized3_522 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                            reg_array__parameterized1_523 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_524 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_525 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_526 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                mux41__parameterized2_527 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                            reg_array__parameterized0_528 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_529 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_530 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_531 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[3].input0_hf_rxtx                                                                 |                                                                         sync_hf_rxtx_344 |    110(0.01%) |    110(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                               dmux14__parameterized1_510 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                mux41__parameterized3_511 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                            reg_array__parameterized1_512 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_513 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_514 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_515 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                mux41__parameterized2_516 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                            reg_array__parameterized0_517 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_518 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_519 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_520 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[4].input0_hf_rxtx                                                                 |                                                                         sync_hf_rxtx_345 |    106(0.01%) |    106(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                                   dmux14__parameterized1 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                    mux41__parameterized3 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                                reg_array__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_504 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_505 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_506 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                    mux41__parameterized2 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                                reg_array__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_507 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_508 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_509 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd1                                                                                  |                                                                             edge_reg_346 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd2                                                                                  |                                                                             edge_reg_347 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd3                                                                                  |                                                                             edge_reg_348 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       err_fsm                                                                                   |                                                                                error_fsm |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     29(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       hf_fsm                                                                                    |                                                           head_foot_fsm__parameterized13 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     70(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__26 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                          sync_mt_fifo_v2__parameterized5 |    104(0.01%) |    104(0.01%) |   0(0.00%) |   0(0.00%) |    169(0.01%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                          sync_mt_fifo_v2__parameterized5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                       sync_fifo_cntrl_v2__parameterized1 |     29(0.01%) |     29(0.01%) |   0(0.00%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                       sync_fifo_cntrl_v2__parameterized1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized4_498 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized4_499 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_500 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized1_501 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_502 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized5_503 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized1_481 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized1_481 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized4_492 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized4_493 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_494 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized1_495 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_496 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized5_497 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized1_482 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized1_482 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized4_486 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized4_487 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_488 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized1_489 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_490 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized5_491 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized1_483 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized1_483 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                                reg_array__parameterized4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized4_484 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                       fifo_addr_count_v2__parameterized1 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                                 sync_rd_side_roll_detect__parameterized1 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized1_485 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                               perf_count__parameterized5 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                               dp_bram_v2__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[1].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__27 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                          sync_mt_fifo_v2__parameterized7 |    103(0.01%) |    103(0.01%) |   0(0.00%) |   0(0.00%) |    189(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (mainfor[1].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                          sync_mt_fifo_v2__parameterized7 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_452 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_452 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_475 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_476 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_477 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_478 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_479 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_480 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_453 |     36(0.01%) |     36(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_453 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_469 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_470 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_471 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_472 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_473 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_474 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_454 |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_454 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_463 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_464 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_465 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_466 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_467 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_468 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_455 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_455 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_457 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_458 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_459 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_460 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_461 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_462 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                           dp_bram_v2__parameterized3_456 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[2].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__28 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                      sync_mt_fifo_v2__parameterized7_349 |    121(0.01%) |    121(0.01%) |   0(0.00%) |   0(0.00%) |    189(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (mainfor[2].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                      sync_mt_fifo_v2__parameterized7_349 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_423 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_423 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_446 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_447 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_448 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_449 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_450 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_451 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_424 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_424 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_440 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_441 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_442 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_443 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_444 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_445 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_425 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_425 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_434 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_435 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_436 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_437 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_438 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_439 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_426 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_426 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_428 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_429 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_430 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_431 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_432 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_433 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                           dp_bram_v2__parameterized3_427 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[3].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__29 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                      sync_mt_fifo_v2__parameterized7_350 |    121(0.01%) |    121(0.01%) |   0(0.00%) |   0(0.00%) |    189(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (mainfor[3].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                      sync_mt_fifo_v2__parameterized7_350 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_394 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_394 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_417 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_418 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_419 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_420 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_421 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_422 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_395 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_395 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_411 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_412 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_413 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_414 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_415 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_416 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_396 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_396 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_405 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_406 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_407 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_408 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_409 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_410 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_397 |     27(0.01%) |     27(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_397 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_399 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_400 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_401 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_402 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_403 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_404 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                           dp_bram_v2__parameterized3_398 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[4].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__30 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[4].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                      sync_mt_fifo_v2__parameterized7_351 |    102(0.01%) |    102(0.01%) |   0(0.00%) |   0(0.00%) |    189(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (mainfor[4].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                      sync_mt_fifo_v2__parameterized7_351 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                       sync_fifo_cntrl_v2__parameterized2 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                       sync_fifo_cntrl_v2__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_388 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_389 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_390 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_391 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_392 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_393 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_371 |     36(0.01%) |     36(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_371 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_382 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_383 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_384 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_385 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_386 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_387 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_372 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_372 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized5_376 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_377 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_378 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized2_379 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_380 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized7_381 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized2_373 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |     31(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized2_373 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                                reg_array__parameterized5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized5_374 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                       fifo_addr_count_v2__parameterized2 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                                 sync_rd_side_roll_detect__parameterized2 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized2_375 |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                               perf_count__parameterized7 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                               dp_bram_v2__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       merge_footer                                                                              |                                                                 array_or__parameterized1 |     64(0.01%) |     64(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       merge_head_snoop                                                                          |                                                                 array_or__parameterized2 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       output_nibbler                                                                            |                                                                  nibbler__parameterized8 |   1253(0.04%) |   1245(0.04%) |   8(0.01%) |   0(0.00%) |   2942(0.04%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (output_nibbler)                                                                        |                                                                  nibbler__parameterized8 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         FREE_FROM_SLR_output_pipeline                                                           |                                                                             pipeline__25 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    396(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.TGEN_VERILOG                                                             |                                                                    tgen__parameterized17 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.timer_source                                                             |                                                             time_nibbler__parameterized3 |    115(0.01%) |    107(0.01%) |   8(0.01%) |   0(0.00%) |    112(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCE_OR_SINK.timer_source)                                                         |                                                             time_nibbler__parameterized3 |     94(0.01%) |     94(0.01%) |   0(0.00%) |   0(0.00%) |     86(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           DESTINATION_TGEN.mem                                                                  |                                                           dp_ram_ipb__parameterized8_368 |     21(0.01%) |     13(0.01%) |   8(0.01%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (DESTINATION_TGEN.mem)                                                              |                                                           dp_ram_ipb__parameterized8_368 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             memory                                                                              |                                                dual_port_bram_infer__parameterized10_369 |     14(0.01%) |      6(0.01%) |   8(0.01%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             syncreg_w_inst                                                                      |                                                                            syncreg_w_370 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mem                                                                                     |                                                           dp_ram_ipb__parameterized9_363 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (mem)                                                                                 |                                                           dp_ram_ipb__parameterized9_363 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized11_366 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                            syncreg_w_367 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         perf_count_inst                                                                         |                                                           perf_count__parameterized9_364 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.FREE_FROM_SLR_input_pipeline                                                        |                                                                             pipeline__24 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    315(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.nibbler_registers                                                                   |                                                      ipbus_ctrlreg_v__parameterized1_365 |   1016(0.03%) |   1016(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       pulse_we                                                                                  |                                                                                pulse_cdc |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                              |                                                                                pulse_cdc |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                            syncreg_w_362 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       rd_done_cda                                                                               |                                                                      cooldown_arbiter_v2 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sync_inst                                                                                 |                                                                              sync_fsm_v6 |     15(0.01%) |     15(0.01%) |   0(0.00%) |   0(0.00%) |     21(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd1                                                                                       |                                                                          watch_dog_timer |     26(0.01%) |     26(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (wd1)                                                                                   |                                                                          watch_dog_timer |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         pc1                                                                                     |                                                           perf_count__parameterized3_361 |     26(0.01%) |     26(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd2                                                                                       |                                                                       watch_dog_timer_2t |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_357 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_357 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_360 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_358 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_358 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_359 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd3                                                                                       |                                                                   watch_dog_timer_2t_352 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_354 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_354 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_356 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_355 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_355 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                               perf_count__parameterized3 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wr_done_cda                                                                               |                                                                  cooldown_arbiter_v2_353 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     MINI_HYPO_APU_IN_SLR0                                                                       |                                                                       hypothesis_lib_apu |   2006(0.06%) |   2006(0.06%) |   0(0.00%) |   0(0.00%) |   2864(0.04%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (MINI_HYPO_APU_IN_SLR0)                                                                   |                                                                       hypothesis_lib_apu |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |    143(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       ALGORITHMS                                                                                |                                                                     HypothesisAlgorithms |   1969(0.06%) |   1969(0.06%) |   0(0.00%) |   0(0.00%) |   2711(0.04%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         Mul[0].U                                                                                |                                                                           Multiplicities |    642(0.02%) |    642(0.02%) |   0(0.00%) |   0(0.00%) |    841(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (Mul[0].U)                                                                            |                                                                           Multiplicities |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[0].M                                                                               |                                                                             Multiplicity |     93(0.01%) |     93(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[0].M)                                                                           |                                                                             Multiplicity |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                                  MultiplicityCounter_337 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                                          GenericSelector |     90(0.01%) |     90(0.01%) |   0(0.00%) |   0(0.00%) |    134(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                                          GenericSelector |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_338 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_339 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_340 |     85(0.01%) |     85(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[1].M                                                                               |                                                             Multiplicity__parameterized0 |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |    140(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[1].M)                                                                           |                                                             Multiplicity__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized0_333 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized0 |    115(0.01%) |    115(0.01%) |   0(0.00%) |   0(0.00%) |    134(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_334 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_335 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_336 |    105(0.01%) |    105(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[2].M                                                                               |                                                             Multiplicity__parameterized1 |     85(0.01%) |     85(0.01%) |   0(0.00%) |   0(0.00%) |    139(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[2].M)                                                                           |                                                             Multiplicity__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized1_329 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized1 |     84(0.01%) |     84(0.01%) |   0(0.00%) |   0(0.00%) |    134(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_330 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_331 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_332 |     83(0.01%) |     83(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[3].M                                                                               |                                                             Multiplicity__parameterized2 |    148(0.01%) |    148(0.01%) |   0(0.00%) |   0(0.00%) |    139(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[3].M)                                                                           |                                                             Multiplicity__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized1_325 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized2 |    147(0.01%) |    147(0.01%) |   0(0.00%) |   0(0.00%) |    134(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized2 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_326 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_327 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_328 |    145(0.01%) |    145(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[4].M                                                                               |                                                             Multiplicity__parameterized3 |    109(0.01%) |    109(0.01%) |   0(0.00%) |   0(0.00%) |    139(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[4].M)                                                                           |                                                             Multiplicity__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized1_321 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized3 |    108(0.01%) |    108(0.01%) |   0(0.00%) |   0(0.00%) |    134(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized3 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_322 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_323 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_324 |    105(0.01%) |    105(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[5].M                                                                               |                                                             Multiplicity__parameterized4 |     97(0.01%) |     97(0.01%) |   0(0.00%) |   0(0.00%) |    139(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[5].M)                                                                           |                                                             Multiplicity__parameterized4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized1_317 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized4 |     96(0.01%) |     96(0.01%) |   0(0.00%) |   0(0.00%) |    134(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized4 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_318 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_319 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_320 |     94(0.01%) |     94(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         Mul[1].U                                                                                |                                                           Multiplicities__parameterized0 |    293(0.01%) |    293(0.01%) |   0(0.00%) |   0(0.00%) |    433(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (Mul[1].U)                                                                            |                                                           Multiplicities__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[0].M                                                                               |                                                             Multiplicity__parameterized5 |     92(0.01%) |     92(0.01%) |   0(0.00%) |   0(0.00%) |    142(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[0].M)                                                                           |                                                             Multiplicity__parameterized5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized1_312 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized5 |     91(0.01%) |     91(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized5 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_313 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_314 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_oFlag.IndFlag                                                                 |                                                                        oFlagSelector_315 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_316 |     86(0.01%) |     86(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[1].M                                                                               |                                                             Multiplicity__parameterized6 |    109(0.01%) |    109(0.01%) |   0(0.00%) |   0(0.00%) |    144(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[1].M)                                                                           |                                                             Multiplicity__parameterized6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                                  MultiplicityCounter_307 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized6 |    106(0.01%) |    106(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized6 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_308 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_309 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_oFlag.IndFlag                                                                 |                                                                        oFlagSelector_310 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_311 |     96(0.01%) |     96(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[2].M                                                                               |                                                             Multiplicity__parameterized7 |     92(0.01%) |     92(0.01%) |   0(0.00%) |   0(0.00%) |    143(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[2].M)                                                                           |                                                             Multiplicity__parameterized7 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized0_302 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized7 |     90(0.01%) |     90(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized7 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_303 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_304 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_oFlag.IndFlag                                                                 |                                                                        oFlagSelector_305 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_306 |     88(0.01%) |     88(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         Mul[2].U                                                                                |                                                           Multiplicities__parameterized1 |    407(0.01%) |    407(0.01%) |   0(0.00%) |   0(0.00%) |    577(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (Mul[2].U)                                                                            |                                                           Multiplicities__parameterized1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[0].M                                                                               |                                                             Multiplicity__parameterized8 |    108(0.01%) |    108(0.01%) |   0(0.00%) |   0(0.00%) |    144(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[0].M)                                                                           |                                                             Multiplicity__parameterized8 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                                  MultiplicityCounter_297 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized8 |    105(0.01%) |    105(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized8 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_298 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_299 |     29(0.01%) |     29(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_bdtFlag.IndFlag                                                               |                                                                      bdtFlagSelector_300 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_301 |     74(0.01%) |     74(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[1].M                                                                               |                                                             Multiplicity__parameterized9 |     81(0.01%) |     81(0.01%) |   0(0.00%) |   0(0.00%) |    144(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[1].M)                                                                           |                                                             Multiplicity__parameterized9 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                                  MultiplicityCounter_292 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                          GenericSelector__parameterized9 |     78(0.01%) |     78(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                          GenericSelector__parameterized9 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_293 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_294 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_bdtFlag.IndFlag                                                               |                                                                      bdtFlagSelector_295 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_296 |     73(0.01%) |     73(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[2].M                                                                               |                                                            Multiplicity__parameterized10 |     76(0.01%) |     76(0.01%) |   0(0.00%) |   0(0.00%) |    143(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[2].M)                                                                           |                                                            Multiplicity__parameterized10 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized0_287 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                         GenericSelector__parameterized10 |     74(0.01%) |     74(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                         GenericSelector__parameterized10 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_288 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_289 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_bdtFlag.IndFlag                                                               |                                                                      bdtFlagSelector_290 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_291 |     73(0.01%) |     73(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[3].M                                                                               |                                                            Multiplicity__parameterized11 |    141(0.01%) |    141(0.01%) |   0(0.00%) |   0(0.00%) |    142(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[3].M)                                                                           |                                                            Multiplicity__parameterized11 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized1_283 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                         GenericSelector__parameterized11 |    140(0.01%) |    140(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                         GenericSelector__parameterized11 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_284 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_285 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_bdtFlag.IndFlag                                                               |                                                                          bdtFlagSelector |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_286 |    139(0.01%) |    139(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         Mul[3].U                                                                                |                                                           Multiplicities__parameterized2 |    311(0.01%) |    311(0.01%) |   0(0.00%) |   0(0.00%) |    427(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (Mul[3].U)                                                                            |                                                           Multiplicities__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[0].M                                                                               |                                                            Multiplicity__parameterized12 |    100(0.01%) |    100(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[0].M)                                                                           |                                                            Multiplicity__parameterized12 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized2_278 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                         GenericSelector__parameterized12 |    100(0.01%) |    100(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                         GenericSelector__parameterized12 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_279 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_280 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_oFlag.IndFlag                                                                 |                                                                        oFlagSelector_281 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_282 |     95(0.01%) |     95(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[1].M                                                                               |                                                            Multiplicity__parameterized13 |    115(0.01%) |    115(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[1].M)                                                                           |                                                            Multiplicity__parameterized13 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                  MultiplicityCounter__parameterized2_273 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                         GenericSelector__parameterized13 |    115(0.01%) |    115(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                         GenericSelector__parameterized13 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_274 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_275 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_oFlag.IndFlag                                                                 |                                                                        oFlagSelector_276 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_277 |    105(0.01%) |    105(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[2].M                                                                               |                                                            Multiplicity__parameterized14 |     96(0.01%) |     96(0.01%) |   0(0.00%) |   0(0.00%) |    141(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[2].M)                                                                           |                                                            Multiplicity__parameterized14 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                      MultiplicityCounter__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                         GenericSelector__parameterized14 |     96(0.01%) |     96(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                         GenericSelector__parameterized14 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_269 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_270 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_oFlag.IndFlag                                                                 |                                                                        oFlagSelector_271 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_272 |     94(0.01%) |     94(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         Mul[4].U                                                                                |                                                           Multiplicities__parameterized3 |    316(0.01%) |    316(0.01%) |   0(0.00%) |   0(0.00%) |    433(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (Mul[4].U)                                                                            |                                                           Multiplicities__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[0].M                                                                               |                                                            Multiplicity__parameterized15 |    100(0.01%) |    100(0.01%) |   0(0.00%) |   0(0.00%) |    142(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[0].M)                                                                           |                                                            Multiplicity__parameterized15 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                      MultiplicityCounter__parameterized1 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                         GenericSelector__parameterized15 |     99(0.01%) |     99(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                         GenericSelector__parameterized15 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_265 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_266 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_oFlag.IndFlag                                                                 |                                                                        oFlagSelector_267 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_268 |     94(0.01%) |     94(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[1].M                                                                               |                                                            Multiplicity__parameterized16 |    120(0.01%) |    120(0.01%) |   0(0.00%) |   0(0.00%) |    144(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[1].M)                                                                           |                                                            Multiplicity__parameterized16 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                                      MultiplicityCounter |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                         GenericSelector__parameterized16 |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                         GenericSelector__parameterized16 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                           EtSelector_261 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                          EtaSelector_262 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_oFlag.IndFlag                                                                 |                                                                        oFlagSelector_263 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                      ipbus_ctrlreg_v__parameterized4_264 |    106(0.01%) |    106(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           FG[2].M                                                                               |                                                            Multiplicity__parameterized17 |     96(0.01%) |     96(0.01%) |   0(0.00%) |   0(0.00%) |    143(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (FG[2].M)                                                                           |                                                            Multiplicity__parameterized17 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genCounter                                                                          |                                                      MultiplicityCounter__parameterized0 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             genSelector                                                                         |                                                         GenericSelector__parameterized17 |     94(0.01%) |     94(0.01%) |   0(0.00%) |   0(0.00%) |    137(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               (genSelector)                                                                     |                                                         GenericSelector__parameterized17 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtSel                                                                             |                                                                               EtSelector |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               EtaSel                                                                            |                                                                              EtaSelector |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               gen_oFlag.IndFlag                                                                 |                                                                            oFlagSelector |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               par_ipbus.app_registers                                                           |                                                          ipbus_ctrlreg_v__parameterized4 |     92(0.01%) |     92(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FSM                                                                                       |                                                                           Hypothesis_FSM |     33(0.01%) |     33(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     MINI_MERGER_APP_IN_SLR3                                                                     |                                                                                      app |   3710(0.11%) |   3710(0.11%) |   0(0.00%) |   0(0.00%) |   8843(0.13%) |  44(0.89%) |  3(0.03%) |  0(0.00%) |   0(0.00%) |
|       (MINI_MERGER_APP_IN_SLR3)                                                                 |                                                                                      app |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     63(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                              pipeline__parameterized1__1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       acc_error_2t_inst                                                                         |                                                                        acc_error_2t_1097 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_rx2t_inst                                                                            |                                                                          BCID_rx_2t_1098 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_0                                                                            |                                                           reg_array__parameterized2_1180 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_1                                                                            |                                                           reg_array__parameterized2_1181 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       data_out_mux                                                                              |                                                                    mux21__parameterized9 |     38(0.01%) |     38(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                        |                                                                              logger_1099 |    246(0.01%) |    246(0.01%) |   0(0.00%) |   0(0.00%) |    255(0.01%) |   9(0.18%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                    |                                                                              logger_1099 |     70(0.01%) |     70(0.01%) |   0(0.00%) |   0(0.00%) |    184(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         APU_RAM                                                                                 |                                                                   ipbus_ram_wrapper_1169 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (APU_RAM)                                                                             |                                                                   ipbus_ram_wrapper_1169 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1179 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                                |                                                                   ipbus_ram_wrapper_1170 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                            |                                                                   ipbus_ram_wrapper_1170 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1178 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ERROR_RAM                                                                               |                                                   ipbus_ram_wrapper__parameterized1_1171 |     47(0.01%) |     47(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (ERROR_RAM)                                                                           |                                                   ipbus_ram_wrapper__parameterized1_1171 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized4_1177 |     37(0.01%) |     37(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                            |                                                   ipbus_ram_wrapper__parameterized0_1172 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                        |                                                   ipbus_ram_wrapper__parameterized0_1172 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1176 |     39(0.01%) |     39(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[0].SRC_RAM                                                                  |                                                                   ipbus_ram_wrapper_1173 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[0].SRC_RAM)                                                              |                                                                   ipbus_ram_wrapper_1173 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1175 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         logger_registers                                                                        |                                                     ipbus_ctrlreg_v__parameterized2_1174 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                                 |                                                     ipbus_ctrlreg_v__parameterized1_1100 |   1052(0.03%) |   1052(0.03%) |   0(0.00%) |   0(0.00%) |   2050(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[0].input0_hf_rxtx                                                                 |                                                                        sync_hf_rxtx_1101 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                              dmux14__parameterized1_1158 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                               mux41__parameterized3_1159 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                           reg_array__parameterized1_1160 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                           reg_array__parameterized1_1161 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                           reg_array__parameterized1_1162 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                           reg_array__parameterized1_1163 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                               mux41__parameterized2_1164 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                           reg_array__parameterized0_1165 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                           reg_array__parameterized0_1166 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                           reg_array__parameterized0_1167 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                           reg_array__parameterized0_1168 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd1                                                                                  |                                                                            edge_reg_1103 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd2                                                                                  |                                                                            edge_reg_1104 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd3                                                                                  |                                                                            edge_reg_1105 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       err_fsm                                                                                   |                                                                           error_fsm_1106 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     27(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       hf_fsm                                                                                    |                                                                            head_foot_fsm |    104(0.01%) |    104(0.01%) |   0(0.00%) |   0(0.00%) |     69(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                                   |                                                                              pipeline__6 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    834(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                                          sync_mt_fifo_v2 |    193(0.01%) |    193(0.01%) |   0(0.00%) |   0(0.00%) |    441(0.01%) |   7(0.14%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                                          sync_mt_fifo_v2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    257(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                                       sync_fifo_cntrl_v2 |     48(0.01%) |     48(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                                       sync_fifo_cntrl_v2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                                           reg_array_1152 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                                           reg_array_1153 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                                  fifo_addr_count_v2_1154 |     14(0.01%) |     14(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                                            sync_rd_side_roll_detect_1155 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                                  fifo_addr_count_v2_1156 |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                                          perf_count_1157 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                                  sync_fifo_cntrl_v2_1134 |     56(0.01%) |     56(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                                  sync_fifo_cntrl_v2_1134 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                                           reg_array_1146 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                                           reg_array_1147 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                                  fifo_addr_count_v2_1148 |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                                            sync_rd_side_roll_detect_1149 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                                  fifo_addr_count_v2_1150 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                                          perf_count_1151 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                                  sync_fifo_cntrl_v2_1135 |     46(0.01%) |     46(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                                  sync_fifo_cntrl_v2_1135 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                                           reg_array_1140 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                                           reg_array_1141 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                                  fifo_addr_count_v2_1142 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                                            sync_rd_side_roll_detect_1143 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                                  fifo_addr_count_v2_1144 |     16(0.01%) |     16(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                                          perf_count_1145 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                                  sync_fifo_cntrl_v2_1136 |     43(0.01%) |     43(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                                  sync_fifo_cntrl_v2_1136 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                                                reg_array |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                                           reg_array_1137 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                                       fifo_addr_count_v2 |     16(0.01%) |     16(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                                                 sync_rd_side_roll_detect |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                                  fifo_addr_count_v2_1138 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                                          perf_count_1139 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                                               dp_bram_v2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   7(0.14%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|       output_nibbler                                                                            |                                                                  nibbler__parameterized1 |   1812(0.05%) |   1812(0.05%) |   0(0.00%) |   0(0.00%) |   4633(0.07%) |  28(0.57%) |  2(0.02%) |  0(0.00%) |   0(0.00%) |
|         (output_nibbler)                                                                        |                                                                  nibbler__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         FREE_FROM_SLR_output_pipeline                                                           |                                                                              pipeline__5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1602(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.TGEN_VERILOG                                                             |                                                                     tgen__parameterized3 |    324(0.01%) |    324(0.01%) |   0(0.00%) |   0(0.00%) |     57(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.timer_source                                                             |                                                        time_nibbler__parameterized0_1125 |    127(0.01%) |    127(0.01%) |   0(0.00%) |   0(0.00%) |    108(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           (SOURCE_OR_SINK.timer_source)                                                         |                                                        time_nibbler__parameterized0_1125 |    117(0.01%) |    117(0.01%) |   0(0.00%) |   0(0.00%) |     98(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           DESTINATION_TGEN.mem                                                                  |                                                          dp_ram_ipb__parameterized1_1131 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|             (DESTINATION_TGEN.mem)                                                              |                                                          dp_ram_ipb__parameterized1_1131 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             memory                                                                              |                                                dual_port_bram_infer__parameterized1_1132 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|             syncreg_w_inst                                                                      |                                                                           syncreg_w_1133 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mem                                                                                     |                                                          dp_ram_ipb__parameterized2_1126 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |  28(0.57%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           (mem)                                                                                 |                                                          dp_ram_ipb__parameterized2_1126 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized2_1129 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |  28(0.57%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                           syncreg_w_1130 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         perf_count_inst                                                                         |                                                          perf_count__parameterized1_1127 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.FREE_FROM_SLR_input_pipeline                                                        |                                                                              pipeline__4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    780(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.nibbler_registers                                                                   |                                                     ipbus_ctrlreg_v__parameterized1_1128 |   1347(0.04%) |   1347(0.04%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       pulse_we                                                                                  |                                                                           pulse_cdc_1108 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                              |                                                                           pulse_cdc_1108 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                           syncreg_w_1124 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       rd_done_cda                                                                               |                                                                 cooldown_arbiter_v2_1109 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sync_inst                                                                                 |                                                                         sync_fsm_v6_1110 |     16(0.01%) |     16(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd1                                                                                       |                                                                     watch_dog_timer_1111 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (wd1)                                                                                   |                                                                     watch_dog_timer_1111 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         pc1                                                                                     |                                                          perf_count__parameterized3_1123 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd2                                                                                       |                                                                  watch_dog_timer_2t_1112 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                     watch_dog_timer_1119 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                     watch_dog_timer_1119 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                          perf_count__parameterized3_1122 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                     watch_dog_timer_1120 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                     watch_dog_timer_1120 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                          perf_count__parameterized3_1121 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd3                                                                                       |                                                                  watch_dog_timer_2t_1113 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                     watch_dog_timer_1115 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                     watch_dog_timer_1115 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                          perf_count__parameterized3_1118 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                     watch_dog_timer_1116 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                     watch_dog_timer_1116 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                          perf_count__parameterized3_1117 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wr_done_cda                                                                               |                                                                 cooldown_arbiter_v2_1114 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     MINI_MERGER_APU_IN_SLR3                                                                     |                                                                      mini_merger_lib_apu |     34(0.01%) |     34(0.01%) |   0(0.00%) |   0(0.00%) |    132(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (MINI_MERGER_APU_IN_SLR3)                                                                 |                                                                      mini_merger_lib_apu |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       SIM.apu_registers                                                                         |                                                        ipbus_ctrlreg_v__parameterized3_9 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     MINI_TOWERSUM_APP_IN_SLR3                                                                   |                                                                      app__parameterized0 |   3272(0.10%) |   3272(0.10%) |   0(0.00%) |   0(0.00%) |   7965(0.12%) |  13(0.26%) |  1(0.01%) |  8(0.31%) |   0(0.00%) |
|       (MINI_TOWERSUM_APP_IN_SLR3)                                                               |                                                                      app__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     63(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                              pipeline__parameterized1__2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       acc_error_2t_inst                                                                         |                                                                        acc_error_2t_1007 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_rx2t_inst                                                                            |                                                                          BCID_rx_2t_1008 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_0                                                                            |                                                           reg_array__parameterized2_1095 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_1                                                                            |                                                           reg_array__parameterized2_1096 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       data_out_mux                                                                              |                                                               mux21__parameterized6_1009 |     60(0.01%) |     60(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                        |                                                                              logger_1010 |    244(0.01%) |    244(0.01%) |   0(0.00%) |   0(0.00%) |    255(0.01%) |   9(0.18%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                    |                                                                              logger_1010 |     69(0.01%) |     69(0.01%) |   0(0.00%) |   0(0.00%) |    184(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         APU_RAM                                                                                 |                                                                   ipbus_ram_wrapper_1084 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (APU_RAM)                                                                             |                                                                   ipbus_ram_wrapper_1084 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1094 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                                |                                                                   ipbus_ram_wrapper_1085 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                            |                                                                   ipbus_ram_wrapper_1085 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1093 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ERROR_RAM                                                                               |                                                   ipbus_ram_wrapper__parameterized1_1086 |     47(0.01%) |     47(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (ERROR_RAM)                                                                           |                                                   ipbus_ram_wrapper__parameterized1_1086 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized4_1092 |     37(0.01%) |     37(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                            |                                                   ipbus_ram_wrapper__parameterized0_1087 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                        |                                                   ipbus_ram_wrapper__parameterized0_1087 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1091 |     39(0.01%) |     39(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[0].SRC_RAM                                                                  |                                                                   ipbus_ram_wrapper_1088 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[0].SRC_RAM)                                                              |                                                                   ipbus_ram_wrapper_1088 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1090 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         logger_registers                                                                        |                                                     ipbus_ctrlreg_v__parameterized2_1089 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                                 |                                                     ipbus_ctrlreg_v__parameterized1_1011 |   1231(0.04%) |   1231(0.04%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[0].input0_hf_rxtx                                                                 |                                                                        sync_hf_rxtx_1012 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                              dmux14__parameterized1_1073 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                               mux41__parameterized3_1074 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                           reg_array__parameterized1_1075 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                           reg_array__parameterized1_1076 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                           reg_array__parameterized1_1077 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                           reg_array__parameterized1_1078 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                               mux41__parameterized2_1079 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                           reg_array__parameterized0_1080 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                           reg_array__parameterized0_1081 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                           reg_array__parameterized0_1082 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                           reg_array__parameterized0_1083 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd1                                                                                  |                                                                            edge_reg_1014 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd2                                                                                  |                                                                            edge_reg_1015 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd3                                                                                  |                                                                            edge_reg_1016 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       err_fsm                                                                                   |                                                                           error_fsm_1017 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     27(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       hf_fsm                                                                                    |                                                            head_foot_fsm__parameterized1 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |     69(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                                   |                                                                              pipeline__9 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1602(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                     sync_mt_fifo_v2__parameterized1_1018 |    211(0.01%) |    211(0.01%) |   0(0.00%) |   0(0.00%) |    717(0.01%) |   0(0.00%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                     sync_mt_fifo_v2__parameterized1_1018 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    513(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                  sync_fifo_cntrl_v2__parameterized0_1044 |     49(0.01%) |     49(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                  sync_fifo_cntrl_v2__parameterized0_1044 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                           reg_array__parameterized3_1067 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                           reg_array__parameterized3_1068 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                  fifo_addr_count_v2__parameterized0_1069 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                            sync_rd_side_roll_detect__parameterized0_1070 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                  fifo_addr_count_v2__parameterized0_1071 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                          perf_count__parameterized1_1072 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                  sync_fifo_cntrl_v2__parameterized0_1045 |     49(0.01%) |     49(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                  sync_fifo_cntrl_v2__parameterized0_1045 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                           reg_array__parameterized3_1061 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                           reg_array__parameterized3_1062 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                  fifo_addr_count_v2__parameterized0_1063 |     24(0.01%) |     24(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                            sync_rd_side_roll_detect__parameterized0_1064 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                  fifo_addr_count_v2__parameterized0_1065 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                          perf_count__parameterized1_1066 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                  sync_fifo_cntrl_v2__parameterized0_1046 |     66(0.01%) |     66(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                  sync_fifo_cntrl_v2__parameterized0_1046 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                           reg_array__parameterized3_1055 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                           reg_array__parameterized3_1056 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                  fifo_addr_count_v2__parameterized0_1057 |     33(0.01%) |     33(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                            sync_rd_side_roll_detect__parameterized0_1058 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                  fifo_addr_count_v2__parameterized0_1059 |     20(0.01%) |     20(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                          perf_count__parameterized1_1060 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                  sync_fifo_cntrl_v2__parameterized0_1047 |     47(0.01%) |     47(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                  sync_fifo_cntrl_v2__parameterized0_1047 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                           reg_array__parameterized3_1049 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                           reg_array__parameterized3_1050 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                  fifo_addr_count_v2__parameterized0_1051 |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                            sync_rd_side_roll_detect__parameterized0_1052 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                  fifo_addr_count_v2__parameterized0_1053 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                          perf_count__parameterized1_1054 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                          dp_bram_v2__parameterized0_1048 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|       output_nibbler                                                                            |                                                                  nibbler__parameterized2 |   1251(0.04%) |   1251(0.04%) |   0(0.00%) |   0(0.00%) |   2713(0.04%) |   4(0.08%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|         (output_nibbler)                                                                        |                                                                  nibbler__parameterized2 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         FREE_FROM_SLR_output_pipeline                                                           |                                                                              pipeline__8 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.TGEN_VERILOG                                                             |                                                                     tgen__parameterized5 |     89(0.01%) |     89(0.01%) |   0(0.00%) |   0(0.00%) |     57(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.timer_source                                                             |                                                        time_nibbler__parameterized0_1037 |    119(0.01%) |    119(0.01%) |   0(0.00%) |   0(0.00%) |    108(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           (SOURCE_OR_SINK.timer_source)                                                         |                                                        time_nibbler__parameterized0_1037 |    109(0.01%) |    109(0.01%) |   0(0.00%) |   0(0.00%) |     98(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           DESTINATION_TGEN.mem                                                                  |                                                          dp_ram_ipb__parameterized1_1041 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|             (DESTINATION_TGEN.mem)                                                              |                                                          dp_ram_ipb__parameterized1_1041 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             memory                                                                              |                                                dual_port_bram_infer__parameterized1_1042 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|             syncreg_w_inst                                                                      |                                                                           syncreg_w_1043 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mem                                                                                     |                                                               dp_ram_ipb__parameterized3 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (mem)                                                                                 |                                                               dp_ram_ipb__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                     dual_port_bram_infer__parameterized5 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                           syncreg_w_1040 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         perf_count_inst                                                                         |                                                          perf_count__parameterized1_1038 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.FREE_FROM_SLR_input_pipeline                                                        |                                                                              pipeline__7 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    204(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.nibbler_registers                                                                   |                                                     ipbus_ctrlreg_v__parameterized1_1039 |   1028(0.03%) |   1028(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       pulse_we                                                                                  |                                                                           pulse_cdc_1020 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                              |                                                                           pulse_cdc_1020 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                           syncreg_w_1036 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       rd_done_cda                                                                               |                                                                 cooldown_arbiter_v2_1021 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sync_inst                                                                                 |                                                                         sync_fsm_v6_1022 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd1                                                                                       |                                                                     watch_dog_timer_1023 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (wd1)                                                                                   |                                                                     watch_dog_timer_1023 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         pc1                                                                                     |                                                          perf_count__parameterized3_1035 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd2                                                                                       |                                                                  watch_dog_timer_2t_1024 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                     watch_dog_timer_1031 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                     watch_dog_timer_1031 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                          perf_count__parameterized3_1034 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                     watch_dog_timer_1032 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                     watch_dog_timer_1032 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                          perf_count__parameterized3_1033 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd3                                                                                       |                                                                  watch_dog_timer_2t_1025 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                     watch_dog_timer_1027 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                     watch_dog_timer_1027 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                          perf_count__parameterized3_1030 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                     watch_dog_timer_1028 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                     watch_dog_timer_1028 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                          perf_count__parameterized3_1029 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wr_done_cda                                                                               |                                                                 cooldown_arbiter_v2_1026 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     MINI_TOWERSUM_APU_IN_SLR3                                                                   |                                                                    mini_towersum_lib_apu |     34(0.01%) |     34(0.01%) |   0(0.00%) |   0(0.00%) |    132(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (MINI_TOWERSUM_APU_IN_SLR3)                                                               |                                                                    mini_towersum_lib_apu |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       SIM.apu_registers                                                                         |                                                        ipbus_ctrlreg_v__parameterized3_8 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     TAU1_APP_IN_SLR3                                                                            |                                                                      app__parameterized1 |   3253(0.10%) |   3221(0.10%) |  32(0.01%) |   0(0.00%) |   7965(0.12%) |  11(0.22%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|       (TAU1_APP_IN_SLR3)                                                                        |                                                                      app__parameterized1 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     63(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       FREE_FROM_SLR_output_pipeline                                                             |                                                              pipeline__parameterized1__3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       acc_error_2t_inst                                                                         |                                                                         acc_error_2t_915 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       bcid_rx2t_inst                                                                            |                                                                           BCID_rx_2t_916 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     24(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_0                                                                            |                                                           reg_array__parameterized2_1005 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         EvTID_BCID_1                                                                            |                                                           reg_array__parameterized2_1006 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       data_out_mux                                                                              |                                                                mux21__parameterized6_917 |     38(0.01%) |     38(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.LOGGER                                                                        |                                                                               logger_918 |    246(0.01%) |    246(0.01%) |   0(0.00%) |   0(0.00%) |    255(0.01%) |   9(0.18%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (debug_ipbus.LOGGER)                                                                    |                                                                               logger_918 |     70(0.01%) |     70(0.01%) |   0(0.00%) |   0(0.00%) |    184(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         APU_RAM                                                                                 |                                                                    ipbus_ram_wrapper_994 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (APU_RAM)                                                                             |                                                                    ipbus_ram_wrapper_994 |      8(0.01%) |      8(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1004 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         BCID_RAM                                                                                |                                                                    ipbus_ram_wrapper_995 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (BCID_RAM)                                                                            |                                                                    ipbus_ram_wrapper_995 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1003 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ERROR_RAM                                                                               |                                                    ipbus_ram_wrapper__parameterized1_996 |     47(0.01%) |     47(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (ERROR_RAM)                                                                           |                                                    ipbus_ram_wrapper__parameterized1_996 |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized4_1002 |     37(0.01%) |     37(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   1(0.02%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         OVERFLOW_RAM                                                                            |                                                    ipbus_ram_wrapper__parameterized0_997 |     40(0.01%) |     40(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (OVERFLOW_RAM)                                                                        |                                                    ipbus_ram_wrapper__parameterized0_997 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      3(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1001 |     39(0.01%) |     39(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCES_LOG[0].SRC_RAM                                                                  |                                                                    ipbus_ram_wrapper_998 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCES_LOG[0].SRC_RAM)                                                              |                                                                    ipbus_ram_wrapper_998 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                dual_port_bram_infer__parameterized3_1000 |     22(0.01%) |     22(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         logger_registers                                                                        |                                                      ipbus_ctrlreg_v__parameterized2_999 |     31(0.01%) |     31(0.01%) |   0(0.00%) |   0(0.00%) |     32(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       debug_ipbus.app_registers                                                                 |                                                      ipbus_ctrlreg_v__parameterized1_919 |   1228(0.04%) |   1228(0.04%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edr_for[0].input0_hf_rxtx                                                                 |                                                                         sync_hf_rxtx_920 |    111(0.01%) |    111(0.01%) |   0(0.00%) |   0(0.00%) |    312(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         dmux_hf_in                                                                              |                                                               dmux14__parameterized1_983 |     28(0.01%) |     28(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_out_mux                                                                            |                                                                mux41__parameterized3_984 |     65(0.01%) |     65(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg0                                                                               |                                                            reg_array__parameterized1_985 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg1                                                                               |                                                            reg_array__parameterized1_986 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg2                                                                               |                                                            reg_array__parameterized1_987 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         foot_reg3                                                                               |                                                            reg_array__parameterized1_988 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     65(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_out_mux                                                                            |                                                                mux41__parameterized2_989 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg0                                                                               |                                                            reg_array__parameterized0_990 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg1                                                                               |                                                            reg_array__parameterized0_991 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg2                                                                               |                                                            reg_array__parameterized0_992 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         head_reg3                                                                               |                                                            reg_array__parameterized0_993 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     13(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd1                                                                                  |                                                                             edge_reg_922 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd2                                                                                  |                                                                             edge_reg_923 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       edrg_wd3                                                                                  |                                                                             edge_reg_924 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       err_fsm                                                                                   |                                                                            error_fsm_925 |     30(0.01%) |     30(0.01%) |   0(0.00%) |   0(0.00%) |     27(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       hf_fsm                                                                                    |                                                            head_foot_fsm__parameterized3 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |     69(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].FREE_FROM_SLR_input_pipeline                                                   |                                                                             pipeline__12 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |   1602(0.02%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2                                           |                                                      sync_mt_fifo_v2__parameterized1_926 |    219(0.01%) |    219(0.01%) |   0(0.00%) |   0(0.00%) |    717(0.01%) |   0(0.00%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|         (mainfor[0].mode_if.sync_mem_if.SYNCH_MT_FIFO_V2)                                       |                                                      sync_mt_fifo_v2__parameterized1_926 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    513(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_0                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_954 |     49(0.01%) |     49(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_0)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_954 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_977 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_978 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_979 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_980 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_981 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_982 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_1                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_955 |     50(0.01%) |     50(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_1)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_955 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_971 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_972 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_973 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_974 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_975 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_976 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_2                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_956 |     70(0.01%) |     70(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_2)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_956 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_965 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_966 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_967 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_968 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_969 |     21(0.01%) |     21(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_970 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         fifo_tid_cntrl_3                                                                        |                                                   sync_fifo_cntrl_v2__parameterized0_957 |     50(0.01%) |     50(0.01%) |   0(0.00%) |   0(0.00%) |     51(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (fifo_tid_cntrl_3)                                                                    |                                                   sync_fifo_cntrl_v2__parameterized0_957 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_rd_pointer_latch                                                                   |                                                            reg_array__parameterized3_959 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           db_wr_pointer_latch                                                                   |                                                            reg_array__parameterized3_960 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_961 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           rd_roll_detect                                                                        |                                             sync_rd_side_roll_detect__parameterized0_962 |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_addr_count                                                                         |                                                   fifo_addr_count_v2__parameterized0_963 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           wr_depth_counter                                                                      |                                                           perf_count__parameterized1_964 |     13(0.01%) |     13(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mt_dp_bram                                                                              |                                                           dp_bram_v2__parameterized0_958 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  8(0.31%) |   0(0.00%) |
|       output_nibbler                                                                            |                                                                  nibbler__parameterized3 |   1244(0.04%) |   1212(0.04%) |  32(0.01%) |   0(0.00%) |   2713(0.04%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (output_nibbler)                                                                        |                                                                  nibbler__parameterized3 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         FREE_FROM_SLR_output_pipeline                                                           |                                                                             pipeline__11 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    258(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.TGEN_VERILOG                                                             |                                                                     tgen__parameterized7 |     92(0.01%) |     92(0.01%) |   0(0.00%) |   0(0.00%) |     53(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SOURCE_OR_SINK.timer_source                                                             |                                                         time_nibbler__parameterized1_945 |    151(0.01%) |    119(0.01%) |  32(0.01%) |   0(0.00%) |    116(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (SOURCE_OR_SINK.timer_source)                                                         |                                                         time_nibbler__parameterized1_945 |     97(0.01%) |     97(0.01%) |   0(0.00%) |   0(0.00%) |     90(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           DESTINATION_TGEN.mem                                                                  |                                                           dp_ram_ipb__parameterized4_951 |     54(0.01%) |     22(0.01%) |  32(0.01%) |   0(0.00%) |     26(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (DESTINATION_TGEN.mem)                                                              |                                                           dp_ram_ipb__parameterized4_951 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             memory                                                                              |                                                 dual_port_bram_infer__parameterized6_952 |     51(0.01%) |     19(0.01%) |  32(0.01%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             syncreg_w_inst                                                                      |                                                                            syncreg_w_953 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         mem                                                                                     |                                                           dp_ram_ipb__parameterized5_946 |      7(0.01%) |      7(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (mem)                                                                                 |                                                           dp_ram_ipb__parameterized5_946 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                 dual_port_bram_infer__parameterized7_949 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   2(0.04%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                            syncreg_w_950 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         perf_count_inst                                                                         |                                                           perf_count__parameterized7_947 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.FREE_FROM_SLR_input_pipeline                                                        |                                                                             pipeline__10 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    204(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         sim.nibbler_registers                                                                   |                                                      ipbus_ctrlreg_v__parameterized1_948 |    991(0.03%) |    991(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       pulse_we                                                                                  |                                                                            pulse_cdc_928 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (pulse_we)                                                                              |                                                                            pulse_cdc_928 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                            syncreg_w_944 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       rd_done_cda                                                                               |                                                                  cooldown_arbiter_v2_929 |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sync_inst                                                                                 |                                                                          sync_fsm_v6_930 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd1                                                                                       |                                                                      watch_dog_timer_931 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (wd1)                                                                                   |                                                                      watch_dog_timer_931 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         pc1                                                                                     |                                                           perf_count__parameterized3_943 |     25(0.01%) |     25(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd2                                                                                       |                                                                   watch_dog_timer_2t_932 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_939 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_939 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_942 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_940 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_940 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_941 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wd3                                                                                       |                                                                   watch_dog_timer_2t_933 |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |     36(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2ta                                                                                   |                                                                      watch_dog_timer_935 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2ta)                                                                               |                                                                      watch_dog_timer_935 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_938 |     17(0.01%) |     17(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         wd2tb                                                                                   |                                                                      watch_dog_timer_936 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     18(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           (wd2tb)                                                                               |                                                                      watch_dog_timer_936 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           pc1                                                                                   |                                                           perf_count__parameterized3_937 |     18(0.01%) |     18(0.01%) |   0(0.00%) |   0(0.00%) |     16(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       wr_done_cda                                                                               |                                                                  cooldown_arbiter_v2_934 |      9(0.01%) |      9(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     TAU1_APU_IN_SLR3                                                                            |                                                                             tau1_lib_apu |    176(0.01%) |    176(0.01%) |   0(0.00%) |   0(0.00%) |    421(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (TAU1_APU_IN_SLR3)                                                                        |                                                                             tau1_lib_apu |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      5(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       AGG                                                                                       |                                                                               aggregator |     15(0.01%) |     15(0.01%) |   0(0.00%) |   0(0.00%) |     43(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       CTRL_DELAY_SR                                                                             |                                                                           shift_register |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      8(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       HLS_WRAPPER                                                                               |                                                                              hls_wrapper |    124(0.01%) |    124(0.01%) |   0(0.00%) |   0(0.00%) |     77(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         GEN_PREPROCESSOR.PREPROCESSOR                                                           |                                                                           AdderTree_Tau1 |    112(0.01%) |    112(0.01%) |   0(0.00%) |   0(0.00%) |     60(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           DelayWC_sum_2_sum_2_d                                                                 |                                                                           DelayWithCarry |     33(0.01%) |     33(0.01%) |   0(0.00%) |   0(0.00%) |     12(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           sum_0                                                                                 |                                                                      MultiAdderWithCarry |     79(0.01%) |     79(0.01%) |   0(0.00%) |   0(0.00%) |     42(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             stage_gen[0].adder_gen[0].ADD                                                       |                                                                                  Adder_1 |     64(0.01%) |     64(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             stage_gen[1].adder_gen[0].ADD                                                       |                                                                                  Adder_2 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             stage_gen[1].adder_gen[1].ADD                                                       |                                                                                  Adder_3 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             stage_gen[2].adder_gen[0].ADD                                                       |                                                                                  Adder_4 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             stage_gen[2].adder_gen[1].ADD                                                       |                                                                                  Adder_5 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             stage_gen[2].adder_gen[2].ADD                                                       |                                                                                  Adder_6 |      5(0.01%) |      5(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             stage_gen[2].adder_gen[3].ADD                                                       |                                                                                  Adder_7 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           sum_2                                                                                 |                                                      MultiAdderWithCarry__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             stage_gen[0].adder_gen[0].ADD                                                       |                                                                                    Adder |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         HLS_BLOCK                                                                               |                                                                                     Tau1 |     12(0.01%) |     12(0.01%) |   0(0.00%) |   0(0.00%) |     17(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       META_DELAY_SR                                                                             |                                                           shift_register__parameterized0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    160(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       apu_registers                                                                             |                                                          ipbus_ctrlreg_v__parameterized3 |     32(0.01%) |     32(0.01%) |   0(0.00%) |   0(0.00%) |    128(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     fabric_IN_SLR0                                                                              |                                                                         ipbus_fabric_sel |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     sink_nibbler_IN_SLR0                                                                        |                                                                  nibbler__parameterized9 |    906(0.03%) |    906(0.03%) |   0(0.00%) |   0(0.00%) |   2516(0.04%) |   4(0.08%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|       (sink_nibbler_IN_SLR0)                                                                    |                                                                  nibbler__parameterized9 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       SOURCE_OR_SINK.timer_sink                                                                 |                                                             time_nibbler__parameterized4 |     50(0.01%) |     50(0.01%) |   0(0.00%) |   0(0.00%) |     56(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|         (SOURCE_OR_SINK.timer_sink)                                                             |                                                             time_nibbler__parameterized4 |     47(0.01%) |     47(0.01%) |   0(0.00%) |   0(0.00%) |     46(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         DESTINATION_TGEN.CASE1_SIM.sink_ram                                                     |                                                               dp_ram_ipb__parameterized8 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           (DESTINATION_TGEN.CASE1_SIM.sink_ram)                                                 |                                                               dp_ram_ipb__parameterized8 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           memory                                                                                |                                                    dual_port_bram_infer__parameterized10 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  1(0.01%) |  0(0.00%) |   0(0.00%) |
|           syncreg_w_inst                                                                        |                                                                              syncreg_w_0 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       mem                                                                                       |                                                               dp_ram_ipb__parameterized9 |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |     10(0.01%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (mem)                                                                                   |                                                               dp_ram_ipb__parameterized9 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         memory                                                                                  |                                                    dual_port_bram_infer__parameterized11 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   4(0.08%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         syncreg_w_inst                                                                          |                                                                                syncreg_w |      3(0.01%) |      3(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       perf_count_inst                                                                           |                                                               perf_count__parameterized9 |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sim.FREE_FROM_SLR_input_pipeline                                                          |                                                                             pipeline__31 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |    396(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sim.nibbler_registers                                                                     |                                                          ipbus_ctrlreg_v__parameterized1 |    849(0.03%) |    849(0.03%) |   0(0.00%) |   0(0.00%) |   2048(0.03%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|   axi_dbg_hub                                                                                   |                                                                axi_dbg_hub_axi_dbg_hub_0 |    636(0.02%) |    636(0.02%) |   0(0.00%) |   0(0.00%) |    951(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     (axi_dbg_hub)                                                                               |                                                                axi_dbg_hub_axi_dbg_hub_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     inst                                                                                        |                                                    axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub |    636(0.02%) |    636(0.02%) |   0(0.00%) |   0(0.00%) |    951(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       sv_top_inst                                                                               |                                      axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_sv_top |    636(0.02%) |    636(0.02%) |   0(0.00%) |   0(0.00%) |    951(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         core_inst                                                                               |                                        axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_core |    636(0.02%) |    636(0.02%) |   0(0.00%) |   0(0.00%) |    951(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           dbg_core_intf_inst                                                                    |                                   axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_core_intf |    184(0.01%) |    184(0.01%) |   0(0.00%) |   0(0.00%) |    268(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             (dbg_core_intf_inst)                                                                |                                   axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_core_intf |     35(0.01%) |     35(0.01%) |   0(0.00%) |   0(0.00%) |    169(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             dbg_core_axis_intf0_inst                                                            |                               axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_stream_engine |     64(0.01%) |     64(0.01%) |   0(0.00%) |   0(0.00%) |     50(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               dbg_core_rx_stream_inst                                                           |                                   axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_rx_engine |     11(0.01%) |     11(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               dbg_core_tx_stream_inst                                                           |                                   axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_tx_engine |     53(0.01%) |     53(0.01%) |   0(0.00%) |   0(0.00%) |     43(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             dbg_core_axis_intf1_inst                                                            |               axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_stream_engine__parameterized0 |     61(0.01%) |     61(0.01%) |   0(0.00%) |   0(0.00%) |     45(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               dbg_core_rx_stream_inst                                                           |                   axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_rx_engine__parameterized0 |     15(0.01%) |     15(0.01%) |   0(0.00%) |   0(0.00%) |      7(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|               dbg_core_tx_stream_inst                                                           |                   axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_tx_engine__parameterized0 |     46(0.01%) |     46(0.01%) |   0(0.00%) |   0(0.00%) |     38(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             dbg_core_rx_ch_sel_inst                                                             |                                      axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_ch_sel |     23(0.01%) |     23(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|             dbg_core_tx_ch_sel_inst                                                             |                                    axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_ch_sel_0 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      2(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|           dbg_core_reg_intf_inst                                                                |                                    axi_dbg_hub_axi_dbg_hub_0_axi_dbg_hub_v2_0_8_reg_intf |    454(0.01%) |    454(0.01%) |   0(0.00%) |   0(0.00%) |    683(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|   axi_noc                                                                                       |                                                                 design_axi_noc_axi_noc_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     inst                                                                                        |                                                         design_axi_noc_axi_noc_0_bd_1091 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (inst)                                                                                    |                                                         design_axi_noc_axi_noc_0_bd_1091 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       M00_AXI_nsu                                                                               |                                           design_axi_noc_axi_noc_0_bd_1091_M00_AXI_nsu_0 |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         bd_1091_M00_AXI_nsu_0_top_INST                                                          |                                       design_axi_noc_axi_noc_0_bd_1091_M00_AXI_nsu_0_top |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      0(0.00%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|   proc_sys_reset                                                                                |                                                          proc_sys_reset_proc_sys_reset_0 |     15(0.01%) |     14(0.01%) |   0(0.00%) |   1(0.01%) |     35(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|     U0                                                                                          |                                           proc_sys_reset_proc_sys_reset_0_proc_sys_reset |     15(0.01%) |     14(0.01%) |   0(0.00%) |   1(0.01%) |     35(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       (U0)                                                                                      |                                           proc_sys_reset_proc_sys_reset_0_proc_sys_reset |      0(0.00%) |      0(0.00%) |   0(0.00%) |   0(0.00%) |      1(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       EXT_LPF                                                                                   |                                                      proc_sys_reset_proc_sys_reset_0_lpf |      5(0.01%) |      4(0.01%) |   0(0.00%) |   1(0.01%) |     19(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (EXT_LPF)                                                                               |                                                      proc_sys_reset_proc_sys_reset_0_lpf |      2(0.01%) |      1(0.01%) |   0(0.00%) |   1(0.01%) |     11(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ACTIVE_LOW_AUX.ACT_LO_AUX                                                               |                                                 proc_sys_reset_proc_sys_reset_0_cdc_sync |      1(0.01%) |      1(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         ACTIVE_LOW_EXT.ACT_LO_EXT                                                               |                                               proc_sys_reset_proc_sys_reset_0_cdc_sync_0 |      2(0.01%) |      2(0.01%) |   0(0.00%) |   0(0.00%) |      4(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|       SEQ                                                                                       |                                             proc_sys_reset_proc_sys_reset_0_sequence_psr |     10(0.01%) |     10(0.01%) |   0(0.00%) |   0(0.00%) |     15(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         (SEQ)                                                                                   |                                             proc_sys_reset_proc_sys_reset_0_sequence_psr |      6(0.01%) |      6(0.01%) |   0(0.00%) |   0(0.00%) |      9(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
|         SEQ_COUNTER                                                                             |                                                  proc_sys_reset_proc_sys_reset_0_upcnt_n |      4(0.01%) |      4(0.01%) |   0(0.00%) |   0(0.00%) |      6(0.01%) |   0(0.00%) |  0(0.00%) |  0(0.00%) |   0(0.00%) |
+-------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------+---------------+------------+------------+---------------+------------+-----------+-----------+------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining


