Declarations

Ports:

wire        clk160;
wire        clk40;
wire        rstb;
wire        lcb_i;
wire        l0a_o;
wire [6:0]  l0a_tag_o;
wire        bcr_o;
wire [3:0]  abcid_i;
wire [7:0]  rb_addr_o;
wire        rb_busy_i;
wire        rb_init_o;
wire        rb_load_o;
wire        rb_rnw_o;
wire        rb_sdat_o;
wire        rb_shen_o;
wire [3:0]  fast_cmd_o;

Diagram Signals:

wire        HI;
wire        LO;
wire        ser_ddr0; // -- ddr0 serial input
wire        ser_ddr1; // -- ddr1 serial input
wire [4:0]  ZERO5;

Pre User:

Post User:

Compiler Directives

Pre-module directives:

`resetall
`timescale 1ns/1ps

Post-module directives:

End-module directives:

Bundles