//
// Module downlink.lcb_abc_top.struct
//
// Created:
//          by - cvmfs.users (pc201.hep.ucl.ac.uk)
//          at - 10:47:25 12/21/16
//
// Generated by Mentor Graphics' HDL Designer(TM) 2015.2 (Build 5)
//

`resetall
`timescale 1ns/1ps
module lcb_abc_top(
   // Port Declarations
   input   wire    [3:0]  abcid_i,
   input   wire           clk160,
   input   wire           clk40,
   input   wire           lcb_i,
   input   wire           rb_busy_i,
   input   wire           rstb,
   output  wire           bcr_o,
   output  wire    [3:0]  fast_cmd_o,
   output  wire           l0a_o,
   output  wire    [6:0]  l0a_tag_o,
   output  wire    [7:0]  rb_addr_o,
   output  wire           rb_init_o,
   output  wire           rb_load_o,
   output  wire           rb_rnw_o,
   output  wire           rb_sdat_o,
   output  wire           rb_shen_o
);


// Internal Declarations


// Local declarations

// Internal signal declarations
wire        HI;
wire        LO;
wire  [4:0] ZERO5;
wire        ser_ddr0;   // -- ddr0 serial input
wire        ser_ddr1;   // -- ddr1 serial input


// Instances 
lcb_core #(1) Ulcbcore(
   .abcid_i    (abcid_i),
   .clk160     (clk160),
   .clk40      (clk40),
   .hccid_i    (ZERO5),
   .rb_busy_i  (rb_busy_i),
   .rstb       (rstb),
   .ser_ddr0_i (ser_ddr0),
   .ser_ddr1_i (ser_ddr1),
   .bcr_o      (bcr_o),
   .fast_cmd_o (fast_cmd_o),
   .l0a_o      (l0a_o),
   .l0a_tag_o  (l0a_tag_o),
   .par4_o     (),
   .rb_addr_o  (rb_addr_o),
   .rb_init_o  (rb_init_o),
   .rb_load_o  (rb_load_o),
   .rb_rnw_o   (rb_rnw_o),
   .rb_sdat_o  (rb_sdat_o),
   .rb_shen_o  (rb_shen_o)
);

lcb_ddr_dec Uiddr(
   .ddr_i (lcb_i),
   .d0_o  (ser_ddr0),
   .d1_o  (ser_ddr1),
   .clk   (clk160)
);

// HDL Embedded Text Block 2 eb2
assign LO = 1'b0;
assign HI = 1'b1;
assign ZERO5= 5'b0;

endmodule // lcb_abc_top