Declarations

Ports:

wire         clk160;
wire         clk40;
wire [3:0]   fast_cmd_o;
wire         ser_ddr0_i; // -- ddr0 serial input
wire         rstb;
wire         rb_busy_i;
wire [3:0]   abcid_i;
wire [3:0]   par4_o;
wire [7:0]   rb_addr_o;
wire [6:0]   l0a_tag_o;
wire         rb_sdat_o;
wire         rb_load_o;
wire         bcr_o;
wire         rb_rnw_o;
wire         l0a_o;
wire         rb_init_o;
wire         rb_shen_o;
wire [4:0]   hccid_i;
wire         ser_ddr1_i; // -- ddr1 serial input

Diagram Signals:

wire         cfifo_re;
wire [8:0]   cbus_all;
wire         cfifo_empty;
wire         a_frame_locked;
wire         cbus_valid;
wire [7:0]   a_dbg_symbol;
wire         rst;
// --    cmd_ignore_o : out std_logic;
wire cbus_sof;
wire [3:0]   a_par4;
wire         parity_err;
wire [8:0]   cfifo_all;
wire         a_decoder_err;
wire         cbus_eof;
wire         a_nibble_err;
wire [6:0]   cbus_data;
wire [1:0]   a_frame_sync;
wire [15:0]  a_dbg_frame;

Pre User:

Post User:

Compiler Directives

Pre-module directives:

`resetall
`timescale 1ns/1ps

Post-module directives:

End-module directives:

Bundles