//
// Module downlink.lcb_core.struct
//
// Created:
//          by - cvmfs.users (pc201.hep.ucl.ac.uk)
//          at - 10:59:05 12/21/16
//
// Generated by Mentor Graphics' HDL Designer(TM) 2015.2 (Build 5)
//

`resetall
`timescale 1ns/1ps
module lcb_core(
   // Port Declarations
   input   wire    [3:0]  abcid_i,
   input   wire           clk160,
   input   wire           clk40,
   input   wire    [4:0]  hccid_i,
   input   wire           rb_busy_i,
   input   wire           rstb,
   input   wire           ser_ddr0_i,
   input   wire           ser_ddr1_i,
   output  wire           bcr_o,
   output  wire    [3:0]  fast_cmd_o,
   output  wire           l0a_o,
   output  wire    [6:0]  l0a_tag_o,
   output  wire    [3:0]  par4_o,
   output  wire    [7:0]  rb_addr_o,
   output  wire           rb_init_o,
   output  wire           rb_load_o,
   output  wire           rb_rnw_o,
   output  wire           rb_sdat_o,
   output  wire           rb_shen_o
);


// synopsys template
parameter ASIC_IS_ABC = 1;

// Internal Declarations


// Local declarations

// Internal signal declarations
wire  [15:0] a_dbg_frame;
wire  [7:0]  a_dbg_symbol;
wire         a_decoder_err;
wire         a_frame_locked;
wire  [1:0]  a_frame_sync;
wire         a_nibble_err;
wire  [3:0]  a_par4;
wire  [8:0]  cbus_all;
wire  [6:0]  cbus_data;
wire         cbus_eof;
// --    cmd_ignore_o : out std_logic;
wire         cbus_sof;
wire         cbus_valid;
wire  [8:0]  cfifo_all;
wire         cfifo_empty;
wire         cfifo_re;
wire         parity_err;
wire         rst;


// Instances 
lcb_decoder #(ASIC_IS_ABC) Udecoder(
   .hccid_i       (hccid_i),
   .par4_i        (a_par4),
   .locked_i      (a_frame_locked),
   .frame_sync_i  (a_frame_sync),
   .decoder_err_o (a_decoder_err),
   .par4_o        (par4_o),
   .l0a_o         (l0a_o),
   .l0a_tag_o     (l0a_tag_o),
   .bcr_o         (bcr_o),
   .cbus_data_o   (cbus_data),
   .cbus_valid_o  (cbus_valid),
   .cbus_sof_o    (cbus_sof),
   .cbus_eof_o    (cbus_eof),
   .cbus_all_o    (cbus_all),
   .fast_cmd_o    (fast_cmd_o),
   .clk40         (clk40),
   .rst           (rst)
);

lcb_frame_sync Uframesync(
   .clk160        (clk160),
   .ser_ddr0_i    (ser_ddr0_i),
   .ser_ddr1_i    (ser_ddr1_i),
   .par4_o        (a_par4),
   .frame_sync_o  (a_frame_sync),
   .dbg_frame_o   (a_dbg_frame),
   .dbg_symbol_o  (a_dbg_symbol),
   .nibble_err_o  (a_nibble_err),
   .parity_err_o  (parity_err),
   .locked_o      (a_frame_locked),
   .decoder_err_i (a_decoder_err),
   .clk40         (clk40),
   .rst           (rst)
);

lcb_regblock_if Uregblkif(
   .abcid_i       (abcid_i),
   .rb_addr_o     (rb_addr_o),
   .rb_rnw_o      (rb_rnw_o),
   .rb_init_o     (rb_init_o),
   .rb_load_o     (rb_load_o),
   .rb_sdat_o     (rb_sdat_o),
   .rb_shen_o     (rb_shen_o),
   .rb_busy_i     (rb_busy_i),
   .cfifo_all_i   (cfifo_all),
   .cfifo_empty_i (cfifo_empty),
   .cfifo_re_o    (cfifo_re),
   .clk40         (clk40),
   .rstb          (rstb)
);

lcb_syncfifo Ucbusfifo(
   .dIn        (cbus_all),
   .dOut       (cfifo_all),
   .we         (cbus_valid),
   .re         (cfifo_re),
   .full       (),
   .almostFull (),
   .empty      (cfifo_empty),
   .clk        (clk40),
   .rstb       (rstb)
);


// ModuleWare code(v1.12) for instance 'U_0' of 'inv'
assign rst = ~rstb;

endmodule // lcb_core