--
-- ITk Strips LCB
--
-- Simple DDR Decoder
--
-- Matt Warren 
--


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library downlink;
use downlink.lcb_pkg_globals.all;

entity lcb_ddr_dec is
   port(

      ddr_i   : in     std_logic;
      d0_o    : out    std_logic;
      d1_o    : out    std_logic;
      clk     : in     std_logic

   );

-- Declarations

end entity lcb_ddr_dec ;

---------------------------------------------------------------------------
architecture rtl of lcb_ddr_dec is

  signal d0_q : std_logic;
  signal d1_q : std_logic;

begin

-- Simple DDR input decoder

    d0_q <= ddr_i when rising_edge(clk);
    d1_q <= ddr_i when falling_edge(clk);

    -- both now clocked by rising and in phase ...
    d0_o <= d0_q when rising_edge(clk);
    d1_o <= d1_q when rising_edge(clk);


end rtl;