//--------------------------------------------------
//--                                                                                                                                                                                            
//--version 3.0_lcb
//
//-- 2016/12/10 Copied for LCB work, with parameters defaulted to desired values
// for easier VHDL  integration
//                                                                                                 //
//                                                                                           
//--------------------------------------------------
//--------------------------------------------------
//  
//      Verilog code generated by Visual Elite
//
//  Design Unit:
//  ------------
//      Unit    Name  :  hcc_syncFifo
//      Library Name  :  HCC_v2
//  
//      Creation Date :  Tue Dec 04 11:05:00 2012
//      Version       :  2011.02 v4.3.0 build 24. Date: Mar 21 2011. License: 2011.3
//  
//  Options Used:
//  -------------
//      Target
//         Language   :  Verilog
//         Purpose    :  Synthesis
//         Vendor     :  Leonardo
//  
//      Style
//         Use tasks                      :  No
//         Code Destination               :  Combined file
//         Attach Directives              :  Yes
//         Structural                     :  No
//         Free text style                :  / / ...
//         Preserve spacing for free text :  Yes
//         Declaration alignment          :  No
//
//--------------------------------------------------
//--------------------------------------------------
//  
//  Library Name :  HCC_v2
//  Unit    Name :  hcc_syncFifo
//  Unit    Type :  Text Unit
//  
//----------------------------------------------------
`timescale 1ns/1ps
//`uselib lib=HCC_LIB

module lcb_syncfifo(
   input   wire    [8:0]  dIn,
   output  wire    [8:0]  dOut,
   input   wire           we,
   input   wire           re,
   output  wire           full,
   output  wire           almostFull,
   output  wire           empty,
   input   wire           clk,
   input   wire           rstb
);

// synopsys template
// Internal Declarations

// synopsys template
parameter WORDWIDTH = 9,
          logDEPTH  = 3,
          MAX       = 2 ** logDEPTH;
  reg [ logDEPTH - 1: 0] rPtr;
  reg [ logDEPTH - 1  : 0] wPtr;
  reg [ logDEPTH : 0] occupancy;  //room to detect overflow
  reg [ WORDWIDTH - 1:0] mem[ MAX-1 : 0];

  assign empty = ( occupancy == 'h0);
  assign full = ( occupancy == MAX );
//  assign almostFull = ( occupancy == (MAX - 1) );
  assign almostFull = ( occupancy >= (MAX - 1) );
//  assign almostFull = ( occupancy >= (MAX - 2) );

  always @(posedge clk )
    if ( rstb == 1'b0 ) begin
      wPtr <=  'h0;
      rPtr <=  'h0;
    end //rstb
    else begin
      if ( we == 1'b1 )
	wPtr <= wPtr + 1'b1;
      if ( re == 1'b1 )
	rPtr <= rPtr + 1'b1;
    end //not reset

  assign dOut = mem[rPtr] ;  //output always valid, at current read pointer.

/* `ifdef MEM_INIT
  //memory contents are not initialized
  //this is behavioral!!!
  integer index;
  always @(posedge clk)
    if ( rstb == 1'b0 ) begin
      for ( index = 0; index < MAX; index = index + 1 ) 
        mem[ index] = 'h0;
    end
 `endif
*/
   integer index;
  always @(posedge clk )
    begin
       if ( rstb == 1'b0 )
	 begin
	    for ( index = 0; index < MAX; index = index + 1 )
              mem[ index] <= 'h0;
	 end
       else
	 if ( we ) mem[ wPtr ] <= dIn;
    end // always @ (posedge clk )


  //calculate the occupancy of the fifo
  always @(posedge clk )
    if ( rstb == 1'b0 ) occupancy <= 'h0;
    else begin
      case ( {re, we } )
        2'b10 :  begin
           occupancy <= occupancy - 1'b1;
        end
        2'b01 :  begin
           occupancy <= occupancy + 1'b1;
        end
      endcase
    end //not reset

endmodule