Declarations

Ports:

Diagram Signals:

wire         clk160;
wire         clk40;
wire         rst;
wire         l0a_in;
wire         bcr_in;
wire [6:0]   tag_in;
wire         cmdfrm_ready;
wire [48:0]  cmdfrm;
wire [4:0]   encoder_hccid;
wire         rstb;
wire         cmd_gen_busy;
wire [4:0]   dut_hccid;
wire [3:0]   dut_abcid;
wire [1:0]   enc_frame_sync;
wire         enc_lcb;
wire         abc_l0a;
wire [6:0]   abc_l0a_tag;
wire         abc_bcr;
wire [3:0]   abc_fast_cmd;
wire [7:0]   abc_rb_addr;
wire         abc_rb_init;
wire         abc_rb_load;
wire         abc_rb_rnw;
wire         abc_rb_sdat;
wire         abc_rb_shen;
wire         abc_rb_busy;
wire         HI;
wire         LO;
wire [31:0]  testreg;

Pre User:

Post User:

Compiler Directives

Pre-module directives:

`resetall
`timescale 1ns/1ps

Post-module directives:

End-module directives:

Bundles