//
// Module downlink.lcbtst_abc_top_tb.struct
//
// Created:
//          by - cvmfs.users (pc201.hep.ucl.ac.uk)
//          at - 11:01:00 12/21/16
//
// Generated by Mentor Graphics' HDL Designer(TM) 2015.2 (Build 5)
//

`resetall
`timescale 1ns/1ps
module lcbtst_abc_top_tb;


// Internal Declarations


// Local declarations

// Internal signal declarations
wire         HI;
wire         LO;
wire         abc_bcr;
wire  [3:0]  abc_fast_cmd;
wire         abc_l0a;
wire  [6:0]  abc_l0a_tag;
wire  [7:0]  abc_rb_addr;
wire         abc_rb_busy;
wire         abc_rb_init;
wire         abc_rb_load;
wire         abc_rb_rnw;
wire         abc_rb_sdat;
wire         abc_rb_shen;
wire         bcr_in;
wire         clk160;
wire         clk40;
wire         cmd_gen_busy;
wire  [48:0] cmdfrm;
wire         cmdfrm_ready;
wire  [3:0]  dut_abcid;
wire  [4:0]  dut_hccid;
wire  [1:0]  enc_frame_sync;
wire         enc_lcb;
wire  [4:0]  encoder_hccid;
wire         l0a_in;
wire         rst;
wire         rstb;
wire  [6:0]  tag_in;
wire  [31:0] testreg;

// ModuleWare signal declarations(v1.12) for instance 'U_1' of 'shiftsp'
reg [31:0] mw_U_1reg_cval;
wire [31:0] mw_U_1reg_nval;


// Instances 
lcb_abc_top Uabc(
   .abcid_i    (dut_abcid),
   .clk160     (clk160),
   .clk40      (clk40),
   .lcb_i      (enc_lcb),
   .rb_busy_i  (abc_rb_busy),
   .rstb       (rstb),
   .bcr_o      (abc_bcr),
   .fast_cmd_o (abc_fast_cmd),
   .l0a_o      (abc_l0a),
   .l0a_tag_o  (abc_l0a_tag),
   .rb_addr_o  (abc_rb_addr),
   .rb_init_o  (abc_rb_init),
   .rb_load_o  (abc_rb_load),
   .rb_rnw_o   (abc_rb_rnw),
   .rb_sdat_o  (abc_rb_sdat),
   .rb_shen_o  (abc_rb_shen)
);

lcbtst_generator Ulcbgen(
   .bcr_in        (bcr_in),
   .clk160        (clk160),
   .clk40         (clk40),
   .cmdfrm        (cmdfrm),
   .cmdfrm_ready  (cmdfrm_ready),
   .encoder_hccid (encoder_hccid),
   .l0a_in        (l0a_in),
   .rst           (rst),
   .tag_in        (tag_in),
   .cmd_gen_busy  (cmd_gen_busy),
   .frame_sync_o  (enc_frame_sync),
   .lcb_o         (enc_lcb)
);

lcbtst_tester Utester(
   .cmdfrm_ready_o   (cmdfrm_ready),
   .cmd_gen_busy_i   (cmd_gen_busy),
   .cmdfrm_o         (cmdfrm),
   .dut_hccid_o      (dut_hccid),
   .dut_abcid_o      (dut_abcid),
   .encoder_hccid_o  (encoder_hccid),
   .enc_frame_sync_i (enc_frame_sync),
   .rb_busy_o        (abc_rb_busy),
   .ser_o            (),
   .l0a_o            (l0a_in),
   .bcr_o            (bcr_in),
   .tag_o            (tag_in),
   .clk160_o         (clk160),
   .clk40_o          (clk40),
   .rstb_o           (rstb),
   .rst_o            (rst)
);

// HDL Embedded Text Block 3 eb3
assign LO = 1'b0;
assign HI = 1'b1;


// ModuleWare code(v1.12) for instance 'U_1' of 'shiftsp'
assign testreg = mw_U_1reg_cval;
always @(posedge clk40, posedge rst)
begin : u_1seq_proc
   if (rst)
      mw_U_1reg_cval = 32'd0;
   else if (abc_rb_shen)
      mw_U_1reg_cval = mw_U_1reg_nval;
end
assign mw_U_1reg_nval = LO ? {abc_rb_sdat, mw_U_1reg_cval} >> 1
   : {mw_U_1reg_cval,abc_rb_sdat};

endmodule // lcbtst_abc_top_tb