// // Module downlink.lcbtst_generator.struct // // Created: // by - warren.warren (mbb) // at - 00:25:39 12/19/16 // // Generated by Mentor Graphics' HDL Designer(TM) 2015.2 (Build 5) // `resetall `timescale 1ns/1ps module lcbtst_generator( // Port Declarations input wire bcr_in, input wire clk160, input wire clk40, input wire [48:0] cmdfrm, input wire cmdfrm_ready, input wire [4:0] encoder_hccid, input wire l0a_in, input wire rst, input wire [6:0] tag_in, output wire cmd_gen_busy, output wire [1:0] frame_sync_o, output wire lcb_o ); // Internal Declarations // Local declarations // Internal signal declarations wire HI; wire LO; wire [1:0] ONEZERO; wire cmd7_ack; wire cmd7_end; wire [6:0] cmd7_in; wire cmd7_ready; wire cmd7_start; wire [1:0] e_frame_sync; wire [3:0] e_par4_out; // Instances lcb_serialiser Ueserout( .frame_sync_i (e_frame_sync), .par4_i (e_par4_out), .delay160_i (ONEZERO), .ser_o (lcb_o), .clk160 (clk160), .rst (rst) ); lcbtst_cmd7_gen Ucmd7_gen( .cmdfrm_ready_i (cmdfrm_ready), .cmd7_gen_busy_o (cmd_gen_busy), .cmdfrm_i (cmdfrm), .cmd7_o (cmd7_in), .cmd7_start_o (cmd7_start), .cmd7_ready_o (cmd7_ready), .cmd7_end_o (cmd7_end), .cmd7_ack_i (cmd7_ack), .clk40 (clk40), .rst (rst) ); lcbtst_encoder Uencoder( .hccid_i (encoder_hccid), .l0a_i (l0a_in), .bcr_i (bcr_in), .tag_i (tag_in), .cmd7_i (cmd7_in), .cmd7_start_i (cmd7_start), .cmd7_ready_i (cmd7_ready), .cmd7_end_i (cmd7_end), .cmd7_ack_o (cmd7_ack), .frame_sync_o (e_frame_sync), .par4_o (e_par4_out), .clk40 (clk40), .rst (rst) ); // HDL Embedded Text Block 2 eb2 assign LO = 1'b0; assign HI = 1'b1; assign ONEZERO = 2'b10; // ModuleWare code(v1.12) for instance 'U_0' of 'buff' assign frame_sync_o = e_frame_sync; endmodule // lcbtst_generator