-- VHDL Entity readout130.star_flink_tb.symbol
--
-- Created by Matt Warren 2015
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2015.1 (Build 16)
--



entity star_flink_tb is
-- Declarations

end star_flink_tb ;

-- VHDL from Block Diagram 
-- Generated by Mentor Graphics HDL Designer(TM) 2015.1 (Build 16) 
--
-- readout130.star_flink_tb.struct
--
-- Created by Matt Warren 2015
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
library readout130;
use readout130.pkg_star_flink.ALL;


architecture struct of star_flink_tb is

   -- Architecture declarations

   -- Internal signal declarations
   signal bcr_in        : std_logic;
   signal bcr_out       : std_logic;
   signal clk           : std_logic;
   signal clk160        : std_logic;
   signal dec_error     : std_logic;                       -- asserted if a symbol decodes as "1111" or "0000"
   signal dec_isidle    : std_logic;
   signal dec_output_en : std_logic;
   signal dec_spysymb   : t_usymbol;
   signal dec_symbol    : std_logic_vector(3 downto 0);
   signal enc_isidle    : std_logic;
   signal enc_spysymb   : t_usymbol;
   signal enc_symbol    : std_logic_vector(3 downto 0);
   signal flink         : std_logic;
   signal l0id_out      : std_logic_vector(7 downto 0);
   signal lp_in_done    : std_logic;
   signal lp_in_l0id    : std_logic_vector(7 downto 0);
   signal lp_in_req     : std_logic;
   signal lp_out_valid  : std_logic;
   signal ls_in         : std_logic;
   signal ls_out        : std_logic;
   signal pr_in_done    : std_logic;
   signal pr_in_l0id    : std_logic_vector(7 downto 0);
   signal pr_in_req     : std_logic;
   signal pr_out_valid  : std_logic;
   signal rst           : std_logic;
   signal symbol_align  : std_logic_vector(2 downto 0);


   -- Component Declarations
   component star_flink_decoder
   port (
      -- 160 MHz domain
      -----------------------------------------
      ser_i          : in     std_logic ;                    -- serial input
      clk160         : in     std_logic ;                    -- sample clock
      -- 40MHz domain
      ------------------------------------------------
      symbol_align_i : in     std_logic_vector (2 downto 0); -- alignment control
      symbol_o       : out    std_logic_vector (3 downto 0); -- output of deser after alignment
      output_en_i    : in     std_logic ;                    -- enable signals after align
      isidle_o       : out    std_logic ;                    -- might be useful for auto-align
      error_o        : out    std_logic ;                    -- asserted if a symbol decodes as "1111" or "0000"
      -- Signals/data out
      bcr_o          : out    std_logic ;
      ls_o           : out    std_logic ;
      l0id_o         : out    std_logic_vector (7 downto 0); -- single L0ID bus
      pr_valid_o     : out    std_logic ;                    -- L0ID is for PR
      lp_valid_o     : out    std_logic ;                    -- L0ID is for LP
      -- Infra
      clk            : in     std_logic ;
      rst            : in     std_logic
   );
   end component;
   component star_flink_encoder
   port (
      bcr_i     : in     std_logic;
      clk       : in     std_logic;
      clk160    : in     std_logic;
      lp_l0id_i : in     std_logic_vector (7 downto 0);
      lp_req_i  : in     std_logic;
      ls_i      : in     std_logic;
      pr_l0id_i : in     std_logic_vector (7 downto 0);
      pr_req_i  : in     std_logic;
      rst       : in     std_logic;
      isidle_o  : out    std_logic;
      lp_done_o : out    std_logic;
      pr_done_o : out    std_logic;
      ser_o     : out    std_logic;
      symbol_o  : out    std_logic_vector (3 downto 0)
   );
   end component;
   component star_flink_sim_spy
   port (
      symbol_i  : in     std_logic_vector (3 downto 0);
      spysymb_o : out    t_usymbol
   );
   end component;
   component star_flink_tester
   port (
      lp_done_i       : in     std_logic;
      pr_done_i       : in     std_logic;
      bcr_o           : out    std_logic;
      clk160_o        : out    std_logic;
      clk40_o         : out    std_logic;
      dec_output_en_o : out    std_logic;
      lp_l0id_o       : out    std_logic_vector (7 downto 0);
      lp_req_o        : out    std_logic;
      ls_o            : out    std_logic;
      pr_l0id_o       : out    std_logic_vector (7 downto 0);
      pr_req_o        : out    std_logic;
      rst_o           : out    std_logic;
      symbol_align_o  : out    std_logic_vector (2 downto 0)
   );
   end component;


begin

   -- Instance port mappings.
   Usfdec : star_flink_decoder
      port map (
         ser_i          => flink,
         clk160         => clk160,
         symbol_align_i => symbol_align,
         symbol_o       => dec_symbol,
         output_en_i    => dec_output_en,
         isidle_o       => dec_isidle,
         error_o        => dec_error,
         bcr_o          => bcr_out,
         ls_o           => ls_out,
         l0id_o         => l0id_out,
         pr_valid_o     => pr_out_valid,
         lp_valid_o     => lp_out_valid,
         clk            => clk,
         rst            => rst
      );
   Usfenc : star_flink_encoder
      port map (
         clk160    => clk160,
         ser_o     => flink,
         bcr_i     => bcr_in,
         ls_i      => ls_in,
         pr_l0id_i => pr_in_l0id,
         pr_req_i  => pr_in_req,
         pr_done_o => pr_in_done,
         lp_l0id_i => lp_in_l0id,
         lp_req_i  => lp_in_req,
         lp_done_o => lp_in_done,
         isidle_o  => enc_isidle,
         symbol_o  => enc_symbol,
         clk       => clk,
         rst       => rst
      );
   Udecspy : star_flink_sim_spy
      port map (
         symbol_i  => dec_symbol,
         spysymb_o => dec_spysymb
      );
   Uencspy : star_flink_sim_spy
      port map (
         symbol_i  => enc_symbol,
         spysymb_o => enc_spysymb
      );
   Utstr : star_flink_tester
      port map (
         symbol_align_o  => symbol_align,
         dec_output_en_o => dec_output_en,
         bcr_o           => bcr_in,
         ls_o            => ls_in,
         lp_l0id_o       => lp_in_l0id,
         lp_req_o        => lp_in_req,
         lp_done_i       => lp_in_done,
         pr_l0id_o       => pr_in_l0id,
         pr_req_o        => pr_in_req,
         pr_done_i       => pr_in_done,
         clk160_o        => clk160,
         clk40_o         => clk,
         rst_o           => rst
      );

end struct;