##############################################################
#
# Xilinx Core Generator version K.39
# Date: Tue Jul 14 12:05:24 2009
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatParenNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc4vfx60
SET devicefamily = virtex4
SET flowvendor = MentorHDL
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Edif
SET package = ff1152
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -11
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Embedded_Tri-mode_Ethernet_MAC_Wrapper family Xilinx,_Inc. 4.6
# END Select
# BEGIN Parameters
CSET address_filter_enable_0=false
CSET address_filter_enable_1=false
CSET byte_phy_0=false
CSET byte_phy_1=false
CSET client_side_data_width_0=8_bit
CSET client_side_data_width_1=8_bit
CSET clock_enable_0=false
CSET clock_enable_1=false
CSET component_name=eth_gmii
CSET enable_emac0=true
CSET enable_emac1=false
CSET host_type=Host
CSET mdio_0=true
CSET mdio_1=false
CSET phy_an_enable_0=false
CSET phy_an_enable_1=false
CSET phy_isolate_0=false
CSET phy_isolate_1=false
CSET phy_loopback_msb_0=false
CSET phy_loopback_msb_1=false
CSET phy_powerdown_0=false
CSET phy_powerdown_1=false
CSET phy_reset_0=false
CSET phy_reset_1=false
CSET physical_interface_0=GMII
CSET physical_interface_1=GMII
CSET rx_disable_length_0=false
CSET rx_disable_length_1=false
CSET rx_enable_0=true
CSET rx_enable_1=true
CSET rx_flow_control_enable_0=false
CSET rx_flow_control_enable_1=false
CSET rx_half_duplex_enable_0=false
CSET rx_half_duplex_enable_1=false
CSET rx_in_band_fcs_enable_0=false
CSET rx_in_band_fcs_enable_1=false
CSET rx_jumbo_frame_enable_0=false
CSET rx_jumbo_frame_enable_1=false
CSET rx_reset_0=false
CSET rx_reset_1=false
CSET rx_vlan_enable_0=false
CSET rx_vlan_enable_1=false
CSET sgmii_mode_0=No_clock
CSET sgmii_mode_1=No_clock
CSET speed_0=Tri_speed
CSET speed_1=1000_Mbps
CSET tx_enable_0=true
CSET tx_enable_1=true
CSET tx_flow_control_enable_0=false
CSET tx_flow_control_enable_1=false
CSET tx_half_duplex_enable_0=false
CSET tx_half_duplex_enable_1=false
CSET tx_ifg_adjust_enable_0=false
CSET tx_ifg_adjust_enable_1=false
CSET tx_in_band_fcs_enable_0=false
CSET tx_in_band_fcs_enable_1=false
CSET tx_jumbo_frame_enable_0=false
CSET tx_jumbo_frame_enable_1=false
CSET tx_reset_0=false
CSET tx_reset_1=false
CSET tx_vlan_enable_0=false
CSET tx_vlan_enable_1=false
CSET unicast_pause_mac_address_0_1=AA
CSET unicast_pause_mac_address_0_2=BB
CSET unicast_pause_mac_address_0_3=CC
CSET unicast_pause_mac_address_0_4=DD
CSET unicast_pause_mac_address_0_5=EE
CSET unicast_pause_mac_address_0_6=FF
CSET unicast_pause_mac_address_1_1=AA
CSET unicast_pause_mac_address_1_2=BB
CSET unicast_pause_mac_address_1_3=CC
CSET unicast_pause_mac_address_1_4=DD
CSET unicast_pause_mac_address_1_5=EE
CSET unicast_pause_mac_address_1_6=FF
# END Parameters
GENERATE
# CRC: 743930bb