##############################################################
#
# Xilinx Core Generator version 11.3
# Date: Mon Oct 26 11:47:39 2009
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatParenNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc4vfx60
SET devicefamily = virtex4
SET flowvendor = MentorHDL
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1152
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -11
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 5.3
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=true
CSET component_name=cg_dfifo_32x16
CSET data_count=false
CSET data_count_width=5
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=false
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=29
CSET full_threshold_negate_value=28
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=16
CSET input_depth=32
CSET output_data_width=16
CSET output_depth=32
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=5
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=5
# END Parameters
GENERATE
# CRC: 3b4691b2