--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: L.57
--  \   \         Application: netgen
--  /   /         Filename: cg_dfifo_32x16_ft.vhd
-- /___/   /\     Timestamp: Mon Oct 26 14:05:11 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -w -sim -ofmt vhdl ./tmp/_cg/cg_dfifo_32x16_ft.ngc ./tmp/_cg/cg_dfifo_32x16_ft.vhd 
-- Device	: 4vfx60ff1152-11
-- Input file	: ./tmp/_cg/cg_dfifo_32x16_ft.ngc
-- Output file	: ./tmp/_cg/cg_dfifo_32x16_ft.vhd
-- # of Entities	: 1
-- Design Name	: cg_dfifo_32x16_ft
-- Xilinx	: /unix/local/xilinx/11.1/ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Command Line Tools User Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------


-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity cg_dfifo_32x16_ft is
  port (
    rd_rst : in STD_LOGIC := 'X'; 
    rd_en : in STD_LOGIC := 'X'; 
    almost_full : out STD_LOGIC; 
    wr_en : in STD_LOGIC := 'X'; 
    full : out STD_LOGIC; 
    empty : out STD_LOGIC; 
    wr_clk : in STD_LOGIC := 'X'; 
    wr_rst : in STD_LOGIC := 'X'; 
    rd_clk : in STD_LOGIC := 'X'; 
    dout : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    din : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end cg_dfifo_32x16_ft;

architecture STRUCTURE of cg_dfifo_32x16_ft is
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_comp2 : STD_LOGIC; 
  signal BU2_N22 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or000063_254 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_15_rstpot_253 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_14_rstpot_251 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_13_rstpot_249 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_12_rstpot_247 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_11_rstpot_245 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_10_rstpot_243 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_9_rstpot_241 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_8_rstpot_239 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_7_rstpot_237 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_6_rstpot_235 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_5_rstpot_233 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_4_rstpot_231 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_3_rstpot_229 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_2_rstpot_227 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_1_rstpot_225 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i_0_rstpot_223 : STD_LOGIC; 
  signal BU2_N20 : STD_LOGIC; 
  signal BU2_N18 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000069_219 : STD_LOGIC; 
  signal BU2_N25 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000067_217 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000026_216 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_c2_dout_i62_215 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000158_214 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000063_213 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000156_212 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000115_211 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000062_210 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000026_209 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_ram_rd_en_i : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_rpntr_N11 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_N11 : STD_LOGIC; 
  signal BU2_N16 : STD_LOGIC; 
  signal BU2_N14 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux0000 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_not0001 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_wr_rst_d1_201 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_fb_i_200 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or0000 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_dout_i_and0000 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N67 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N65 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N61 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N59 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N63 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N55 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N53 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N57 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N49 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N47 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N51 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N43 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N41 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N45 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N37 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N35 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N39 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N31 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N29 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N33 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N25 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N23 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N27 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N19 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N17 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N21 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N13 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N11 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N15 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N9 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N7 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_N5 : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count2 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count1 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count3 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count4 : STD_LOGIC; 
  signal BU2_U0_grf_rf_ram_wr_en : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_fb_118 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_i_or0000 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count2 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count1 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count3 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count4 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0003 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0002 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0001 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0000 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0003 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0002 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0001 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0000 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0003_62 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0002 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0001 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0000 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0003_52 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0002 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0001 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0000 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_43 : STD_LOGIC; 
  signal BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000 : STD_LOGIC; 
  signal NLW_VCC_P_UNCONNECTED : STD_LOGIC; 
  signal NLW_GND_G_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM32_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM31_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM29_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM28_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM30_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM26_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM25_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM27_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM23_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM22_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM24_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM20_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM19_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM21_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM17_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM16_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM18_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM14_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM13_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM15_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM11_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM10_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM12_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM8_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM7_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM9_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM5_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM6_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED : STD_LOGIC; 
  signal NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED : STD_LOGIC; 
  signal BU2_U0_grf_rf_mem_gdm_dm_varindex0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_grf_rf_mem_gdm_dm_dout_i : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_count_d3 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_grf_rf_gl0_rd_gr1_rfwft_next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BU2_U0_grf_rf_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BU2_rd_data_count : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  VCC_0 : VCC
    port map (
      P => NLW_VCC_P_UNCONNECTED
    );
  GND_1 : GND
    port map (
      G => NLW_GND_G_UNCONNECTED
    );
  BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000063 : LUT3_L
    generic map(
      INIT => X"90"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(0),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      I2 => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000062_210,
      LO => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000063_213
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_c2_dout_i79 : LUT4_D
    generic map(
      INIT => X"0900"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(4),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(4),
      I2 => BU2_N18,
      I3 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_c2_dout_i62_215,
      LO => BU2_N25,
      O => BU2_U0_grf_rf_gl0_wr_gwas_wsts_comp2
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or000063 : LUT4_L
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(3),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(3),
      I2 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(2),
      I3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(2),
      LO => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or000063_254
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count_xor_3_111 : LUT3_L
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count(0),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count(1),
      I2 => BU2_U0_grf_rf_gl0_rd_rpntr_count(2),
      LO => BU2_U0_grf_rf_gl0_rd_rpntr_N11
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count_xor_3_111 : LUT3_L
    generic map(
      INIT => X"7F"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_wpntr_count(0),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count(1),
      I2 => BU2_U0_grf_rf_gl0_wr_wpntr_count(2),
      LO => BU2_U0_grf_rf_gl0_wr_wpntr_N11
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX11 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N5,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N7,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(0)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX1011 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N45,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N47,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(10)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX1111 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N9,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N11,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(1)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX11111 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N49,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N51,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(11)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX1211 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N53,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N55,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(12)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX1311 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N57,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N59,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(13)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX1411 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N61,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N63,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(14)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX1511 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N65,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N67,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(15)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX211 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N13,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N15,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(2)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX311 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N17,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N19,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(3)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX411 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N21,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N23,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(4)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX511 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N25,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N27,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(5)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX611 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N29,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N31,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(6)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX711 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N33,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N35,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(7)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX811 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N37,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N39,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(8)
    );
  BU2_U0_grf_rf_mem_gdm_dm_inst_LPM_MUX911 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_mem_gdm_dm_N41,
      I2 => BU2_U0_grf_rf_mem_gdm_dm_N43,
      LO => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(9)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
    port map (
      I => BU2_U0_grf_rf_gl0_rd_rpntr_count(0),
      O => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
    port map (
      I => BU2_U0_grf_rf_gl0_wr_wpntr_count(0),
      O => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count
    );
  BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_1 : LUT4
    generic map(
      INIT => X"2333"
    )
    port map (
      I0 => rd_en,
      I1 => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_43,
      I2 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(1),
      I3 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(0),
      O => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count_xor_3_12 : LUT4
    generic map(
      INIT => X"6AAA"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count(3),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count(0),
      I2 => BU2_U0_grf_rf_gl0_rd_rpntr_count(1),
      I3 => BU2_U0_grf_rf_gl0_rd_rpntr_count(2),
      O => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count3
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count_xor_3_12 : LUT4
    generic map(
      INIT => X"6AAA"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_wpntr_count(3),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count(0),
      I2 => BU2_U0_grf_rf_gl0_wr_wpntr_count(1),
      I3 => BU2_U0_grf_rf_gl0_wr_wpntr_count(2),
      O => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count3
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or000091 : LUT4
    generic map(
      INIT => X"2F0F"
    )
    port map (
      I0 => wr_en,
      I1 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_fb_i_200,
      I2 => BU2_N22,
      I3 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_comp2,
      O => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or0000
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or000091_SW0 : LUT4
    generic map(
      INIT => X"FF6F"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(4),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(4),
      I2 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or000063_254,
      I3 => BU2_N20,
      O => BU2_N22
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_15 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_15_rstpot_253,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(15)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_15_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(15),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(15),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_15_rstpot_253
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_14 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_14_rstpot_251,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(14)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_14_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(14),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(14),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_14_rstpot_251
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_13 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_13_rstpot_249,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(13)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_13_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(13),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(13),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_13_rstpot_249
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_12 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_12_rstpot_247,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(12)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_12_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(12),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(12),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_12_rstpot_247
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_11 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_11_rstpot_245,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(11)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_11_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(11),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(11),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_11_rstpot_245
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_10 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_10_rstpot_243,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(10)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_10_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(10),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(10),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_10_rstpot_243
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_9 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_9_rstpot_241,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(9)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_9_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(9),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(9),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_9_rstpot_241
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_8 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_8_rstpot_239,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(8)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_8_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(8),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(8),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_8_rstpot_239
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_7 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_7_rstpot_237,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(7)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_7_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(7),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(7),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_7_rstpot_237
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_6 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_6_rstpot_235,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(6)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_6_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(6),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(6),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_6_rstpot_235
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_5 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_5_rstpot_233,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(5)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_5_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(5),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(5),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_5_rstpot_233
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_4 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_4_rstpot_231,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(4)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_4_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(4),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(4),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_4_rstpot_231
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_3 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_3_rstpot_229,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(3)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_3_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(3),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(3),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_3_rstpot_229
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_2 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_2_rstpot_227,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(2)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_2_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(2),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(2),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_2_rstpot_227
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_1 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_1_rstpot_225,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(1)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_1_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(1),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(1),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_1_rstpot_225
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_0 : FDR
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i_0_rstpot_223,
      R => BU2_rd_data_count(0),
      Q => BU2_U0_grf_rf_mem_gdm_dm_dout_i(0)
    );
  BU2_U0_grf_rf_mem_gdm_dm_dout_i_0_rstpot : LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => BU2_U0_grf_rf_mem_ram_rd_en_i,
      I1 => BU2_U0_grf_rf_mem_gdm_dm_dout_i(0),
      I2 => BU2_U0_grf_rf_mem_gdm_dm_varindex0000(0),
      O => BU2_U0_grf_rf_mem_gdm_dm_dout_i_0_rstpot_223
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000069 : LUT4
    generic map(
      INIT => X"9000"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(0),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count(0),
      I2 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000067_217,
      I3 => BU2_U0_grf_rf_ram_wr_en,
      O => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000069_219
    );
  BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000158 : LUT4
    generic map(
      INIT => X"9000"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(0),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count(0),
      I2 => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000156_212,
      I3 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      O => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000158_214
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or000080_SW0 : LUT4
    generic map(
      INIT => X"6FF6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(0),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(0),
      I2 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(1),
      I3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(1),
      O => BU2_N20
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_c2_dout_i79_SW0 : LUT4
    generic map(
      INIT => X"6FF6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(0),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(0),
      I2 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(1),
      I3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(1),
      O => BU2_N18
    );
  BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1 : LUT3
    generic map(
      INIT => X"08"
    )
    port map (
      I0 => wr_en,
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(4),
      I2 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_fb_i_200,
      O => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150
    );
  BU2_U0_grf_rf_mem_gdm_dm_write_ctrl : LUT3
    generic map(
      INIT => X"02"
    )
    port map (
      I0 => wr_en,
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(4),
      I2 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_fb_i_200,
      O => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148
    );
  BU2_U0_grf_rf_gl0_wr_ram_wr_en_i1 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => wr_en,
      I1 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_fb_i_200,
      O => BU2_U0_grf_rf_ram_wr_en
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux0000107 : LUT4
    generic map(
      INIT => X"5450"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_wr_rst_d1_201,
      I1 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000026_216,
      I2 => BU2_N25,
      I3 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000069_219,
      O => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux0000
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000067 : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(2),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count(2),
      I2 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(1),
      I3 => BU2_U0_grf_rf_gl0_wr_wpntr_count(1),
      O => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000067_217
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000026 : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(4),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count(4),
      I2 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(3),
      I3 => BU2_U0_grf_rf_gl0_wr_wpntr_count(3),
      O => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux000026_216
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_c2_dout_i62 : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(3),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(3),
      I2 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(2),
      I3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(2),
      O => BU2_U0_grf_rf_gl0_wr_gwas_wsts_c2_dout_i62_215
    );
  BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000183 : LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000115_211,
      I1 => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000026_209,
      I2 => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000063_213,
      I3 => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000158_214,
      O => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000
    );
  BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000156 : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count(2),
      I1 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(2),
      I2 => BU2_U0_grf_rf_gl0_rd_rpntr_count(1),
      I3 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(1),
      O => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000156_212
    );
  BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000115 : LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count(4),
      I1 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(4),
      I2 => BU2_U0_grf_rf_gl0_rd_rpntr_count(3),
      I3 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(3),
      O => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000115_211
    );
  BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000062 : LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(2),
      I1 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(3),
      I2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      I3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      O => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000062_210
    );
  BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000026 : LUT4
    generic map(
      INIT => X"8241"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(1),
      I1 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(4),
      I2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      O => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000026_209
    );
  BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21 : LUT4
    generic map(
      INIT => X"2333"
    )
    port map (
      I0 => rd_en,
      I1 => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_43,
      I2 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(1),
      I3 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(0),
      O => BU2_U0_grf_rf_mem_ram_rd_en_i
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count_xor_4_11 : LUT3
    generic map(
      INIT => X"A6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count(4),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count(3),
      I2 => BU2_U0_grf_rf_gl0_rd_rpntr_N11,
      O => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count4
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count_xor_4_11 : LUT3
    generic map(
      INIT => X"A6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_wpntr_count(4),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count(3),
      I2 => BU2_U0_grf_rf_gl0_wr_wpntr_N11,
      O => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count4
    );
  BU2_U0_grf_rf_mem_dout_i_and00001 : LUT4
    generic map(
      INIT => X"4404"
    )
    port map (
      I0 => rd_rst,
      I1 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(1),
      I2 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(0),
      I3 => rd_en,
      O => BU2_U0_grf_rf_mem_dout_i_and0000
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_not00011 : LUT2
    generic map(
      INIT => X"B"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_wr_rst_d1_201,
      I1 => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_fb_i_200,
      O => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_not0001
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0003 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(4),
      I1 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(0),
      I2 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(3),
      I3 => BU2_N16,
      O => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0003_52
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0003_SW0 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(2),
      I1 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(1),
      O => BU2_N16
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0003 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(4),
      I1 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(0),
      I2 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(3),
      I3 => BU2_N14,
      O => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0003_62
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0003_SW0 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(2),
      I1 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(1),
      O => BU2_N14
    );
  BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_i_or00001 : LUT4
    generic map(
      INIT => X"8E8A"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_fb_118,
      I1 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(0),
      I2 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(1),
      I3 => rd_en,
      O => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_i_or0000
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor00021 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(2),
      I1 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(1),
      I2 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(4),
      I3 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(3),
      O => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0002
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor00021 : LUT4
    generic map(
      INIT => X"6996"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(2),
      I1 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(1),
      I2 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(4),
      I3 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(3),
      O => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0002
    );
  BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_next_fwft_state41 : LUT4
    generic map(
      INIT => X"5D55"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_43,
      I1 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(1),
      I2 => rd_en,
      I3 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(0),
      O => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_next_fwft_state(1)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count(2),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count(1),
      I2 => BU2_U0_grf_rf_gl0_rd_rpntr_count(0),
      O => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count2
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
    generic map(
      INIT => X"6A"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_wpntr_count(2),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count(1),
      I2 => BU2_U0_grf_rf_gl0_wr_wpntr_count(0),
      O => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count2
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor00011 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(4),
      I1 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(3),
      I2 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(2),
      O => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0001
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor00011 : LUT3
    generic map(
      INIT => X"96"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(4),
      I1 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(3),
      I2 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(2),
      O => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0001
    );
  BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_next_fwft_state11 : LUT3
    generic map(
      INIT => X"BA"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(1),
      I1 => rd_en,
      I2 => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(0),
      O => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_next_fwft_state(0)
    );
  BU2_U0_grf_rf_gcx_clkx_Mxor_rd_pntr_gc_xor0000_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      O => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0000
    );
  BU2_U0_grf_rf_gcx_clkx_Mxor_rd_pntr_gc_xor0001_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      O => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0001
    );
  BU2_U0_grf_rf_gcx_clkx_Mxor_rd_pntr_gc_xor0002_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      O => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0002
    );
  BU2_U0_grf_rf_gcx_clkx_Mxor_rd_pntr_gc_xor0003_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      O => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0003
    );
  BU2_U0_grf_rf_gcx_clkx_Mxor_wr_pntr_gc_xor0000_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(4),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      O => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0000
    );
  BU2_U0_grf_rf_gcx_clkx_Mxor_wr_pntr_gc_xor0001_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      O => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0001
    );
  BU2_U0_grf_rf_gcx_clkx_Mxor_wr_pntr_gc_xor0002_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      O => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0002
    );
  BU2_U0_grf_rf_gcx_clkx_Mxor_wr_pntr_gc_xor0003_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      O => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0003
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_rd_rpntr_count(1),
      I1 => BU2_U0_grf_rf_gl0_rd_rpntr_count(0),
      O => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count1
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gl0_wr_wpntr_count(1),
      I1 => BU2_U0_grf_rf_gl0_wr_wpntr_count(0),
      O => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count1
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor00001 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(3),
      I1 => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(4),
      O => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0000
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor00001 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(3),
      I1 => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(4),
      O => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0000
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => wr_clk,
      D => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or0000,
      PRE => wr_rst,
      Q => full
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i : FDPE
    generic map(
      INIT => '1'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_not0001,
      D => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_almost_full_i_mux0000,
      PRE => wr_rst,
      Q => almost_full
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_wr_rst_d1 : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => wr_clk,
      D => BU2_rd_data_count(0),
      PRE => wr_rst,
      Q => BU2_U0_grf_rf_gl0_wr_gwas_wsts_wr_rst_d1_201
    );
  BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_fb_i : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => wr_clk,
      D => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or0000,
      PRE => wr_rst,
      Q => BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_fb_i_200
    );
  BU2_U0_grf_rf_mem_dout_i_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(0),
      Q => dout(0)
    );
  BU2_U0_grf_rf_mem_dout_i_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(1),
      Q => dout(1)
    );
  BU2_U0_grf_rf_mem_dout_i_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(2),
      Q => dout(2)
    );
  BU2_U0_grf_rf_mem_dout_i_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(3),
      Q => dout(3)
    );
  BU2_U0_grf_rf_mem_dout_i_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(4),
      Q => dout(4)
    );
  BU2_U0_grf_rf_mem_dout_i_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(5),
      Q => dout(5)
    );
  BU2_U0_grf_rf_mem_dout_i_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(6),
      Q => dout(6)
    );
  BU2_U0_grf_rf_mem_dout_i_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(7),
      Q => dout(7)
    );
  BU2_U0_grf_rf_mem_dout_i_8 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(8),
      Q => dout(8)
    );
  BU2_U0_grf_rf_mem_dout_i_9 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(9),
      Q => dout(9)
    );
  BU2_U0_grf_rf_mem_dout_i_10 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(10),
      Q => dout(10)
    );
  BU2_U0_grf_rf_mem_dout_i_11 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(11),
      Q => dout(11)
    );
  BU2_U0_grf_rf_mem_dout_i_12 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(12),
      Q => dout(12)
    );
  BU2_U0_grf_rf_mem_dout_i_13 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(13),
      Q => dout(13)
    );
  BU2_U0_grf_rf_mem_dout_i_14 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(14),
      Q => dout(14)
    );
  BU2_U0_grf_rf_mem_dout_i_15 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_mem_dout_i_and0000,
      D => BU2_U0_grf_rf_mem_gdm_dm_dout_i(15),
      Q => dout(15)
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM32 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(15),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM32_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N67
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM31 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(15),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM31_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N65
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM29 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(14),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM29_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N61
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM28 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(13),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM28_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N59
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM30 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(14),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM30_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N63
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM26 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(12),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM26_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N55
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM25 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(12),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM25_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N53
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM27 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(13),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM27_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N57
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM23 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(11),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM23_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N49
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM22 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(10),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM22_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N47
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM24 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(11),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM24_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N51
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM20 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(9),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM20_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N43
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM19 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(9),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM19_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N41
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM21 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(10),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM21_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N45
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM17 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(8),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM17_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N37
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM16 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(7),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM16_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N35
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM18 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(8),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM18_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N39
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM14 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(6),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM14_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N31
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM13 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(6),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM13_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N29
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM15 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(7),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM15_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N33
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM11 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(5),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM11_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N25
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM10 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(4),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM10_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N23
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM12 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(5),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM12_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N27
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM8 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(3),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM8_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N19
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM7 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(3),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM7_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N17
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM9 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(4),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM9_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N21
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM5 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(2),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM5_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N13
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM4 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(1),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N11
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM6 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(2),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM6_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N15
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM3 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(1),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N9
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM2 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(0),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl1_150,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N7
    );
  BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM1 : RAM16X1D
    port map (
      A0 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0),
      A1 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1),
      A2 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2),
      A3 => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3),
      D => din(0),
      DPRA0 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0),
      DPRA1 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1),
      DPRA2 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2),
      DPRA3 => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3),
      WCLK => wr_clk,
      WE => BU2_U0_grf_rf_mem_gdm_dm_write_ctrl_148,
      SPO => NLW_BU2_U0_grf_rf_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED,
      DPO => BU2_U0_grf_rf_mem_gdm_dm_N5
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d3_0 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(0),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(0)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d3_1 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(1),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(1)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d3_2 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(2),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(2)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d3_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(3),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(3)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d3_4 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(4),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(4)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d2_4 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(4),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(4)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d2_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(3),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(3)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d2_1 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(1),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(1)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d2_0 : FDPE
    generic map(
      INIT => '1'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(0),
      PRE => wr_rst,
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(0)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d2_2 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(2),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d2(2)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d1_4 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count(4),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(4)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d1_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count(3),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(3)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d1_1 : FDPE
    generic map(
      INIT => '1'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count(1),
      PRE => wr_rst,
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(1)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d1_0 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count(0),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(0)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_d1_2 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count(2),
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count_d1(2)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_2 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count2,
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count(2)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_0 : FDPE
    generic map(
      INIT => '1'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count,
      PRE => wr_rst,
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count(0)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_1 : FDPE
    generic map(
      INIT => '1'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count1,
      PRE => wr_rst,
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count(1)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count3,
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count(3)
    );
  BU2_U0_grf_rf_gl0_wr_wpntr_count_4 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CE => BU2_U0_grf_rf_ram_wr_en,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count4,
      Q => BU2_U0_grf_rf_gl0_wr_wpntr_count(4)
    );
  BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_next_fwft_state(0),
      Q => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(0)
    );
  BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_next_fwft_state(1),
      Q => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_curr_fwft_state(1)
    );
  BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_i : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_i_or0000,
      PRE => rd_rst,
      Q => empty
    );
  BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_fb : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_i_or0000,
      PRE => rd_rst,
      Q => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_empty_fwft_fb_118
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_d1_0 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_count(0),
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(0)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_d1_1 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_count(1),
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(1)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_d1_2 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_count(2),
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(2)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_d1_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_count(3),
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(3)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_d1_4 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_count(4),
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_2 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count2,
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count(2)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_0 : FDPE
    generic map(
      INIT => '1'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count,
      PRE => rd_rst,
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count(0)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_1 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count1,
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count(1)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count3,
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count(3)
    );
  BU2_U0_grf_rf_gl0_rd_rpntr_count_4 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CE => BU2_U0_grf_rf_gl0_rd_gr1_rfwft_Mmux_RAM_RD_EN_FWFT21_102,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count4,
      Q => BU2_U0_grf_rf_gl0_rd_rpntr_count(4)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0003,
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(0)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0002,
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(1)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0001,
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(2)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0000,
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(3)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gl0_wr_wpntr_count_d3(4),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(4)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0003,
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(0)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0002,
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(1)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0001,
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(2)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0000,
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(3)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gl0_rd_rpntr_count_d1(4),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(4)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(0),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(0)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(1),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(1)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(2),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(2)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(3),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(3)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc(4),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(4)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(0),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(0)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(1),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(1)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(2),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(2)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(3),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(3)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc(4),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(4)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(0),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(0)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(1),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(1)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(2),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(2)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(3),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(3)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1_4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg(4),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(4)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(0),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(0)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(1),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(1)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(2),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(2)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(3),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(3)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1_4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg(4),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(4)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0003_62,
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(0)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0002,
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(1)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0001,
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(2)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0000,
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(3)
    );
  BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => rd_clk,
      CLR => rd_rst,
      D => BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1(4),
      Q => BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin(4)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0003_52,
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(0)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0002,
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(1)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0001,
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(2)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0000,
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(3)
    );
  BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      C => wr_clk,
      CLR => wr_rst,
      D => BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1(4),
      Q => BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin(4)
    );
  BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i : FDP
    generic map(
      INIT => '1'
    )
    port map (
      C => rd_clk,
      D => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000,
      PRE => rd_rst,
      Q => BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_43
    );
  BU2_XST_GND : GND
    port map (
      G => BU2_rd_data_count(0)
    );

end STRUCTURE;

-- synthesis translate_on