The following files were generated for 'cg_dfifo_clk40to125' in directory 
/home/warren/slhc/hsio/coregen/

cg_dfifo_clk40to125_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

cg_dfifo_clk40to125.gise:
   ISE Project Navigator support file. This is a generated file and should
   not be edited directly.

cg_dfifo_clk40to125.ise:
   ISE Project Navigator support file. This is a generated file and should
   not be edited directly.

cg_dfifo_clk40to125.ngc:
   Binary Xilinx implementation netlist file containing the information
   required to implement the module in a Xilinx (R) FPGA.

cg_dfifo_clk40to125.vhd:
   Unisim VHDL file containing the information required to simulate
   the module.

cg_dfifo_clk40to125.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.

cg_dfifo_clk40to125.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

cg_dfifo_clk40to125.xise:
   ISE Project Navigator support file. This is a generated file and should
   not be edited directly.

cg_dfifo_clk40to125_readme.txt:
   Text file indicating the files generated and how they are used.

cg_dfifo_clk40to125_xmdf.tcl:
   ISE Project Navigator interface file. ISE uses this file to determine
   how the files output by CORE Generator for the core can be integrated
   into your ISE project.

fifo_generator_ug175.pdf:
   Please see the core data sheet.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.