-------------------------------------------------------------------------------- -- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: L.46 -- \ \ Application: netgen -- / / Filename: cg_ipfifo_1kx18.vhd -- /___/ /\ Timestamp: Wed Aug 26 17:06:19 2009 -- \ \ / \ -- \___\/\___\ -- -- Command : -intstyle ise -w -sim -ofmt vhdl /tmp/_cg/cg_ipfifo_1kx18.ngc /tmp/_cg/cg_ipfifo_1kx18.vhd -- Device : 4vfx60ff1152-11 -- Input file : /tmp/_cg/cg_ipfifo_1kx18.ngc -- Output file : /tmp/_cg/cg_ipfifo_1kx18.vhd -- # of Entities : 1 -- Design Name : cg_ipfifo_1kx18 -- Xilinx : /unix/local/xilinx/11.1/ISE -- -- Purpose: -- This VHDL netlist is a verification model and uses simulation -- primitives which may not represent the true implementation of the -- device, however the netlist is functionally correct and should not -- be modified. This file cannot be synthesized and should only be used -- with supported simulation tools. -- -- Reference: -- Command Line Tools User Guide, Chapter 23 -- Synthesis and Simulation Design Guide, Chapter 6 -- -------------------------------------------------------------------------------- -- synthesis translate_off library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; use UNISIM.VPKG.ALL; entity cg_ipfifo_1kx18 is port ( rd_en : in STD_LOGIC := 'X'; wr_en : in STD_LOGIC := 'X'; full : out STD_LOGIC; empty : out STD_LOGIC; wr_clk : in STD_LOGIC := 'X'; rst : in STD_LOGIC := 'X'; rd_clk : in STD_LOGIC := 'X'; dout : out STD_LOGIC_VECTOR ( 17 downto 0 ); din : in STD_LOGIC_VECTOR ( 17 downto 0 ) ); end cg_ipfifo_1kx18; architecture STRUCTURE of cg_ipfifo_1kx18 is signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_3_1_202 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_2_1_201 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000049_200 : STD_LOGIC; signal BU2_N8 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000049_198 : STD_LOGIC; signal BU2_N6 : STD_LOGIC; signal BU2_N4 : STD_LOGIC; signal BU2_N2 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000131_194 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000129_193 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000131_192 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000129_191 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000093_190 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_0_1_189 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000093_188 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_aflgq_or0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_186 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_and0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lwren_and0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lxfer_183 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lxfer_and0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_almostfullq_181 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_aflgq_180 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_fb_i_179 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_i_177 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_176 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lafull : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lwren_173 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_d2_172 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_d2_171 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_d1_170 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_169 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_168 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_d1_167 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_comb : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_comb : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor0001 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor0002 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor0001 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor0002 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_xor0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_xor0001 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_xor0002 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_xor0000 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_xor0001 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_xor0002 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_117 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count3 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count2 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count1 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count3 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count2 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count1 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_fb_46 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_inblk_rd_rst_fb_45 : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_inblk_rd_rst_reg_44 : STD_LOGIC; signal NLW_VCC_P_UNCONNECTED : STD_LOGIC; signal NLW_GND_G_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_ALMOSTEMPTY_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_FULL_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDERR_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRERR_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_31_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_30_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_29_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_28_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_27_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_26_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_25_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_24_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_23_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_22_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_21_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_20_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_19_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_18_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_17_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_16_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DOP_3_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DOP_2_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_11_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_10_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_9_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_8_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_7_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_6_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_5_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_4_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_3_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_2_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_1_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_0_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_11_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_10_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_9_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_8_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_7_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_6_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_5_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_4_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_3_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_2_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_1_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_0_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM18_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM17_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM16_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM15_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM14_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM13_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM11_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM10_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM12_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM9_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM8_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM7_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM6_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM5_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED : STD_LOGIC; signal NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED : STD_LOGIC; signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1 : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1 : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 1 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i : STD_LOGIC_VECTOR ( 17 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000 : STD_LOGIC_VECTOR ( 17 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 ); signal BU2_rd_data_count : STD_LOGIC_VECTOR ( 0 downto 0 ); begin VCC_0 : VCC port map ( P => NLW_VCC_P_UNCONNECTED ); GND_1 : GND port map ( G => NLW_GND_G_UNCONNECTED ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000129 : LUT4_L generic map( INIT => X"8421" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(2), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(3), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_2_1_201, I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_3_1_202, LO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000129_193 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000049 : LUT4_L generic map( INIT => X"9009" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(1), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(1), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(3), I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(3), LO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000049_200 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000129 : LUT4_L generic map( INIT => X"9009" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(3), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(3), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(2), I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(2), LO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000129_191 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000049 : LUT4_L generic map( INIT => X"9009" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(1), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(1), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(3), I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(3), LO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000049_198 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV port map ( I => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(0), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV port map ( I => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(0), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar1_INV_0 : INV port map ( I => rd_clk, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_0_1 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(0), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_0_1_189 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_2 : LUT2 generic map( INIT => X"2" ) port map ( I0 => wr_en, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_fb_i_179, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_3_1 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_3_1_202 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_2_1 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_2_1_201 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => wr_en, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_fb_i_179, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_117 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000143 : LUT4 generic map( INIT => X"FF02" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000049_200, I1 => BU2_N4, I2 => BU2_N8, I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000131_194, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000066_SW1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(2), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(2), O => BU2_N8 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000143 : LUT4 generic map( INIT => X"FF02" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000049_198, I1 => BU2_N2, I2 => BU2_N6, I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000131_192, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000066_SW1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(2), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(2), O => BU2_N6 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000066_SW0 : LUT4 generic map( INIT => X"DFFD" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_186, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_176, I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(0), I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(0), O => BU2_N4 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000066_SW0 : LUT4 generic map( INIT => X"DFFD" ) port map ( I0 => wr_en, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_fb_i_179, I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(0), I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(0), O => BU2_N2 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000131 : LUT4 generic map( INIT => X"9000" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(1), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000093_190, I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000129_193, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000131_194 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000131 : LUT4 generic map( INIT => X"9000" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(1), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(1), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000093_188, I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000129_191, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000131_192 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000093 : LUT2 generic map( INIT => X"9" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(0), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_0_1_189, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or000093_190 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000093 : LUT2 generic map( INIT => X"9" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(0), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(0), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or000093_188 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => wr_en, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_fb_i_179, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lwren_and00001 : LUT4 generic map( INIT => X"5510" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lafull, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_i_177, I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_186, I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lxfer_183, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lwren_and0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lxfer_and00001 : LUT4 generic map( INIT => X"AA20" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lafull, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_i_177, I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_186, I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lxfer_183, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lxfer_and0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_aflgq_or00001 : LUT3 generic map( INIT => X"F4" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_i_177, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_aflgq_180, I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lafull, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_aflgq_or0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_and00001 : LUT2 generic map( INIT => X"1" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_i_177, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lafull, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_and0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_ram_rd_en_i1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_186, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_176, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(3), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(0), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(1), I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(2), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count3 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(3), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(0), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(1), I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(2), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count3 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor00021 : LUT4 generic map( INIT => X"6996" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(0), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(1), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(2), I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(3), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor0002 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor00021 : LUT4 generic map( INIT => X"6996" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(0), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(1), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(2), I3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(3), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor0002 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3 generic map( INIT => X"6A" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(2), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(0), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(1), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count2 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3 generic map( INIT => X"6A" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(2), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(0), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(1), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count2 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor00011 : LUT3 generic map( INIT => X"96" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(1), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(2), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(3), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor0001 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor00011 : LUT3 generic map( INIT => X"96" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(1), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(2), I2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(3), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor0001 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_Mxor_rd_pntr_gc_xor0000_Result1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_xor0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_Mxor_rd_pntr_gc_xor0001_Result1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_xor0001 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_Mxor_rd_pntr_gc_xor0002_Result1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_xor0002 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_Mxor_wr_pntr_gc_xor0000_Result1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_xor0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_Mxor_wr_pntr_gc_xor0001_Result1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_xor0001 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_Mxor_wr_pntr_gc_xor0002_Result1 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_xor0002 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(0), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(1), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count1 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(1), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(0), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count1 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor00001 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(2), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(3), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor00001 : LUT2 generic map( INIT => X"6" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(2), I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(3), O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor0000 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_comb1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_168, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_d2_172, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_comb ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_comb1 : LUT2 generic map( INIT => X"2" ) port map ( I0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_169, I1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_d2_171, O => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_comb ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_aflgq : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_aflgq_or0000, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_aflgq_180 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden : FDC port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_and0000, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lrden_186 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lwren : FDC port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lwren_and0000, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lwren_173 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lxfer : FDC port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lxfer_and0000, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lxfer_183 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_almostfullq : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_aflgq_180, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_almostfullq_181 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_fb_i : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_fb_i_179 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_gwas_wsts_ram_full_i_or0000, Q => full ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_i : FDP generic map( INIT => '1' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000, PRE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_i_177 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i : FDP generic map( INIT => '1' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_or0000, PRE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_gras_rsts_ram_empty_fb_i_176 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i : FIFO16 generic map( ALMOST_FULL_OFFSET => X"004", DATA_WIDTH => 18, FIRST_WORD_FALL_THROUGH => FALSE, ALMOST_EMPTY_OFFSET => X"00A" ) port map ( RDCLK => rd_clk, RDEN => rd_en, RST => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47, WRCLK => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, WREN => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lwren_173, ALMOSTEMPTY => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_ALMOSTEMPTY_UNCONNECTED, ALMOSTFULL => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lafull, EMPTY => empty, FULL => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_FULL_UNCONNECTED, RDERR => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDERR_UNCONNECTED, WRERR => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRERR_UNCONNECTED, DI(31) => BU2_rd_data_count(0), DI(30) => BU2_rd_data_count(0), DI(29) => BU2_rd_data_count(0), DI(28) => BU2_rd_data_count(0), DI(27) => BU2_rd_data_count(0), DI(26) => BU2_rd_data_count(0), DI(25) => BU2_rd_data_count(0), DI(24) => BU2_rd_data_count(0), DI(23) => BU2_rd_data_count(0), DI(22) => BU2_rd_data_count(0), DI(21) => BU2_rd_data_count(0), DI(20) => BU2_rd_data_count(0), DI(19) => BU2_rd_data_count(0), DI(18) => BU2_rd_data_count(0), DI(17) => BU2_rd_data_count(0), DI(16) => BU2_rd_data_count(0), DI(15) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(15), DI(14) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(14), DI(13) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(13), DI(12) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(12), DI(11) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(11), DI(10) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(10), DI(9) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(9), DI(8) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(8), DI(7) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(7), DI(6) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(6), DI(5) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(5), DI(4) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(4), DI(3) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(3), DI(2) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(2), DI(1) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(1), DI(0) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(0), DIP(3) => BU2_rd_data_count(0), DIP(2) => BU2_rd_data_count(0), DIP(1) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(17), DIP(0) => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(16), DO(31) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_31_UNCONNECTED, DO(30) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_30_UNCONNECTED, DO(29) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_29_UNCONNECTED, DO(28) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_28_UNCONNECTED, DO(27) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_27_UNCONNECTED, DO(26) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_26_UNCONNECTED, DO(25) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_25_UNCONNECTED, DO(24) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_24_UNCONNECTED, DO(23) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_23_UNCONNECTED, DO(22) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_22_UNCONNECTED, DO(21) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_21_UNCONNECTED, DO(20) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_20_UNCONNECTED, DO(19) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_19_UNCONNECTED, DO(18) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_18_UNCONNECTED, DO(17) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_17_UNCONNECTED, DO(16) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DO_16_UNCONNECTED, DO(15) => dout(15), DO(14) => dout(14), DO(13) => dout(13), DO(12) => dout(12), DO(11) => dout(11), DO(10) => dout(10), DO(9) => dout(9), DO(8) => dout(8), DO(7) => dout(7), DO(6) => dout(6), DO(5) => dout(5), DO(4) => dout(4), DO(3) => dout(3), DO(2) => dout(2), DO(1) => dout(1), DO(0) => dout(0), DOP(3) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DOP_3_UNCONNECTED, DOP(2) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_DOP_2_UNCONNECTED, DOP(1) => dout(17), DOP(0) => dout(16), RDCOUNT(11) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_11_UNCONNECTED, RDCOUNT(10) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_10_UNCONNECTED, RDCOUNT(9) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_9_UNCONNECTED, RDCOUNT(8) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_8_UNCONNECTED, RDCOUNT(7) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_7_UNCONNECTED, RDCOUNT(6) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_6_UNCONNECTED, RDCOUNT(5) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_5_UNCONNECTED, RDCOUNT(4) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_4_UNCONNECTED, RDCOUNT(3) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_3_UNCONNECTED, RDCOUNT(2) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_2_UNCONNECTED, RDCOUNT(1) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_1_UNCONNECTED, RDCOUNT(0) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_RDCOUNT_0_UNCONNECTED, WRCOUNT(11) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_11_UNCONNECTED, WRCOUNT(10) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_10_UNCONNECTED, WRCOUNT(9) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_9_UNCONNECTED, WRCOUNT(8) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_8_UNCONNECTED, WRCOUNT(7) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_7_UNCONNECTED, WRCOUNT(6) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_6_UNCONNECTED, WRCOUNT(5) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_5_UNCONNECTED, WRCOUNT(4) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_4_UNCONNECTED, WRCOUNT(3) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_3_UNCONNECTED, WRCOUNT(2) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_2_UNCONNECTED, WRCOUNT(1) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_1_UNCONNECTED, WRCOUNT(0) => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_set_opt_fifo16_i_WRCOUNT_0_UNCONNECTED ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_d2 : FD generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_d1_167, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_d2_172 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_d2 : FD generic map( INIT => '0' ) port map ( C => wr_clk, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_d1_170, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_d2_171 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_d1 : FD generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_168, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_d1_167 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg : FDPE port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_d1_170, D => BU2_rd_data_count(0), PRE => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_169 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_d1 : FD generic map( INIT => '0' ) port map ( C => wr_clk, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_169, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_asreg_d1_170 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg : FDPE port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_d1_167, D => BU2_rd_data_count(0), PRE => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_asreg_168 ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg_2 : FDP generic map( INIT => '1' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, D => BU2_rd_data_count(0), PRE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_comb, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg_1 : FDP generic map( INIT => '1' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, D => BU2_rd_data_count(0), PRE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_comb, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg_1 : FDP generic map( INIT => '1' ) port map ( C => wr_clk, D => BU2_rd_data_count(0), PRE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_comb, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg_0 : FDP generic map( INIT => '1' ) port map ( C => wr_clk, D => BU2_rd_data_count(0), PRE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_comb, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_3 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_2 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor0000, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_1 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor0001, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_0 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin_xor0002, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_bin(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_3 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_2 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor0000, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_1 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor0001, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_0 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin_xor0002, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_bin(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1_3 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1_2 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1_1 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1_0 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg(0), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_d1(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1_3 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1_2 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1_1 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1_0 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg(0), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_d1(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_3 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_2 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_1 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg_0 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc(0), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_asreg(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_3 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_2 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_1 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg_0 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc(0), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_asreg(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_3 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_2 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_xor0000, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_1 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_xor0001, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_0 : FDC generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc_xor0002, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_rd_pntr_gc(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_3 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_2 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_xor0000, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_1 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_xor0001, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_0 : FDC generic map( INIT => '0' ) port map ( C => wr_clk, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(0), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc_xor0002, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gcx_clkx_wr_pntr_gc(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM18 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(17), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM18_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(17) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM17 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(16), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM17_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(16) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM16 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(15), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM16_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(15) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM15 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(14), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM15_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(14) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM14 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(13), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM14_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(13) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM13 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(12), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM13_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(12) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM11 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(10), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM11_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(10) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM10 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(9), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM10_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(9) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM12 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(11), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_not0001, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM12_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(11) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM9 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(8), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM9_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(8) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM8 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(7), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM8_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(7) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM7 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(6), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM7_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(6) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM6 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(5), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM6_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(5) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM5 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(4), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM5_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(4) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM4 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(3), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_117, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM4_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM2 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(1), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_117, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM2_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM1 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(0), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_117, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM1_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM3 : RAM16X1D port map ( A0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0), A1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1), A2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2), A3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3), D => din(2), DPRA0 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0), DPRA1 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1), DPRA2 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2), DPRA3 => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3), WCLK => wr_clk, WE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_117, SPO => NLW_BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_Mram_RAM3_SPO_UNCONNECTED, DPO => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_17 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(17), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(17) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_16 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(16), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(16) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_15 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(15), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(15) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_14 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(14), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(14) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_13 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(13), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(13) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_12 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(12), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(12) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_11 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(11), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(11) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_10 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(10), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(10) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_9 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(9), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(9) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_8 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(8), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(8) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_7 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(7), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(7) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_6 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(6), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(6) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_5 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(5), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(5) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_4 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(4), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(4) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_3 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_2 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_1 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i_0 : FDE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_varindex0000(0), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_mem_gdm_dm_dout_i(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_3 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count3, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_2 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count2, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_1 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count1, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_0 : FDPE generic map( INIT => '1' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_Mcount_count, PRE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_3 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_2 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_1 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1_0 : FDCE generic map( INIT => '0' ) port map ( C => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_rdclkbar, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_not0001, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_rd_rst_reg(2), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count(0), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_rd_rpntr_count_d1(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_3 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count3, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_2 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count2, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_1 : FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count1, PRE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_0 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_Mcount_count, Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1_0 : FDPE generic map( INIT => '1' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(0), PRE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(0) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1_1 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1_2 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1_3 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2_3 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(3), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(3) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2_2 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(2), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(2) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2_1 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(1), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(1) ); BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2_0 : FDCE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_ram_wr_en_i1_1_48, CLR => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_rstblk_wr_rst_reg(1), D => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d1(0), Q => BU2_U0_gbiv4_fgfifo16_patch_fblk_gen_rgtw_inst_rgtw_lut_f_gl0_wr_wpntr_count_d2(0) ); BU2_U0_gbiv4_fgfifo16_patch_inblk_rd_rst_reg : FDPE generic map( INIT => '0' ) port map ( C => rd_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_inblk_rd_rst_fb_45, D => BU2_rd_data_count(0), PRE => rst, Q => BU2_U0_gbiv4_fgfifo16_patch_inblk_rd_rst_reg_44 ); BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_fb : FDP generic map( INIT => '0' ) port map ( C => wr_clk, D => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47, PRE => rst, Q => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_fb_46 ); BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg : FDPE generic map( INIT => '0' ) port map ( C => wr_clk, CE => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_fb_46, D => BU2_rd_data_count(0), PRE => rst, Q => BU2_U0_gbiv4_fgfifo16_patch_inblk_wr_rst_reg_47 ); BU2_U0_gbiv4_fgfifo16_patch_inblk_rd_rst_fb : FDP generic map( INIT => '0' ) port map ( C => rd_clk, D => BU2_U0_gbiv4_fgfifo16_patch_inblk_rd_rst_reg_44, PRE => rst, Q => BU2_U0_gbiv4_fgfifo16_patch_inblk_rd_rst_fb_45 ); BU2_XST_GND : GND port map ( G => BU2_rd_data_count(0) ); end STRUCTURE; -- synthesis translate_on