CONFIG PART = 4vfx60ff1152-11; CONFIG STEPPING = "0"; # Accouding datasheet (ds302) version 2 = stepping 0 #NET "*clk125" TNM_NET = "CLK_125MHz"; NET "clk_xtal_125_pi" TNM_NET = "CLK_125MHz"; # 125Mhz- 7200ps!! Seems this is what xilinx do for the mac!!! TIMESPEC "TS_CLK_125MHz" = PERIOD "CLK_125MHz" 8000 ps HIGH 50 %; NET "clk_xtal_125_mi" LOC = "J17" | IOSTANDARD = LVDS_25; # 125MHz $1I155\CRYSTAL_CLK_M NET "clk_xtal_125_pi" LOC = "H17" | IOSTANDARD = LVDS_25; # 125MHz $1I155\CRYSTAL_CLK_P # NET "clk_mgtclk0a_mi" LOC = "N34" ; # 125MHz Bank 101-106 / Lane 7-0 $1I155\$1I707\$1N174 # NET "clk_mgtclk0a_pi" LOC = "M34" ; # 125MHz Bank 101-106 / Lane 7-0 $1I155\$1I707\$1N173 # NET "clk_mgtclk0b_mi" LOC = "AP28" ; # 156MHz Bank 101-106 / Lane 7-0 $1I155\$1I707\$1N117 # NET "clk_mgtclk0b_pi" LOC = "AP29" ; # 156MHz Bank 101-106 / Lane 7-0 $1I155\$1I707\$1N116 # NET "clk_mgtclk1a_mi" LOC = "AP4" ; # 125MHz Bank 109-111 / Lane 15-8 $1I155\$1I703\$1N359 # NET "clk_mgtclk1a_pi" LOC = "AP3" ; # 125MHz Bank 109-111 / Lane 15-8 $1I155\$1I703\$1N356 # NET "clk_mgtclk1b_mi" LOC = "K1" ; # 156MHz Bank 109-114 / Lane 15-8 $1I155\$1I703\$1N534 # NET "clk_mgtclk1b_pi" LOC = "J1" ; # 156MHz Bank 109-114 / Lane 15-8 $1I155\$1I703\$1N531 # NET "__" LOC = "" ; # CONF/JTAG # NET "cjt_fpga_jtag_ena_i" LOC = "G17" ; # Config and JTAG $1I155\FPGA_JTAG_ENA # NET "cjt_fpga_jtag_tck_i" LOC = "G18" ; # Config and JTAG $1I155\FPGA_JTAG_TCK # NET "cjt_fpga_jtag_tdi_i" LOC = "H14" ; # Config and JTAG $1I155\FPGA_JTAG_TDI # NET "cjt_fpga_jtag_tdo_i" LOC = "H13" ; # Config and JTAG $1I155\FPGA_JTAG_TDO # NET "cjt_fpga_jtag_tms_i" LOC = "F18" ; # Config and JTAG $1I155\FPGA_JTAG_TMS # NET "cjt_reload_fpga_fw_n_ni" LOC = "G16" ; # Config and JTAG $1I155\$1I326\~RELOAD_FPGA_FIRMWARE # NET "cjt_rev_b0_i" LOC = "F13" ; # Config and JTAG $1I155\$1I326\REV_B0 # NET "cjt_rev_b1_i" LOC = "F16" ; # Config and JTAG $1I155\$1I326\REV_B1 # NET "cjt_rev_clk_i" LOC = "G13" ; # Config and JTAG $1I155\$1I326\REV_CLK # NET "__" LOC = "" ; # CX4 # NET "cx4_lane0_mi" LOC = "A32" ; # LANE_0_RX_M # NET "cx4_lane0_pi" LOC = "A31" ; # LANE_0_RX_P # NET "cx4_lane0_mo" LOC = "E34" ; # LANE_0_TX_M # NET "cx4_lane0_po" LOC = "D34" ; # LANE_0_TX_P # NET "cx4_lane1_pi" LOC = "J34" ; # LANE_1_RX_P # NET "cx4_lane1_po" LOC = "F34" ; # LANE_1_TX_P # NET "cx4_lane1_mo" LOC = "G34" ; # LANE_1_TX_M # NET "cx4_lane1_mi" LOC = "K34" ; # LANE_1_RX_M # NET "cx4_lane2_mo" LOC = "W34" ; # LANE_2_TX_M # NET "cx4_lane2_mi" LOC = "T34" ; # LANE_2_RX_M # NET "cx4_lane2_pi" LOC = "R34" ; # LANE_2_RX_P # NET "cx4_lane2_po" LOC = "V34" ; # LANE_2_TX_P # NET "cx4_lane3_po" LOC = "Y34" ; # LANE_3_TX_P # NET "cx4_lane3_mi" LOC = "AD34" ; # LANE_3_RX_M # NET "cx4_lane3_mo" LOC = "AA34" ; # LANE_3_TX_M # NET "cx4_lane3_pi" LOC = "AC34" ; # LANE_3_RX_P # NET "cx4_lane10_mi" LOC = "AD1" ; # LANE_10_RX_M # NET "cx4_lane10_po" LOC = "AF1" ; # LANE_10_TX_P # NET "cx4_lane10_pi" LOC = "AC1" ; # LANE_10_RX_P # NET "cx4_lane10_mo" LOC = "AG1" ; # LANE_10_TX_M # NET "cx4_lane11_pi" LOC = "AL1" ; # LANE_11_RX_P # NET "cx4_lane11_mi" LOC = "AM1" ; # LANE_11_RX_M # NET "cx4_lane11_mo" LOC = "AJ1" ; # LANE_11_TX_M # NET "cx4_lane11_po" LOC = "AH1" ; # LANE_11_TX_P # NET "cx4_lane12_po" LOC = "R1" ; # LANE_12_TX_P # NET "cx4_lane12_mo" LOC = "T1" ; # LANE_12_TX_M # NET "cx4_lane12_mi" LOC = "N1" ; # LANE_12_RX_M # NET "cx4_lane12_pi" LOC = "M1" ; # LANE_12_RX_P # NET "cx4_lane13_po" LOC = "U1" ; # LANE_13_TX_P # NET "cx4_lane13_mo" LOC = "V1" ; # LANE_13_TX_M # NET "cx4_lane13_mi" LOC = "AA1" ; # LANE_13_RX_M # NET "cx4_lane13_pi" LOC = "Y1" ; # LANE_13_RX_P # NET "__" LOC = "" ; # DDR RAM # NET "ddr_addr_o(0)" LOC = "C9" ; # recheck direction $1I155\DDR_ADDR0 # NET "ddr_addr_o(1)" LOC = "D11" ; # recheck direction $1I155\DDR_ADDR1 # NET "ddr_addr_o(2)" LOC = "D12" ; # recheck direction $1I155\DDR_ADDR2 # NET "ddr_addr_o(3)" LOC = "E9" ; # recheck direction $1I155\DDR_ADDR3 # NET "ddr_addr_o(4)" LOC = "D9" ; # recheck direction $1I155\DDR_ADDR4 # NET "ddr_addr_o(5)" LOC = "E11" ; # recheck direction $1I155\DDR_ADDR5 # NET "ddr_addr_o(6)" LOC = "F11" ; # recheck direction $1I155\DDR_ADDR6 # NET "ddr_addr_o(7)" LOC = "J9" ; # recheck direction $1I155\DDR_ADDR7 # NET "ddr_addr_o(8)" LOC = "H9" ; # recheck direction $1I155\DDR_ADDR8 # NET "ddr_addr_o(9)" LOC = "F9" ; # recheck direction $1I155\DDR_ADDR9 # NET "ddr_addr_o(10)" LOC = "F10" ; # recheck direction $1I155\DDR_ADDR10 # NET "ddr_addr_o(11)" LOC = "C10" ; # recheck direction $1I155\DDR_ADDR11 # NET "ddr_addr_o(12)" LOC = "D10" ; # recheck direction $1I155\DDR_ADDR12 # NET "ddr_ba_o(0)" LOC = "H10" ; # recheck direction $1I155\DDR_BA0 # NET "ddr_ba_o(1)" LOC = "G10" ; # recheck direction $1I155\DDR_BA1 # NET "ddr_cas_mo" LOC = "K13" ; # recheck direction $1I155\~DDR_CAS # NET "ddr_ck_po" LOC = "C13" ; # recheck direction $1I155\DDR_CK # NET "ddr_ck_mo" LOC = "C12" ; # recheck direction $1I155\~DDR_CK # NET "ddr_cke_o" LOC = "E8" ; # recheck direction $1I155\DDR_CKE # NET "ddr_cs_no" LOC = "D6" ; # recheck direction $1I155\~DDR_CS # NET "ddr_dq_i(0)" LOC = "J7" ; # recheck direction $1I155\DDR_DQ0 # NET "ddr_dq_i(1)" LOC = "G11" ; # recheck direction $1I155\DDR_DQ1 # NET "ddr_dq_i(2)" LOC = "G12" ; # recheck direction $1I155\DDR_DQ2 # NET "ddr_dq_i(3)" LOC = "H8" ; # recheck direction $1I155\DDR_DQ3 # NET "ddr_dq_i(4)" LOC = "G8" ; # recheck direction $1I155\DDR_DQ4 # NET "ddr_dq_i(5)" LOC = "J10" ; # recheck direction $1I155\DDR_DQ5 # NET "ddr_dq_i(6)" LOC = "J11" ; # recheck direction $1I155\DDR_DQ6 # NET "ddr_dq_i(7)" LOC = "F8" ; # recheck direction $1I155\DDR_DQ7 # NET "ddr_dq_i(8)" LOC = "K9" ; # recheck direction $1I155\DDR_DQ8 # NET "ddr_dq_i(9)" LOC = "E12" ; # recheck direction $1I155\DDR_DQ9 # NET "ddr_dq_i(10)" LOC = "E13" ; # recheck direction $1I155\DDR_DQ10 # NET "ddr_dq_i(11)" LOC = "E6" ; # recheck direction $1I155\DDR_DQ11 # NET "ddr_dq_i(12)" LOC = "E7" ; # recheck direction $1I155\DDR_DQ12 # NET "ddr_dq_i(13)" LOC = "H12" ; # recheck direction $1I155\DDR_DQ13 # NET "ddr_dq_i(14)" LOC = "J12" ; # recheck direction $1I155\DDR_DQ14 # NET "ddr_dq_i(15)" LOC = "C8" ; # recheck direction $1I155\DDR_DQ15 # NET "ddr_ldm_o" LOC = "F6" ; # recheck direction $1I155\DDR_LDM # NET "ddr_ldqs_o" LOC = "D16" ; # recheck direction $1I155\DDR_LDQS # NET "ddr_ras_no" LOC = "C5" ; # recheck direction $1I155\~DDR_RAS # NET "ddr_udm_o" LOC = "G6" ; # recheck direction $1I155\DDR_UDM # NET "ddr_udqs_o" LOC = "D15" ; # recheck direction $1I155\DDR_UDQS # NET "ddr_we_no" LOC = "K12" ; # recheck direction $1I155\~DDR_WE # NET "__" LOC = "" ; # DISPLAY # NET "disp_clk_o" LOC = "AG22" | IOSTANDARD = LVCMOS; # DISP_CLK # NET "disp_dat_o" LOC = "AJ22" | IOSTANDARD = LVCMOS; # DISP_DAT # NET "disp_load_no(0)" LOC = "AK18" | IOSTANDARD = LVCMOS; # ~DISP_LOAD0 # NET "disp_load_no(1)" LOC = "AK17" | IOSTANDARD = LVCMOS; # ~DISP_LOAD1 # NET "disp_rst_no" LOC = "AH22" | IOSTANDARD = LVCMOS; # ~DISP_RST # NET "__" LOC = "" ; # ETHERNET INTERFACE #NET "eth_col_i" LOC = "G21" | IOSTANDARD = LVTTL; # ETH_COL NET "eth_coma_o" LOC = "E28" | IOSTANDARD = LVCMOS25; # Marvell infosheet: “Low Power Down Modes” -active high ETH_COMA NET "eth_crs_i" LOC = "F28" | IOSTANDARD = LVCMOS25; # ETH_CRS NET "eth_gtxclk_txc_o" LOC = "G25" | IOSTANDARD = LVCMOS25; # This may be same as the MAC clock input ETH_GTX_CLK #NET "eth_int_ni" LOC = "D26" | IOSTANDARD = LVTTL; # Marvell infosheet: from Management I/f (MD) active low ~ETH_INT NET "eth_mdc_o" LOC = "E26" | IOSTANDARD = LVCMOS25; # ETH_MDC NET "eth_md_io" LOC = "K21" | IOSTANDARD = LVCMOS25; # ETH_MDIO NET "eth_reset_no" LOC = "F21" | IOSTANDARD = LVCMOS25; # ~ETH_RESET NET "eth_rx_clk_rxc_i" LOC = "F20" | IOSTANDARD = LVCMOS25; # ETH_RX_CLK NET "eth_rx_dv_ctl_i" LOC = "G28" | IOSTANDARD = LVCMOS25; # ETH_RX_DV NET "eth_rx_er_i" LOC = "G27" | IOSTANDARD = LVCMOS25; # ETH_RX_ER NET "eth_rxd_i(0)" LOC = "E27" | IOSTANDARD = LVCMOS25; # ETH_RXD_0 NET "eth_rxd_i(1)" LOC = "D27" | IOSTANDARD = LVCMOS25; # ETH_RXD_1 NET "eth_rxd_i(2)" LOC = "K23" | IOSTANDARD = LVCMOS25; # ETH_RXD_2 NET "eth_rxd_i(3)" LOC = "L23" | IOSTANDARD = LVCMOS25; # ETH_RXD_3 #NET "eth_rxd_i(4)" LOC = "C28" | IOSTANDARD = LVCMOS25; # ETH_RXD_4 #NET "eth_rxd_i(5)" LOC = "C27" | IOSTANDARD = LVCMOS25; # ETH_RXD_5 #NET "eth_rxd_i(6)" LOC = "H20" | IOSTANDARD = LVCMOS25; # ETH_RXD_6 #NET "eth_rxd_i(7)" LOC = "J20" | IOSTANDARD = LVCMOS25; # ETH_RXD_7 NET "eth_tx_clk_i" LOC = "G20" | IOSTANDARD = LVCMOS25; # ETH_TX_CLK NET "eth_tx_en_ctl_o" LOC = "F26" | IOSTANDARD = LVCMOS25; # ETH_TX_EN NET "eth_tx_er_o" LOC = "J21" | IOSTANDARD = LVCMOS25; # ETH_TX_ER NET "eth_txd_o(0)" LOC = "F25" | IOSTANDARD = LVCMOS25; # ETH_TXD_0 NET "eth_txd_o(1)" LOC = "D22" | IOSTANDARD = LVCMOS25; # ETH_TXD_1 NET "eth_txd_o(2)" LOC = "E22" | IOSTANDARD = LVCMOS25; # ETH_TXD_2 NET "eth_txd_o(3)" LOC = "D25" | IOSTANDARD = LVCMOS25; # ETH_TXD_3 #NET "eth_txd_o(4)" LOC = "C25" | IOSTANDARD = LVCMOS25; # ETH_TXD_4 #NET "eth_txd_o(5)" LOC = "J22" | IOSTANDARD = LVCMOS25; # ETH_TXD_5 #NET "eth_txd_o(6)" LOC = "K22" | IOSTANDARD = LVCMOS25; # ETH_TXD_6 #NET "eth_txd_o(7)" LOC = "G26" | IOSTANDARD = LVCMOS25; # ETH_TXD_7 # NET "__" LOC = "" ; # FLASH MEM INTERFACE # NET "flash_ale_o" LOC = "AD19" ; # $1I155\FLASH_ALE # NET "flash_busy_ni" LOC = "AG16" ; # $1I155\~FLASH_BUSY # NET "flash_cle_o" LOC = "AE19" ; # $1I155\FLASH_CLE # NET "flash_cs_no" LOC = "AF20" ; # $1I155\~FLASH_CS # NET "flash_data_io(0)" LOC = "AD21" ; # $1I155\FLASH_DATA0 # NET "flash_data_io(1)" LOC = "AD20" ; # $1I155\FLASH_DATA1 # NET "flash_data_io(2)" LOC = "AF16" ; # $1I155\FLASH_DATA2 # NET "flash_data_io(3)" LOC = "AE16" ; # $1I155\FLASH_DATA3 # NET "flash_data_io(4)" LOC = "AE21" ; # $1I155\FLASH_DATA4 # NET "flash_data_io(5)" LOC = "AF21" ; # $1I155\FLASH_DATA5 # NET "flash_data_io(6)" LOC = "AE18" ; # $1I155\FLASH_DATA6 # NET "flash_data_io(7)" LOC = "AE17" ; # $1I155\FLASH_DATA7 # NET "flash_rd_ena_no" LOC = "AG17" ; # $1I155\~FLASH_RD_ENA # NET "flash_wr_ena_no" LOC = "AF19" ; # $1I155\~FLASH_WR_ENA # NET "__" LOC = "" ; # XFP INTERFACES # NET "f0_desel_i(0)" LOC = "AL4" ; # recheck direction FO_0_DESEL # NET "f0_int_i(0)" LOC = "AB8" ; # recheck direction FO_0_INT # NET "f0_mod_abs_i(0)" LOC = "AE3" ; # recheck direction FO_0_MOD_ABS # NET "f0_mod_nr_i(0)" LOC = "AE4" ; # recheck direction FO_0_MOD_NR # NET "f0_pdown_i(0)" LOC = "AJ4" ; # recheck direction FO_0_PDOWN # NET "f0_rd_mi(0)" LOC = "AG34" ; # recheck direction FO_0_RD_M # NET "f0_rd_pi(0)" LOC = "AF34" ; # recheck direction FO_0_RD_P # NET "f0_refclk_i(0)" LOC = "AH3" ; # recheck direction FO_0_REFCLK_M # NET "f0_refclk_i(0)" LOC = "AH4" ; # recheck direction FO_0_REFCLK_P # NET "f0_rx_los_i(0)" LOC = "AK3" ; # recheck direction FO_0_RX_LOS # NET "f0_scl_io(0)" LOC = "AL5" ; # recheck direction FO_0_SCL # NET "f0_sda_io(0)" LOC = "AM5" ; # recheck direction FO_0_SDA # NET "f0_td_mi(0)" LOC = "A6" ; # recheck direction FO_0_TD_M # NET "f0_td_pi(0)" LOC = "A7" ; # recheck direction FO_0_TD_P # NET "fo_tx_dis_i(0)" LOC = "AC7" ; # recheck direction FO_0_TX_DIS # NET "fo_desel_i(1)" LOC = "AB5" ; # recheck direction FO_1_DESEL # NET "fo_int_i(1)" LOC = "AC5" ; # recheck direction FO_1_INT # NET "fo_mod_abs_i(1)" LOC = "Y8" ; # recheck direction FO_1_MOD_ABS # NET "fo_mod_nr_i(1)" LOC = "W6" ; # recheck direction FO_1_MOD_NR # NET "fo_pdown_i(1)" LOC = "AA4" ; # recheck direction FO_1_PDOWN # NET "fo_rd_mi(1)" LOC = "AP31" ; # recheck direction FO_1_RD_M # NET "fo_rd_pi(1)" LOC = "AP32" ; # recheck direction FO_1_RD_P # NET "fo_refclk_mo(1)" LOC = "AA3" ; # recheck direction FO_1_REFCLK_M # NET "fo_refclk_po(1)" LOC = "AB3" ; # recheck direction FO_1_REFCLK_P # NET "fo_rx_los_i(1)" LOC = "W7" ; # recheck direction FO_1_RX_LOS # NET "fo_scl_io(1)" LOC = "Y4" ; # recheck direction FO_1_SCL # NET "fo_sda_io(1)" LOC = "Y7" ; # recheck direction FO_1_SDA # NET "fo_td_mi(1)" LOC = "G1" ; # recheck direction FO_1_TD_M # NET "fo_td_pi(1)" LOC = "F1" ; # recheck direction FO_1_TD_P # NET "fo_tx_dis_i(1)" LOC = "Y3" ; # recheck direction FO_1_TX_DIS # NET "fo_desel_i(1)" LOC = "AC4" ; # recheck direction FO_2_DESEL # NET "fo_int_i(2)" LOC = "AA8" ; # recheck direction FO_2_INT # NET "fo_mod_abs_i(2)" LOC = "AF3" ; # recheck direction FO_2_MOD_ABS # NET "fo_mod_nr_i(2)" LOC = "AG3" ; # recheck direction FO_2_MOD_NR # NET "fo_pdown_i(2)" LOC = "AA6" ; # recheck direction FO_2_PDOWN # NET "fo_rd_mo(2)" LOC = "AK34" ; # recheck direction FO_2_RD_M # NET "fo_rd_po(2)" LOC = "AJ34" ; # recheck direction FO_2_RD_P # NET "fo_refclk_mi(2)" LOC = "AB6" ; # recheck direction FO_2_REFCLK_M # NET "fo_refclk_pi(2)" LOC = "AB7" ; # recheck direction FO_2_REFCLK_P # NET "fo_rx_los_i(2)" LOC = "Y6" ; # recheck direction FO_2_RX_LOS # NET "fo_scl_io(2)" LOC = "Y9" ; # recheck direction FO_2_SCL # NET "fo_sda_io(2)" LOC = "W9" ; # recheck direction FO_2_SDA # NET "fo_td_mo(2)" LOC = "A3" ; # recheck direction FO_2_TD_M # NET "fo_td_po(2)" LOC = "A4" ; # recheck direction FO_2_TD_P # NET "fo_tx_dis_i(2)" LOC = "AA9" ; # recheck direction FO_2_TX_DIS # NET "fo_desel_i(3)" LOC = "AG6" ; # recheck direction FO_3_DESEL # NET "fo_int_i(3)" LOC = "AL6" ; # recheck direction FO_3_INT # NET "fo_mod_abs_i(3)" LOC = "AG7" ; # recheck direction FO_3_MOD_ABS # NET "fo_mod_nr_i(3)" LOC = "AG8" ; # recheck direction FO_3_MOD_NR # NET "fo_pdown_i(3)" LOC = "AM3" ; # recheck direction FO_3_PDOWN # NET "fo_rd_mo(3)" LOC = "AM34" ; # recheck direction FO_3_RD_M # NET "fo_rd_po(3)" LOC = "AL34" ; # recheck direction FO_3_RD_P # NET "fo_refclk_mi(3)" LOC = "AJ6" ; # recheck direction FO_3_REFCLK_M # NET "fo_refclk_pi(3)" LOC = "AK6" ; # recheck direction FO_3_REFCLK_P # NET "fo_rx_los_i(3)" LOC = "AL3" ; # recheck direction FO_3_RX_LOS # NET "fo_scl_io(3)" LOC = "AD6" ; # recheck direction FO_3_SCL # NET "fo_sda_io(3)" LOC = "AD7" ; # recheck direction FO_3_SDA # NET "fo_td_mo(3)" LOC = "D1" ; # recheck direction FO_3_TD_M # NET "fo_td_po(3)" LOC = "C1" ; # recheck direction FO_3_TD_P # NET "fo_tx_dis_i(3)" LOC = "AM6" ; # recheck direction FO_3_TX_DIS # NET "__" LOC = "" ; # GC_IO # NET "dunno_gc_mio(0)" LOC = "L16" ; # GC_IO_0_M # NET "dunno_gc_pio(0)" LOC = "K16" ; # GC_IO_0_P # NET "dunno_gc_mio(1)" LOC = "K17" ; # GC_IO_1_M # NET "dunno_gc_pio(1)" LOC = "K18" ; # GC_IO_1_P # NET "dunno_gc_mio(2)" LOC = "J15" ; # GC_IO_2_M # NET "dunno_gc_pio(2)" LOC = "J16" ; # GC_IO_2_P # NET "dunno_gc_mio(3)" LOC = "J19" ; # GC_IO_3_M # NET "dunno_gc_pio(3)" LOC = "K19" ; # GC_IO_3_P # NET "__" LOC = "" ; # HEX SWITCH #NET "sw_hex_i(0)" LOC = "AJ17" | IOSTANDARD = LVCMOS; # HEXSW_BIT1 #NET "sw_hex_i(1)" LOC = "AJ21" | IOSTANDARD = LVCMOS; # HEXSW_BIT0 #NET "sw_hex_i(2)" LOC = "AH17" | IOSTANDARD = LVCMOS; # HEXSW_BIT2 #NET "sw_hex_i(3)" LOC = "AG21" | IOSTANDARD = LVCMOS; # HEXSW_BIT3 # NET "__" LOC = "" ; # IDC CONNECTORS (P2-5) #NET "idc_p2_io(0)" LOC = "P11" ; # Pin 1 BANK10_IO0_P #NET "idc_p2_io(1)" LOC = "R11" ; # Pin 2 BANK10_IO0_M #NET "idc_p2_io(2)" LOC = "P10" ; # Pin 3 BANK10_IO1_P #NET "idc_p2_io(3)" LOC = "P9" ; # Pin 4 BANK10_IO1_M #NET "idc_p2_io(4)" LOC = "P7" ; # Pin 5 BANK10_IO2_P #NET "idc_p2_io(5)" LOC = "P6" ; # Pin 6 BANK10_IO2_M #NET "idc_p2_io(6)" LOC = "T6" ; # Pin 7 BANK10_IO3_P #NET "idc_p2_io(7)" LOC = "R6" ; # Pin 8 BANK10_IO3_M ## NET "idc_p2_" LOC = "" ; # Pin 9 DGND ## NET "idc_p2_" LOC = "" ; # Pin 10 DGND #NET "idc_p2_io(8)" LOC = "T5" ; # Pin 11 BANK10_IO4_P #NET "idc_p2_io(9)" LOC = "T4" ; # Pin 12 BANK10_IO4_M #NET "idc_p2_io(10)" LOC = "R4" ; # Pin 13 BANK10_IO5_P #NET "idc_p2_io(11)" LOC = "R3" ; # Pin 14 BANK10_IO5_M #NET "idc_p2_io(12)" LOC = "P5" ; # Pin 15 BANK10_IO6_P #NET "idc_p2_io(13)" LOC = "P4" ; # Pin 16 BANK10_IO6_M #NET "idc_p2_io(14)" LOC = "N5" ; # Pin 17 BANK10_IO7_P #NET "idc_p2_io(15)" LOC = "N4" ; # Pin 18 BANK10_IO7_M ## NET "idc_p2_" LOC = "" ; # Pin 19 DGND ## NET "idc_p2_" LOC = "" ; # Pin 20 DGND #NET "idc_p2_io(16)" LOC = "M8" ; # Pin 21 BANK10_IO8_P #NET "idc_p2_io(17)" LOC = "M7" ; # Pin 22 BANK10_IO8_M #NET "idc_p2_io(18)" LOC = "L9" ; # Pin 23 BANK10_IO9_P #NET "idc_p2_io(19)" LOC = "L8" ; # Pin 24 BANK10_IO9_M #NET "idc_p2_io(20)" LOC = "L10" ; # Pin 25 BANK10_IO10_P #NET "idc_p2_io(21)" LOC = "M10" ; # Pin 26 BANK10_IO10_M #NET "idc_p2_io(22)" LOC = "J5" ; # Pin 27 BANK10_IO11_P #NET "idc_p2_io(23)" LOC = "J4" ; # Pin 28 BANK10_IO11_M ## NET "idc_p2_" LOC = "" ; # Pin 29 DGND ## NET "idc_p2_" LOC = "" ; # Pin 30 DGND #NET "idc_p2_io(24)" LOC = "G3" ; # Pin 31 BANK10_IO12_P #NET "idc_p2_io(25)" LOC = "H3" ; # Pin 32 BANK10_IO12_M #NET "idc_p2_io(26)" LOC = "H5" ; # Pin 33 BANK10_IO13_P #NET "idc_p2_io(27)" LOC = "H4" ; # Pin 34 BANK10_IO13_M #NET "idc_p2_io(28)" LOC = "F4" ; # Pin 35 BANK10_IO14_P #NET "idc_p2_io(29)" LOC = "F3" ; # Pin 36 BANK10_IO14_M #NET "idc_p2_io(30)" LOC = "F5" ; # Pin 37 BANK10_IO15_P #NET "idc_p2_io(31)" LOC = "G5" ; # Pin 38 BANK10_IO15_M ## NET "idc_p2_" LOC = "" ; # Pin 39 DGND ## NET "idc_p2_" LOC = "" ; # Pin 40 DGND #NET "idc_p3_io(0)" LOC = "N10" ; # Pin 1 BANK10_IO16_P #NET "idc_p3_io(1)" LOC = "N9" ; # Pin 2 BANK10_IO16_M #NET "idc_p3_io(2)" LOC = "N8" ; # Pin 3 BANK10_IO17_P #NET "idc_p3_io(3)" LOC = "N7" ; # Pin 4 BANK10_IO17_M #NET "idc_p3_io(4)" LOC = "J6" ; # Pin 5 BANK10_IO18_P #NET "idc_p3_io(5)" LOC = "K6" ; # Pin 6 BANK10_IO18_M #NET "idc_p3_io(6)" LOC = "L6" ; # Pin 7 BANK10_IO19_P #NET "idc_p3_io(7)" LOC = "L5" ; # Pin 8 BANK10_IO19_M ## NET "idc_p3_" LOC = "" ; # Pin 9 DGND ## NET "idc_p3_" LOC = "" ; # Pin 10 DGND #NET "idc_p3_io(8)" LOC = "K4" ; # Pin 11 BANK10_IO20_P #NET "idc_p3_io(9)" LOC = "K3" ; # Pin 12 BANK10_IO20_M #NET "idc_p3_io(10)" LOC = "L4" ; # Pin 13 BANK10_IO21_P #NET "idc_p3_io(11)" LOC = "L3" ; # Pin 14 BANK10_IO21_M #NET "idc_p3_io(12)" LOC = "M6" ; # Pin 15 BANK10_IO22_P #NET "idc_p3_io(13)" LOC = "M5" ; # Pin 16 BANK10_IO22_M #NET "idc_p3_io(14)" LOC = "M3" ; # Pin 17 BANK10_IO23_P #NET "idc_p3_io(15)" LOC = "N3" ; # Pin 18 BANK10_IO23_M ## NET "idc_p3_" LOC = "" ; # Pin 19 DGND ## NET "idc_p3_" LOC = "" ; # Pin 20 DGND #NET "idc_p3_io(16)" LOC = "T11" ; # Pin 21 BANK10_IO24_P #NET "idc_p3_io(17)" LOC = "T10" ; # Pin 22 BANK10_IO24_M #NET "idc_p3_io(18)" LOC = "R8" ; # Pin 23 BANK10_IO25_P #NET "idc_p3_io(19)" LOC = "R7" ; # Pin 24 BANK10_IO25_M #NET "idc_p3_io(20)" LOC = "T9" ; # Pin 25 BANK10_IO26_P #NET "idc_p3_io(21)" LOC = "R9" ; # Pin 26 BANK10_IO26_M #NET "idc_p3_io(22)" LOC = "U3" ; # Pin 27 BANK10_IO27_P #NET "idc_p3_io(23)" LOC = "T3" ; # Pin 28 BANK10_IO27_M ## NET "idc_p3_" LOC = "" ; # Pin 29 DGND ## NET "idc_p3_" LOC = "" ; # Pin 30 DGND #NET "idc_p3_io(24)" LOC = "U7" ; # Pin 31 BANK10_IO28_P #NET "idc_p3_io(25)" LOC = "U6" ; # Pin 32 BANK10_IO28_M #NET "idc_p3_io(26)" LOC = "V4" ; # Pin 33 BANK10_IO29_P #NET "idc_p3_io(27)" LOC = "V3" ; # Pin 34 BANK10_IO29_M #NET "idc_p3_io(28)" LOC = "V5" ; # Pin 35 BANK10_IO30_P #NET "idc_p3_io(29)" LOC = "U5" ; # Pin 36 BANK10_IO30_M #NET "idc_p3_io(30)" LOC = "U8" ; # Pin 37 BANK10_IO31_P #NET "idc_p3_io(31)" LOC = "T8" ; # Pin 38 BANK10_IO31_M ## NET "idc_p3_" LOC = "" ; # Pin 39 DGND ## NET "idc_p3_" LOC = "" ; # Pin 40 DGND #NET "idc_p4_io(0)" LOC = "AG32" ; # Pin 1 BANK11_IO0_P #NET "idc_p4_io(1)" LOC = "AH32" ; # Pin 2 BANK11_IO0_M #NET "idc_p4_io(2)" LOC = "W25" ; # Pin 3 BANK11_IO1_P #NET "idc_p4_io(3)" LOC = "W24" ; # Pin 4 BANK11_IO1_M #NET "idc_p4_io(4)" LOC = "AA26" ; # Pin 5 BANK11_IO2_P #NET "idc_p4_io(5)" LOC = "AA25" ; # Pin 6 BANK11_IO2_M #NET "idc_p4_io(6)" LOC = "W26" ; # Pin 7 BANK11_IO3_P #NET "idc_p4_io(7)" LOC = "Y26" ; # Pin 8 BANK11_IO3_M ## NET "idc_p4_" LOC = "" ; # Pin 9 DGND ## NET "idc_p4_" LOC = "" ; # Pin 10 DGND #NET "idc_p4_io(8)" LOC = "W27" ; # Pin 11 BANK11_IO4_P #NET "idc_p4_io(9)" LOC = "V27" ; # Pin 12 BANK11_IO4_M #NET "idc_p4_io(10)" LOC = "U32" ; # Pin 13 BANK11_IO5_P #NET "idc_p4_io(11)" LOC = "U31" ; # Pin 14 BANK11_IO5_M #NET "idc_p4_io(12)" LOC = "V30" ; # Pin 15 BANK11_IO6_P #NET "idc_p4_io(13)" LOC = "U30" ; # Pin 16 BANK11_IO6_M #NET "idc_p4_io(14)" LOC = "V29" ; # Pin 17 BANK11_IO7_P #NET "idc_p4_io(15)" LOC = "V28" ; # Pin 18 BANK11_IO7_M ## NET "idc_p4_" LOC = "" ; # Pin 19 DGND ## NET "idc_p4_" LOC = "" ; # Pin 20 DGND #NET "idc_p4_io(16)" LOC = "W32" ; # Pin 21 BANK11_IO8_P #NET "idc_p4_io(17)" LOC = "V32" ; # Pin 22 BANK11_IO8_M #NET "idc_p4_io(18)" LOC = "Y29" ; # Pin 23 BANK11_IO9_P #NET "idc_p4_io(19)" LOC = "W29" ; # Pin 24 BANK11_IO9_M #NET "idc_p4_io(20)" LOC = "AB26" ; # Pin 25 BANK11_IO10_P #NET "idc_p4_io(21)" LOC = "AB25" ; # Pin 26 BANK11_IO10_M #NET "idc_p4_io(22)" LOC = "AB28" ; # Pin 27 BANK11_IO11_P #NET "idc_p4_io(23)" LOC = "AB27" ; # Pin 28 BANK11_IO11_M ## NET "idc_p4_" LOC = "" ; # Pin 29 DGND ## NET "idc_p4_" LOC = "" ; # Pin 30 DGND #NET "idc_p4_io(24)" LOC = "AC28" ; # Pin 31 BANK11_IO12_P #NET "idc_p4_io(25)" LOC = "AC27" ; # Pin 32 BANK11_IO12_M #NET "idc_p4_io(26)" LOC = "AC30" ; # Pin 33 BANK11_IO13_P #NET "idc_p4_io(27)" LOC = "AC29" ; # Pin 34 BANK11_IO13_M #NET "idc_p4_io(28)" LOC = "AD32" ; # Pin 35 BANK11_IO14_P #NET "idc_p4_io(29)" LOC = "AD31" ; # Pin 36 BANK11_IO14_M #NET "idc_p4_io(30)" LOC = "AD30" ; # Pin 37 BANK11_IO15_P #NET "idc_p4_io(31)" LOC = "AD29" ; # Pin 38 BANK11_IO15_M ## NET "idc_p4_" LOC = "" ; # Pin 39 DGND ## NET "idc_p4_" LOC = "" ; # Pin 40 DGND ## NET "idc_p5_io(0)" LOC = "Y24" ; # Pin 1 BANK11_IO16_P ## NET "idc_p5_io(1)" LOC = "AA24" ; # Pin 2 BANK11_IO16_M ## NET "idc_p5_io(2)" LOC = "AC25" ; # Pin 3 BANK11_IO17_P ## NET "idc_p5_io(3)" LOC = "AD25" ; # Pin 4 BANK11_IO17_M ## NET "idc_p5_io(4)" LOC = "Y28" ; # Pin 5 BANK11_IO18_P ## NET "idc_p5_io(5)" LOC = "Y27" ; # Pin 6 BANK11_IO18_M ## NET "idc_p5_io(6)" LOC = "AA29" ; # Pin 7 BANK11_IO19_P ## NET "idc_p5_io(7)" LOC = "AA28" ; # Pin 8 BANK11_IO19_M ## NET "idc_p5_" LOC = "" ; # Pin 9 DGND ## NET "idc_p5_" LOC = "" ; # Pin 10 DGND ## NET "idc_p5_io(8)" LOC = "W31" ; # Pin 11 BANK11_IO20_P ## NET "idc_p5_io(9)" LOC = "W30" ; # Pin 12 BANK11_IO20_M ## NET "idc_p5_io(10)" LOC = "Y32" ; # Pin 13 BANK11_IO21_P ## NET "idc_p5_io(11)" LOC = "Y31" ; # Pin 14 BANK11_IO21_M ## NET "idc_p5_io(12)" LOC = "AA31" ; # Pin 15 BANK11_IO22_P ## NET "idc_p5_io(13)" LOC = "AA30" ; # Pin 16 BANK11_IO22_M ## NET "idc_p5_io(14)" LOC = "AB31" ; # Pin 17 BANK11_IO23_P ## NET "idc_p5_io(15)" LOC = "AB30" ; # Pin 18 BANK11_IO23_M ## NET "idc_p5_" LOC = "" ; # Pin 19 DGND ## NET "idc_p5_" LOC = "" ; # Pin 20 DGND ## NET "idc_p5_io(16)" LOC = "AB32" ; # Pin 21 BANK11_IO24_P ## NET "idc_p5_io(17)" LOC = "AC32" ; # Pin 22 BANK11_IO24_M ## NET "idc_p5_io(18)" LOC = "AD27" ; # Pin 23 BANK11_IO25_P ## NET "idc_p5_io(19)" LOC = "AD26" ; # Pin 24 BANK11_IO25_M ## NET "idc_p5_io(20)" LOC = "AE29" ; # Pin 25 BANK11_IO26_P ## NET "idc_p5_io(21)" LOC = "AF29" ; # Pin 26 BANK11_IO26_M ## NET "idc_p5_io(22)" LOC = "AE32" ; # Pin 27 BANK11_IO27_P ## NET "idc_p5_io(23)" LOC = "AE31" ; # Pin 28 BANK11_IO27_M ## NET "idc_p5_" LOC = "" ; # Pin 29 DGND ## NET "idc_p5_" LOC = "" ; # Pin 30 DGND ## NET "idc_p5_io(24)" LOC = "AF31" ; # Pin 31 BANK11_IO28_P ## NET "idc_p5_io(25)" LOC = "AF30" ; # Pin 32 BANK11_IO28_M ## NET "idc_p5_io(26)" LOC = "AG31" ; # Pin 33 BANK11_IO29_P ## NET "idc_p5_io(27)" LOC = "AG30" ; # Pin 34 BANK11_IO29_M ## NET "idc_p5_io(28)" LOC = "AH30" ; # Pin 35 BANK11_IO30_P ## NET "idc_p5_io(29)" LOC = "AJ30" ; # Pin 36 BANK11_IO30_M ## NET "idc_p5_io(30)" LOC = "AJ32" ; # Pin 37 BANK11_IO31_P ## NET "idc_p5_io(31)" LOC = "AJ31" ; # Pin 38 BANK11_IO31_M ## NET "idc_p5_" LOC = "" ; # Pin 39 DGND ## NET "idc_p5_" LOC = "" ; # Pin 40 DGND # NET "__" LOC = "" ; # MISC CONNS – EEPROM ID1WIRE LED RESET # NET "eeprom_cs_o" LOC = "H19" ; # $1I155\$1I326\$1N1133 # NET "eeprom_d_i" LOC = "L15" ; # $1I155\$1I326\$1N1137 # NET "eeprom_d_o" LOC = "L14" ; # $1I155\$1I326\$1N1139 # NET "eeprom_sk_o" LOC = "H18" ; # $1I155\$1I326\$1N1135 # NET "id_1wire_io" LOC = "AH18" ; # $1I155\$1I326\$1N1121 NET "led_status_o" LOC = "K14" ; # FPGA_STATUS NET "rst_poweron_ni" LOC = "AJ19" ; # $1I155\$1I326\$1N909 # NET "__" LOC = "" ; # USB INTERFACE # NET "usb_d_io(0)" LOC = "AK32" | IOSTANDARD = LVCMOS33 | PULLDOWN; # USB_D0 # NET "usb_d_io(1)" LOC = "AK31" | IOSTANDARD = LVCMOS33 | PULLDOWN; # USB_D1 # NET "usb_d_io(2)" LOC = "AL19" | IOSTANDARD = LVCMOS33 | PULLDOWN; # USB_D2 # NET "usb_d_io(3)" LOC = "AL18" | IOSTANDARD = LVCMOS33 | PULLDOWN; # USB_D3 # NET "usb_d_io(4)" LOC = "AM32" | IOSTANDARD = LVCMOS33 | PULLDOWN; # USB_D4 # NET "usb_d_io(5)" LOC = "AM31" | IOSTANDARD = LVCMOS33 | PULLDOWN; # USB_D5 # NET "usb_d_io(6)" LOC = "AC23" | IOSTANDARD = LVCMOS33 | PULLDOWN; # USB_D6 # NET "usb_d_io(7)" LOC = "AC22" | IOSTANDARD = LVCMOS33 | PULLDOWN; # USB_D7 # NET "usb_rd_o" LOC = "AL31" | IOSTANDARD = LVCMOS33; # ~USB_RD # NET "usb_rxf_ni" LOC = "AL20" | IOSTANDARD = LVCMOS33; # check dir ~USB_RXF # NET "usb_txe_ni" LOC = "AM20" | IOSTANDARD = LVCMOS33; # check dir ~USB_TXE # NET "usb_wr_o" LOC = "AL30" | IOSTANDARD = LVCMOS33; # USB_WR # NET "__" LOC = "" ; # ZONE3 (ATCA) CONNECTOR # NET "z3_gpio_io(0)" LOC = "AG28" ; # J25.A3 GPIO_0 # NET "z3_gpio_io(1)" LOC = "AG26" ; # J25.B3 GPIO_1 # NET "z3_gpio_io(2)" LOC = "AH29" ; # J25.C3 GPIO_2 # NET "z3_gpio_io(3)" LOC = "AE28" ; # J25.D3 GPIO_3 # NET "z3_gpio_io(4)" LOC = "AH27" ; # J25.E3 GPIO_4 # NET "z3_gpio_io(5)" LOC = "AH28" ; # J25.F3 GPIO_5 # NET "z3_gpio_io(6)" LOC = "AG27" ; # J25.G3 GPIO_6 # NET "z3_gpio_io(7)" LOC = "AF26" ; # J25.H3 GPIO_7 # NET "z3_gpio_io(8)" LOC = "AJ29" ; # J25.A4 GPIO_8 # NET "z3_gpio_io(9)" LOC = "AK29" ; # J25.B4 GPIO_9 # NET "z3_gpio_io(10)" LOC = "AK28" ; # J25.C4 GPIO_10 # NET "z3_gpio_io(11)" LOC = "AK27" ; # J25.D4 GPIO_11 # NET "z3_gpio_io(12)" LOC = "AE27" ; # J25.E4 GPIO_12 # NET "z3_gpio_io(13)" LOC = "AE23" ; # J25.F4 GPIO_13 # NET "z3_gpio_io(14)" LOC = "AF23" ; # J25.G4 GPIO_14 # NET "z3_gpio_io(15)" LOC = "AF28" ; # J25.H4 GPIO_15 # NET "z3_gpio_io(16)" LOC = "AK26" ; # J25.A5 GPIO_16 # NET "z3_gpio_io(17)" LOC = "AL25" ; # J25.B5 GPIO_17 # NET "z3_gpio_io(18)" LOC = "AK24" ; # J25.C5 GPIO_18 # NET "z3_gpio_io(19)" LOC = "AK23" ; # J25.D5 GPIO_19 # NET "z3_gpio_io(20)" LOC = "AJ27" ; # J25.E5 GPIO_20 # NET "z3_gpio_io(21)" LOC = "AL26" ; # J25.F5 GPIO_21 # NET "z3_gpio_io(22)" LOC = "AM30" ; # J25.G5 GPIO_22 # NET "z3_gpio_io(23)" LOC = "AL29" ; # J25.H5 GPIO_23 # NET "z3_gpio_io(24)" LOC = "AJ25" ; # J25.A6 GPIO_24 # NET "z3_gpio_io(25)" LOC = "AK21" ; # J25.B6 GPIO_25 # NET "z3_gpio_io(26)" LOC = "AE22" ; # J25.C6 GPIO_26 # NET "z3_gpio_io(27)" LOC = "AD22" ; # J25.D6 GPIO_27 # NET "z3_gpio_io(28)" LOC = "AL28" ; # J25.E6 GPIO_28 # NET "z3_gpio_io(29)" LOC = "AM28" ; # J25.F6 GPIO_29 # NET "z3_gpio_io(30)" LOC = "AM27" ; # J25.G6 GPIO_30 # NET "z3_gpio_io(31)" LOC = "AM26" ; # J25.H6 GPIO_31 # NET "z3_gpio_io(32)" LOC = "AD24" ; # J25.A7 GPIO_32 # NET "z3_gpio_io(33)" LOC = "AJ24" ; # J25.B7 GPIO_33 # NET "z3_gpio_io(34)" LOC = "AF24" ; # J25.C7 GPIO_34 # NET "z3_gpio_io(35)" LOC = "AG23" ; # J25.D7 GPIO_35 # NET "z3_gpio_io(36)" LOC = "AM25" ; # J25.E7 GPIO_36 # NET "z3_gpio_io(37)" LOC = "AL24" ; # J25.F7 GPIO_37 # NET "z3_gpio_io(38)" LOC = "AM23" ; # J25.G7 GPIO_38 # NET "z3_gpio_io(39)" LOC = "AM22" ; # J25.H7 GPIO_39 # NET "z3_gpio_io(40)" LOC = "AE24" ; # J25.A8 GPIO_40 # NET "z3_gpio_io(41)" LOC = "AG25" ; # J25.B8 GPIO_41 # NET "z3_gpio_io(42)" LOC = "AH24" ; # J25.C8 GPIO_42 # NET "z3_gpio_io(43)" LOC = "AH25" ; # J25.D8 GPIO_43 # NET "z3_gpio_io(44)" LOC = "AM21" ; # J25.E8 GPIO_44 # NET "z3_gpio_io(45)" LOC = "AL23" ; # J25.F8 GPIO_45 # NET "z3_gpio_io(46)" LOC = "AL21" ; # J25.G8 GPIO_46 # NET "z3_gpio_io(47)" LOC = "AJ26" ; # J25.H8 GPIO_47 # NET "z3_gpio_io(48)" LOC = "AH23" ; # J25.A9 GPIO_48 # NET "z3_gpio_io(49)" LOC = "AK22" ; # J25.B9 GPIO_49 # NET "z3_j26_lvds_pio(0)" LOC = "AM13" ; # J26.A1 J26_LVDS_0_P # NET "z3_j26_lvds_mio(0)" LOC = "AM12" ; # J26.B1 J26_LVDS_0_M # NET "z3_j26_lvds_pio(1)" LOC = "AM8" ; # J26.C1 J26_LVDS_1_P # NET "z3_j26_lvds_mio(1)" LOC = "AM7" ; # J26.D1 J26_LVDS_1_M # NET "z3_j26_lvds_pio(2)" LOC = "AK14" ; # J26.E1 J26_LVDS_2_P # NET "z3_j26_lvds_mio(2)" LOC = "AL14" ; # J26.F1 J26_LVDS_2_M # NET "z3_j26_lvds_pio(3)" LOC = "AK13" ; # J26.G1 J26_LVDS_3_P # NET "z3_j26_lvds_mio(3)" LOC = "AL13" ; # J26.H1 J26_LVDS_3_M # NET "z3_j26_lvds_mio(4)" LOC = "AM11" ; # J26.B2 J26_LVDS_4_M # NET "z3_j26_lvds_pio(4)" LOC = "AL11" ; # J26.A2 J26_LVDS_4_P # NET "z3_j26_lvds_pio(5)" LOC = "AL9" ; # J26.C2 J26_LVDS_5_P # NET "z3_j26_lvds_mio(5)" LOC = "AK9" ; # J26.D2 J26_LVDS_5_M # NET "z3_j26_lvds_pio(6)" LOC = "AL10" ; # J26.E2 J26_LVDS_6_P # NET "z3_j26_lvds_mio(6)" LOC = "AM10" ; # J26.F2 J26_LVDS_6_M # NET "z3_j26_lvds_mio(7)" LOC = "AK8" ; # J26.H2 J26_LVDS_7_M # NET "z3_j26_lvds_pio(7)" LOC = "AL8" ; # J26.G2 J26_LVDS_7_P # NET "z3_j26_lvds_mio(8)" LOC = "AJ7" ; # J26.B3 J26_LVDS_8_M # NET "z3_j26_lvds_pio(8)" LOC = "AK7" ; # J26.A3 J26_LVDS_8_P # NET "z3_j26_lvds_pio(9)" LOC = "AJ9" ; # J26.C3 J26_LVDS_9_P # NET "z3_j26_lvds_mio(9)" LOC = "AH9" ; # J26.D3 J26_LVDS_9_M # NET "z3_j26_lvds_mio(10)" LOC = "AK11" ; # J26.F3 J26_LVDS_10_M # NET "z3_j26_lvds_pio(10)" LOC = "AJ11" ; # J26.E3 J26_LVDS_10_P # NET "z3_j26_lvds_pio(11)" LOC = "AH8" ; # J26.G3 J26_LVDS_11_P # NET "z3_j26_lvds_mio(11)" LOC = "AH7" ; # J26.H3 J26_LVDS_11_M # NET "z3_j26_lvds_pio(12)" LOC = "AJ12" ; # J26.A4 J26_LVDS_12_P # NET "z3_j26_lvds_mio(12)" LOC = "AK12" ; # J26.B4 J26_LVDS_12_M # NET "z3_j26_lvds_pio(13)" LOC = "AH10" ; # J26.C4 J26_LVDS_13_P # NET "z3_j26_lvds_mio(13)" LOC = "AJ10" ; # J26.D4 J26_LVDS_13_M # NET "z3_j26_lvds_pio(14)" LOC = "AH14" ; # J26.E4 J26_LVDS_14_P # NET "z3_j26_lvds_mio(14)" LOC = "AJ14" ; # J26.F4 J26_LVDS_14_M # NET "z3_j26_lvds_mio(15)" LOC = "AG10" ; # J26.H4 J26_LVDS_15_M # NET "z3_j26_lvds_pio(15)" LOC = "AF10" ; # J26.G4 J26_LVDS_15_P # NET "z3_j26_lvds_mio(16)" LOC = "AE12" ; # J26.B5 J26_LVDS_16_M # NET "z3_j26_lvds_pio(16)" LOC = "AD12" ; # J26.A5 J26_LVDS_16_P # NET "z3_j26_lvds_mio(17)" LOC = "AH12" ; # J26.D5 J26_LVDS_17_M # NET "z3_j26_lvds_pio(17)" LOC = "AG12" ; # J26.C5 J26_LVDS_17_P # NET "z3_j26_lvds_mio(18)" LOC = "AE9" ; # J26.F5 J26_LVDS_18_M # NET "z3_j26_lvds_pio(18)" LOC = "AF9" ; # J26.E5 J26_LVDS_18_P # NET "z3_j26_lvds_mio(19)" LOC = "AG11" ; # J26.H5 J26_LVDS_19_M # NET "z3_j26_lvds_pio(19)" LOC = "AF11" ; # J26.G5 J26_LVDS_19_P # NET "z3_j26_lvds_pio(20)" LOC = "AC12" ; # J26.A6 J26_LVDS_20_P # NET "z3_j26_lvds_mio(20)" LOC = "AB12" ; # J26.B6 J26_LVDS_20_M # NET "z3_j26_lvds_pio(21)" LOC = "AG13" ; # J26.C6 J26_LVDS_21_P # NET "z3_j26_lvds_mio(21)" LOC = "AH13" ; # J26.D6 J26_LVDS_21_M # NET "z3_j26_lvds_pio(22)" LOC = "AD11" ; # J26.E6 J26_LVDS_22_P # NET "z3_j26_lvds_mio(22)" LOC = "AE11" ; # J26.F6 J26_LVDS_22_M # NET "z3_j26_lvds_mio(23)" LOC = "AD9" ; # J26.H6 J26_LVDS_23_M # NET "z3_j26_lvds_pio(23)" LOC = "AD10" ; # J26.G6 J26_LVDS_23_P # NET "z3_j26_lvds_mio(24)" LOC = "AF14" ; # J26.B7 J26_LVDS_24_M # NET "z3_j26_lvds_pio(24)" LOC = "AE14" ; # J26.A7 J26_LVDS_24_P # NET "z3_j26_lvds_pio(25)" LOC = "AB11" ; # J26.C7 J26_LVDS_25_P # NET "z3_j26_lvds_mio(25)" LOC = "AA11" ; # J26.D7 J26_LVDS_25_M # NET "z3_j26_lvds_pio(26)" LOC = "AD14" ; # J26.E7 J26_LVDS_26_P # NET "z3_j26_lvds_mio(26)" LOC = "AC13" ; # J26.F7 J26_LVDS_26_M # NET "z3_j26_lvds_mio(27)" LOC = "AA13" ; # J26.H7 J26_LVDS_27_M # NET "z3_j26_lvds_pio(27)" LOC = "AB13" ; # J26.G7 J26_LVDS_27_P # NET "z3_j26_lvds_mio(28)" LOC = "AJ15" ; # J26.B8 J26_LVDS_28_M # NET "z3_j26_lvds_pio(28)" LOC = "AH15" ; # J26.A8 J26_LVDS_28_P # NET "z3_j26_lvds_pio(29)" LOC = "AF15" ; # J26.C8 J26_LVDS_29_P # NET "z3_j26_lvds_mio(29)" LOC = "AG15" ; # J26.D8 J26_LVDS_29_M # NET "z3_j26_lvds_pio(30)" LOC = "AE13" ; # J26.E8 J26_LVDS_30_P # NET "z3_j26_lvds_mio(30)" LOC = "AF13" ; # J26.F8 J26_LVDS_30_M # NET "z3_j26_lvds_mio(31)" LOC = "AK16" ; # J26.H8 J26_LVDS_31_M # NET "z3_j26_lvds_pio(31)" LOC = "AJ16" ; # J26.G8 J26_LVDS_31_P # NET "z3_j26_lvds_mio(32)" LOC = "J24" ; # J26.B9 J26_LVDS_32_M # NET "z3_j26_lvds_pio(32)" LOC = "H24" ; # J26.A9 J26_LVDS_32_P # NET "z3_j26_lvds_pio(33)" LOC = "G22" ; # J26.C9 J26_LVDS_33_P # NET "z3_j26_lvds_mio(33)" LOC = "H22" ; # J26.D9 J26_LVDS_33_M # NET "z3_j26_lvds_mio(34)" LOC = "F24" ; # J26.F9 J26_LVDS_34_M # NET "z3_j26_lvds_pio(34)" LOC = "E24" ; # J26.E9 J26_LVDS_34_P # NET "z3_j26_lvds_pio(35)" LOC = "J25" ; # J26.G9 J26_LVDS_35_P # NET "z3_j26_lvds_mio(35)" LOC = "H25" ; # J26.H9 J26_LVDS_35_M # NET "z3_j26_lvds_mio(36)" LOC = "D24" ; # J26.B10 J26_LVDS_36_M # NET "z3_j26_lvds_pio(36)" LOC = "C24" ; # J26.A10 J26_LVDS_36_P # NET "z3_j26_lvds_pio(37)" LOC = "C23" ; # J26.C10 J26_LVDS_37_P # NET "z3_j26_lvds_mio(37)" LOC = "C22" ; # J26.D10 J26_LVDS_37_M # NET "z3_j26_lvds_mio(38)" LOC = "H23" ; # J26.F10 J26_LVDS_38_M # NET "z3_j26_lvds_pio(38)" LOC = "G23" ; # J26.E10 J26_LVDS_38_P # NET "z3_j26_lvds_mio(39)" LOC = "F23" ; # J26.H10 J26_LVDS_39_M # NET "z3_j26_lvds_pio(39)" LOC = "E23" ; # J26.G10 J26_LVDS_39_P # NET "z3_j27_lvds_pio(0)" LOC = "K26" ; # J27.A1 J27_LVDS_0_P # NET "z3_j27_lvds_mio(0)" LOC = "J26" ; # J27.B1 J27_LVDS_0_M # NET "z3_j27_lvds_pio(1)" LOC = "D21" ; # J27.C1 J27_LVDS_1_P # NET "z3_j27_lvds_mio(1)" LOC = "E21" ; # J27.D1 J27_LVDS_1_M # NET "z3_j27_lvds_mio(2)" LOC = "N22" ; # J27.F1 J27_LVDS_2_M # NET "z3_j27_lvds_pio(2)" LOC = "P22" ; # J27.E1 J27_LVDS_2_P # NET "z3_j27_lvds_mio(3)" LOC = "F19" ; # J27.H1 J27_LVDS_3_M # NET "z3_j27_lvds_pio(3)" LOC = "E19" ; # J27.G1 J27_LVDS_3_P # NET "z3_j27_lvds_pio(4)" LOC = "L21" ; # J27.A2 J27_LVDS_4_P # NET "z3_j27_lvds_mio(4)" LOC = "M22" ; # J27.B2 J27_LVDS_4_M # NET "z3_j27_lvds_mio(5)" LOC = "L25" ; # J27.D2 J27_LVDS_5_M # NET "z3_j27_lvds_pio(5)" LOC = "L26" ; # J27.C2 J27_LVDS_5_P # NET "z3_j27_lvds_pio(6)" LOC = "P24" ; # J27.E2 J27_LVDS_6_P # NET "z3_j27_lvds_mio(6)" LOC = "N24" ; # J27.F2 J27_LVDS_6_M # NET "z3_j27_lvds_pio(7)" LOC = "K24" ; # J27.G2 J27_LVDS_7_P # NET "z3_j27_lvds_mio(7)" LOC = "L24" ; # J27.H2 J27_LVDS_7_M # NET "z3_j27_lvds_pio(8)" LOC = "D30" ; # J27.A3 J27_LVDS_8_P # NET "z3_j27_lvds_mio(8)" LOC = "C30" ; # J27.B3 J27_LVDS_8_M # NET "z3_j27_lvds_pio(9)" LOC = "D29" ; # J27.C3 J27_LVDS_9_P # NET "z3_j27_lvds_mio(9)" LOC = "C29" ; # J27.D3 J27_LVDS_9_M # NET "z3_j27_lvds_pio(10)" LOC = "P27" ; # J27.E3 J27_LVDS_10_P # NET "z3_j27_lvds_mio(10)" LOC = "P26" ; # J27.F3 J27_LVDS_10_M # NET "z3_j27_lvds_pio(11)" LOC = "M26" ; # J27.G3 J27_LVDS_11_P # NET "z3_j27_lvds_mio(11)" LOC = "M25" ; # J27.H3 J27_LVDS_11_M # NET "z3_j27_lvds_pio(12)" LOC = "D32" ; # J27.A4 J27_LVDS_12_P # NET "z3_j27_lvds_mio(12)" LOC = "C32" ; # J27.B4 J27_LVDS_12_M # NET "z3_j27_lvds_mio(13)" LOC = "D31" ; # J27.D4 J27_LVDS_13_M # NET "z3_j27_lvds_pio(13)" LOC = "E31" ; # J27.C4 J27_LVDS_13_P # NET "z3_j27_lvds_mio(14)" LOC = "E29" ; # J27.F4 J27_LVDS_14_M # NET "z3_j27_lvds_pio(14)" LOC = "F29" ; # J27.E4 J27_LVDS_14_P # NET "z3_j27_lvds_mio(15)" LOC = "H27" ; # J27.H4 J27_LVDS_15_M # NET "z3_j27_lvds_pio(15)" LOC = "H28" ; # J27.G4 J27_LVDS_15_P # NET "z3_j27_lvds_mio(16)" LOC = "F30" ; # J27.B5 J27_LVDS_16_M # NET "z3_j27_lvds_pio(16)" LOC = "G30" ; # J27.A5 J27_LVDS_16_P # NET "z3_j27_lvds_mio(17)" LOC = "H29" ; # J27.D5 J27_LVDS_17_M # NET "z3_j27_lvds_pio(17)" LOC = "H30" ; # J27.C5 J27_LVDS_17_P # NET "z3_j27_lvds_pio(18)" LOC = "J31" ; # J27.E5 J27_LVDS_18_P # NET "z3_j27_lvds_mio(18)" LOC = "J30" ; # J27.F5 J27_LVDS_18_M # NET "z3_j27_lvds_mio(19)" LOC = "J27" ; # J27.H5 J27_LVDS_19_M # NET "z3_j27_lvds_pio(19)" LOC = "K28" ; # J27.G5 J27_LVDS_19_P # NET "z3_j27_lvds_pio(20)" LOC = "K29" ; # J27.A6 J27_LVDS_20_P # NET "z3_j27_lvds_mio(20)" LOC = "J29" ; # J27.B6 J27_LVDS_20_M # NET "z3_j27_lvds_pio(21)" LOC = "J32" ; # J27.C6 J27_LVDS_21_P # NET "z3_j27_lvds_mio(21)" LOC = "H32" ; # J27.D6 J27_LVDS_21_M # NET "z3_j27_lvds_mio(22)" LOC = "G31" ; # J27.F6 J27_LVDS_22_M # NET "z3_j27_lvds_pio(22)" LOC = "G32" ; # J27.E6 J27_LVDS_22_P # NET "z3_j27_lvds_mio(23)" LOC = "F31" ; # J27.H6 J27_LVDS_23_M # NET "z3_j27_lvds_pio(23)" LOC = "E32" ; # J27.G6 J27_LVDS_23_P # NET "z3_j27_lvds_pio(24)" LOC = "M32" ; # J27.A7 J27_LVDS_24_P # NET "z3_j27_lvds_mio(24)" LOC = "M31" ; # J27.B7 J27_LVDS_24_M # NET "z3_j27_lvds_pio(25)" LOC = "L31" ; # J27.C7 J27_LVDS_25_P # NET "z3_j27_lvds_mio(25)" LOC = "L30" ; # J27.D7 J27_LVDS_25_M # NET "z3_j27_lvds_pio(26)" LOC = "N27" ; # J27.E7 J27_LVDS_26_P # NET "z3_j27_lvds_mio(26)" LOC = "M28" ; # J27.F7 J27_LVDS_26_M # NET "z3_j27_lvds_mio(27)" LOC = "K31" ; # J27.H7 J27_LVDS_27_M # NET "z3_j27_lvds_pio(27)" LOC = "K32" ; # J27.G7 J27_LVDS_27_P # NET "z3_j27_lvds_mio(28)" LOC = "N32" ; # J27.B8 J27_LVDS_28_M # NET "z3_j27_lvds_pio(28)" LOC = "P32" ; # J27.A8 J27_LVDS_28_P # NET "z3_j27_lvds_pio(29)" LOC = "N30" ; # J27.C8 J27_LVDS_29_P # NET "z3_j27_lvds_mio(29)" LOC = "M30" ; # J27.D8 J27_LVDS_29_M # NET "z3_j27_lvds_pio(30)" LOC = "P31" ; # J27.E8 J27_LVDS_30_P # NET "z3_j27_lvds_mio(30)" LOC = "P30" ; # J27.F8 J27_LVDS_30_M # NET "z3_j27_lvds_mio(31)" LOC = "N28" ; # J27.H8 J27_LVDS_31_M # NET "z3_j27_lvds_pio(31)" LOC = "N29" ; # J27.G8 J27_LVDS_31_P # NET "z3_j27_lvds_pio(32)" LOC = "R32" ; # J27.A9 J27_LVDS_32_P # NET "z3_j27_lvds_mio(32)" LOC = "R31" ; # J27.B9 J27_LVDS_32_M # NET "z3_j27_lvds_mio(33)" LOC = "L28" ; # J27.D9 J27_LVDS_33_M # NET "z3_j27_lvds_pio(33)" LOC = "L29" ; # J27.C9 J27_LVDS_33_P # NET "z3_j27_lvds_pio(34)" LOC = "R28" ; # J27.E9 J27_LVDS_34_P # NET "z3_j27_lvds_mio(34)" LOC = "R27" ; # J27.F9 J27_LVDS_34_M # NET "z3_j27_lvds_mio(35)" LOC = "P29" ; # J27.H9 J27_LVDS_35_M # NET "z3_j27_lvds_pio(35)" LOC = "R29" ; # J27.G9 J27_LVDS_35_P # NET "z3_j27_lvds_mio(36)" LOC = "T28" ; # J27.B10 J27_LVDS_36_M # NET "z3_j27_lvds_pio(36)" LOC = "T29" ; # J27.A10 J27_LVDS_36_P # NET "z3_j27_lvds_pio(37)" LOC = "T31" ; # J27.C10 J27_LVDS_37_P # NET "z3_j27_lvds_mio(37)" LOC = "T30" ; # J27.D10 J27_LVDS_37_M # NET "z3_j27_lvds_pio(38)" LOC = "U28" ; # J27.E10 J27_LVDS_38_P # NET "z3_j27_lvds_mio(38)" LOC = "U27" ; # J27.F10 J27_LVDS_38_M # NET "z3_j27_lvds_pio(39)" LOC = "T26" ; # J27.G10 J27_LVDS_39_P # NET "z3_j27_lvds_mio(39)" LOC = "R26" ; # J27.H10 J27_LVDS_39_M # NET "z3_mgt106a_mo" LOC = "AP22" ; # LANE6_TX_M # NET "z3_mgt106a_pi" LOC = "AP26" ; # LANE6_RX_P # NET "z3_mgt106a_po" LOC = "AP23" ; # LANE6_TX_P # NET "z3_mgt106a_mi" LOC = "AP25" ; # LANE6_RX_M # NET "z3_mgt106b_pi" LOC = "AP18" ; # LANE7_RX_P # NET "z3_mgt106b_mo" LOC = "AP20" ; # LANE7_TX_M # NET "z3_mgt106b_mi" LOC = "AP17" ; # LANE7_RX_M # NET "z3_mgt106b_po" LOC = "AP21" ; # LANE7_TX_P # NET "z3_mgt109a_pi" LOC = "AP6" ; # LANE16_RX_P # NET "z3_mgt109a_mi" LOC = "AP7" ; # LANE16_RX_M # NET "z3_mgt109a_mo" LOC = "AP10" ; # LANE16_TX_M # NET "z3_mgt109a_po" LOC = "AP9" ; # LANE16_TX_P # NET "z3_mgt109b_pi" LOC = "AP14" ; # LANE17_RX_P # NET "z3_mgt109b_mi" LOC = "AP15" ; # LANE17_RX_M # NET "z3_mgt109b_mo" LOC = "AP12" ; # LANE17_TX_M # NET "z3_mgt109b_po" LOC = "AP11" ; # LANE17_TX_P ################################################### # Below from MII core ##################################################### #CONFIG PART = 4vfx60ff672-10; NET "*tx_gmii_mii_clk_in_0_i" TNM_NET = "clk_phy_tx_clk0"; TIMESPEC "TS_phy_tx_clk0" = PERIOD "clk_phy_tx_clk0" 7400 ps HIGH 50 %; NET "*tx_client_clk_in_0_i" TNM_NET = "clk_client_tx_clk0"; TIMESPEC "TS_client_tx_clk0" = PERIOD "clk_client_tx_clk0" 7200 ps HIGH 50 %; NET "*rx_client_clk_in_0_i" TNM_NET = "clk_client_rx_clk0"; TIMESPEC "TS_client_rx_clk0" = PERIOD "clk_client_rx_clk0" 7200 ps HIGH 50 %; NET "*mii_rx_clk_0_i" TNM_NET = "clk_phy_rx_clk0"; TIMESPEC "TS_phy_rx_clk0" = PERIOD "clk_phy_rx_clk0" 7200 ps HIGH 50 %; #NET "*host_clk_i" TNM_NET = "host_clock"; #TIMEGRP "clk_host" = "host_clock"; #TIMESPEC "TS_clk_host" = PERIOD "clk_host" 10000 ps HIGH 50 %; # Locate EMAC instance for timing closure #***INST "*v4_emac" LOC = "EMAC_X0Y0"; INST "*v4_emac" LOC = "EMAC_X0Y1"; #################### EMAC 0 MII Constraints ######################## INST "*mii0?RXD_TO_MAC*" IOB = true; INST "*mii0?RX_DV_TO_MAC" IOB = true; INST "*mii0?RX_ER_TO_MAC" IOB = true; INST "eth_txd_o" TNM = "sig_mii_tx_0"; INST "eth_tx_en_ctl_o" TNM = "sig_mii_tx_0"; INST "eth_tx_er_o" TNM = "sig_mii_tx_0"; INST "eth_rxd_i" TNM = "sig_mii_rx_0"; INST "eth_rx_dv_ctl_i" TNM = "sig_mii_rx_0"; INST "eth_rx_er_i" TNM = "sig_mii_rx_0"; # using recommended budget from the clause 22 #***TIMEGRP "sig_mii_rx_0" OFFSET = IN 10 ns VALID 20 ns BEFORE "mii_rx_clk_0"; #***TIMEGRP "sig_mii_tx_0" OFFSET = OUT 15 ns AFTER "mii_tx_clk_0"; TIMEGRP "sig_mii_rx_0" OFFSET = IN 10 ns VALID 20 ns BEFORE "eth_rx_clk_rxc_i"; TIMEGRP "sig_mii_tx_0" OFFSET = OUT 15 ns AFTER "eth_tx_clk_i"; # Give the host bus a 10ns setup, 10ns hold window to lower skew. Recommended only. #INST "HOSTADDR" TNM = "host_in_addr"; #INST "HOSTWRDATA" TNM = "host_in_wrdata"; #INST "HOSTRDDATA" TNM = "host_out"; #TIMEGRP "host_in_addr" OFFSET = IN 10 ns VALID 20 ns BEFORE "HOSTCLK"; #TIMEGRP "host_in_wrdata" OFFSET = IN 10 ns VALID 20 ns BEFORE "HOSTCLK"; # Remove the following constraints if example design FIFOs are not used # These constraints cover any clock domain crossing for metastability. # Tx client FIFO: #INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable"; #INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_tog" TNM = "tx_metastable"; #INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_1" TNM = "tx_stable"; #INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_sync" TNM = "tx_stable"; # #INST "*tx_fifo_i?wr_tran_frame_tog" TNM = "tx_metastable"; #INST "*tx_fifo_i?frame_in_fifo_sync" TNM = "tx_metastable"; #INST "*tx_fifo_i?wr_txfer_tog" TNM = "tx_metastable"; #INST "*tx_fifo_i?wr_rd_addr*" TNM = "tx_metastable"; # #INST "*tx_fifo_i?wr_tran_frame_sync" TNM = "tx_stable"; #INST "*tx_fifo_i?frame_in_fifo" TNM = "tx_stable"; #INST "*tx_fifo_i?wr_txfer_tog_sync" TNM = "tx_stable"; #INST "*tx_fifo_i?wr_addr_diff*" TNM = "tx_stable"; # #TIMESPEC "TS_tx_meta_protect" = FROM "tx_metastable" TO "tx_stable" 5 ns; # ## Rx client FIFO: # #INST "*rx_fifo_i?rd_store_frame_tog" TNM = "rx_metastable"; #INST "*rx_fifo_i?wr_rd_addr_gray_sync*" TNM = "rx_metastable"; # #INST "*rx_fifo_i?rd_store_frame_sync" TNM = "rx_stable"; #INST "*rx_fifo_i?wr_rd_addr_gray*" TNM = "rx_stable"; # #TIMESPEC "TS_rx_meta_protect" = FROM "rx_metastable" TO "rx_stable" 5 ns; #*** ISE says: #ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock # IOB site. The clock IOB component is placed at site . # The clock IO site can use the fast path between the IO and the Clock # buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub # optimal condition is acceptable for this design, you may use the # CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a # WARNING and allow your design to continue. However, the use of this override # is highly discouraged as it may lead to very poor timing results. It is # recommended that this error condition be corrected in the design. A list of # all the COMP.PINs used in this clock placement rule is listed below. These # examples can be used directly in the .ucf file to override this clock rule. # < NET "eth_rx_clk_rxc_i" CLOCK_DEDICATED_ROUTE = FALSE; > NET "eth_rx_clk_rxc_i" CLOCK_DEDICATED_ROUTE = FALSE; NET "eth_tx_clk_i" CLOCK_DEDICATED_ROUTE = FALSE;