--
-- Parameter Block
--
-- Stores values read and written by the param opcode
-- May need to be adapted for block read/writes too
--
-- Ideally this will operate using global constants to define the register address,
-- but that is a project for another day
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity param_block is
  port(
    wr_i         : in  std_logic;
    rd_i         : in  std_logic;
    addr_i       : in    std_logic_vector (15 downto 0);
    data_i         : in  std_logic_vector (15 downto 0);
    data_o         : out  std_logic_vector (15 downto 0);

    param_test_o : out   std_logic_vector (15 downto 0);
    param_mode_o : out   std_logic_vector (15 downto 0);
    param_stream_en_o : out   std_logic_vector (15 downto 0);
    
    clk            : in  std_logic;
    rst            : in  std_logic
    );

-- Declarations

end param_block;


architecture rtl of param_block is

  constant ADDR_BITS: integer := 2;
  constant PARAMS_MAX : integer := 3; -- 2^ADDR_BITS-1;

                                    
  signal param_list : slv16_array(PARAMS_MAX downto 0);
  
  signal address : integer range 0 to PARAMS_MAX;
  
begin

  param_test_o <= param_list(0);
  param_mode_o <= param_list(1);
  param_stream_en_o <= param_list(2);

  address <= conv_integer(addr_i); 
--                          (ADDR_BITS-1 downto 0));


  prc_param_reg : process (clk)
  begin
    if rising_edge(clk) then
      if (rst = '1') then
        param_list <= (others => "0000000000000000");
      else
        if (wr_i = '1') then 
          param_list(conv_integer(address)) <= data_i;
        end if;

        if (rd_i = '1') then
          data_o <=  param_list(conv_integer(address));
        end if;
       
      end if;
    end if;

  end process;

end architecture;