-- VHDL Entity hsio.readout_demux.symbol
--
-- Created:
--          by - Matt Warren
--          at - 15:26:57 04/15/10
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1b (Build 7)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity readout_demux is
   port( 
      clk    : in     std_logic;
      clkn   : in     std_ulogic;
      delay0 : in     std_logic_vector (1 downto 0);
      delay1 : in     std_logic_vector (1 downto 0);
      ido_i  : in     std_logic;
      rst    : in     std_logic;
      idodq0 : out    std_logic;
      idodq1 : out    std_logic
   );

-- Declarations

end readout_demux ;

--
-- VHDL Architecture hsio.readout_demux.struct
--
-- Created:
--          by - Matt Warren
--          at - 15:26:57 04/15/10
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1b (Build 7)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


architecture struct of readout_demux is

   -- Architecture declarations

   -- Internal signal declarations
   signal idod0 : std_logic;
   signal idod1 : std_logic;


   -- Component Declarations
   component gate_delay4
   port (
      d : in     std_logic_vector (1 downto 0);
      i : in     std_logic ;
      o : out    std_logic 
   );
   end component;
   component m_dff
   port (
      c : in     std_logic;
      d : in     std_logic;
      r : in     std_logic;
      q : out    std_logic
   );
   end component;


begin

   -- Instance port mappings.
   Ugatedelay0 : gate_delay4
      port map (
         d => delay0,
         i => ido_i,
         o => idod0
      );
   Ugatedelay1 : gate_delay4
      port map (
         d => delay1,
         i => ido_i,
         o => idod1
      );
   U_5 : m_dff
      port map (
         r => rst,
         c => clk,
         d => idod0,
         q => idodq0
      );
   U_10 : m_dff
      port map (
         r => rst,
         c => clkn,
         d => idod1,
         q => idodq1
      );

end struct;