-- VHDL Entity hsio.xilinx_reset.symbol
--
-- Created:
--          by - Matt Warren
--          at - 15:26:51 04/15/10
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1b (Build 7)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity xilinx_reset is
   port( 
      clk      : in     std_ulogic;
      locked   : in     std_logic;
      por      : in     std_ulogic;
      reset_no : out    std_ulogic;
      reset_o  : out    std_ulogic
   );

-- Declarations

end xilinx_reset ;

--
-- VHDL Architecture hsio.xilinx_reset.struct
--
-- Created:
--          by - Matt Warren
--          at - 15:26:51 04/15/10
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1b (Build 7)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


architecture struct of xilinx_reset is

   -- Architecture declarations

   -- Internal signal declarations
   signal lo       : std_ulogic;
   signal locked_n : std_logic;
   signal r0       : std_ulogic;
   signal r1       : std_ulogic;
   signal r2       : std_ulogic;
   signal r3       : std_ulogic;

   -- Implicit buffer signal declarations
   signal reset_o_internal : std_ulogic;


   -- Component Declarations
   component FD
   generic (
      INIT : bit := '0'
   );
   port (
      C : in     std_ulogic;
      D : in     std_ulogic;
      Q : out    std_ulogic
   );
   end component;
   component FDS
   generic (
      INIT : bit := '1'
   );
   port (
      C : in     std_ulogic;
      D : in     std_ulogic;
      S : in     std_ulogic;
      Q : out    std_ulogic
   );
   end component;


begin

   -- ModuleWare code(v1.9) for instance 'Ulo' of 'gnd'
   lo <= '0';

   -- ModuleWare code(v1.9) for instance 'U_0' of 'inv'
   reset_no <= not(reset_o_internal);

   -- ModuleWare code(v1.9) for instance 'U_3' of 'inv'
   locked_n <= not(locked);

   -- ModuleWare code(v1.9) for instance 'U_2' of 'or'
   reset_o_internal <= r1 or r2 or r3 or locked_n;

   -- Instance port mappings.
   Ufd0 : FD
      generic map (
         INIT => '0'
      )
      port map (
         Q => r1,
         C => clk,
         D => r0
      );
   Ufd1 : FD
      generic map (
         INIT => '0'
      )
      port map (
         Q => r2,
         C => clk,
         D => r1
      );
   Ufd2 : FD
      generic map (
         INIT => '0'
      )
      port map (
         Q => r3,
         C => clk,
         D => r2
      );
   Ufds : FDS
      generic map (
         INIT => '1'
      )
      port map (
         Q => r0,
         C => clk,
         D => por,
         S => lo
      );

   -- Implicit buffered output assignments
   reset_o <= reset_o_internal;

end struct;