library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rstDebounce is

generic(holdTicks : integer :=20000000);

port(
   resetIn  : in std_logic;
   clock    : in std_logic;
   resetOut : out std_logic
      );

end rstDebounce;

architecture Behavioral of rstDebounce is

signal hold, hold_next		: integer range 0 to holdTicks :=holdTicks;
signal reset, reset_next	: std_logic := '1';

begin

process(clock,resetIn)
begin
if(resetIn = '1') then
   hold <= holdTicks-1;
   reset <= '1';
elsif(clock'event AND clock='1') then
   hold <= hold_next;
   reset <= reset_next;
end if;
end process;
resetOut <= reset;

process(hold)
begin
if(hold>0) then
   hold_next <= hold-1;
   reset_next <= '1';
else 
   hold_next <= 0;
   reset_next <= '0';
end if;
end process;

end Behavioral;