-- VHDL Entity lib.led_mux_pulse.symbol
--
-- Created:
--          by - Matt Warren
--          at - 11:14:16 03/08/10
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1b (Build 7)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY led_mux_pulse IS
   PORT( 
      clk : IN     std_logic;
      i0  : IN     std_logic;
      i1  : IN     std_logic;
      rst : IN     std_logic;
      sel : IN     std_logic;
      o   : OUT    std_logic
   );

-- Declarations

END led_mux_pulse ;

--
-- VHDL Architecture lib.led_mux_pulse.struct
--
-- Created:
--          by - Matt Warren
--          at - 11:14:16 03/08/10
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2008.1b (Build 7)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


ARCHITECTURE struct OF led_mux_pulse IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL i : std_logic;


   -- Component Declarations
   COMPONENT led_pulse
   PORT (
      clk : IN     std_logic ;
      i   : IN     std_logic ;
      rst : IN     std_logic ;
      o   : OUT    std_logic 
   );
   END COMPONENT;


BEGIN

   -- ModuleWare code(v1.9) for instance 'U_1' of 'mux'
   prcu_1combo: PROCESS(i0, i1, sel)
   BEGIN
      CASE sel IS
      WHEN '0'|'L' => i <= i0;
      WHEN '1'|'H' => i <= i1;
      WHEN OTHERS => i <= 'X';
      END CASE;
   END PROCESS prcu_1combo;

   -- Instance port mappings.
   Ulpmp : led_pulse
      PORT MAP (
         clk => clk,
         i   => i,
         rst => rst,
         o   => o
      );

END struct;