HELIX Driver User Guide [very very very under dev.]

Introduction

The HELIX Driver is part of the ZEUS MVD Clock and Control (C+C) system, where it is predominantly used to fan-out C+C signals to HELIX inside the detector.

The signals are sent via a patch-box (PB) locate next to the detector, using LVDS differential signals.

Clocks can be delayed in .5ns steps to fix timing skews due to physical detector layout on a module by module basis.

The HELIX Driver (HD) also provides the signalling and serialisation of command strings sent to the HELIX modules ('Serial Data Mode').

Various diagnostic and read-back systems are also built into the HD to help with system debug and monitoring.

Custom Backplane

To correct voltage offsets required by this custom system (and ensure signal voltage swings around zero, the HD requires 2 auxiliary supplies:

a) -5V -- for level shifting the TTL voltages

b) +3.8 -> -1.2V (offset 5V supply) for the LVDS drivers.

These voltages are supplied via a D15 connector at the back of the crate wired to spare pins on the VME backplane (J2 connector)

Input/Output

Each HD supports 15 Helix Modules. The HD supplies: Clock, Trigger/Serial_Data, Serial_Load, Not_Reset and Test signals (See table below). All of these signals are derived from a single front-panel input, except for Serial_Load, which is generated automatically by the HD during a program cycle. If for some reason the clock is absent these signals will revert to known conditions for HELIX module safety.

HELIX Driver Output Signal Definition
	Name	Description	At-Reset/ No-Clock
	CLOCK	Input clock is fanned out via 15 programmable delays	Unknown
	TRIG/SD	Trigger/Serial_Data /pld_clock and fanned-out to 15 outputs. During Serial_Data_Mode it provides the serial programming data.	0
	NRESET	Not_Reset Gated by Serial_Data_Mode select, clocked by /pld_clock and fanned out to 15 outputs. A direct feed of the input Not_Reset, except during Serial_Data_Mode, when it is held in reset for the duration on the serial programming cycle.	1
	TESTPULSE	Test_Pulse Fanned-out via channel by channel by channel enable register Test_Pulse_Mask_Reg), NOT clocked!	Unchanged, but Mask is set to 1 (enabled)

Clock Delays and Adjustments

Operation

The board has a power-on reset.

It can also be reset with a VME command.

To program serial data:

1) Change to Serial_Program_Mode, by issuing a Serial_Program_Mode_Set command.

2) Load the Data Register with the serial data (remember the top 4 bits indicate channel 0 to 14)

3) Issue the Start_Program_Cycle command.

At this point the Serial_Program_Busy flag will be set (in the Status Register) and should be polled for a zero before loading further data into the Data Register.

Serial Programming Cycle:

This data is transmitted after:

- Serial_Program_Mode is/has been set, and the Start_Serial_Program_Cycle command is issued.

During the Serial Program Cycle the following happens:

- Busy goes high (asynchronously) with the reception of 'Start_Serial_Program_Mode' command.

- At the next negative clock edge the Not_Reset signal is pulled low (holding the HELIX Module in program mode).

- The start command is synced to the clock, and a maximum of 2 clock cycles

later, the programming cycle starts, on the negative edge of the clock

- 20 clocks later the data is complete

- for the 21st clock period the relevant Serial_Load_Pulse (as specified by bits 20-23 of the Data_Reg) is set high.

- This action is registered in the Serial_Load_Sent_Reg for the relevant channel.

- On the 23rd clock the control of Not_Reset is released (neg edge)

HELIX Driver Address Map Summery
Registers
	ID	Offset		Name	Size (bits)	R/W	Special	Reset State
	0	00h		Data	24	RW	-	0
	1	04h		Feedback0	4	R	-	0
	2	08h		Feedback1	8	R	-	0
	3	0Ch		Feedback2	8	R	-	0
	4	10h		Status	5	R	W=rst	8h*
	5	14h		Trigger Counter	8	R	-	0
	6	18h		TestPulse Mask	15	RW	-	0
	7	1Ch		SerialLoad Sent	15	R	W=rst
Commands (activate with a Read)
	8	20h	Serial Program Mode Set		-	R	-
	9	24h	Start Serial Program Cycle		-	R	-
	10	28h	Test Trigger		-	R	-
	11	2Ch	Trigger (Normal) Mode Set		-	R	-	Default*
	12	30h	Unused		-	-	-
	13	34h	Unused		-	-	-
	14	38h	Unused		-	-	-
	15	3Ch	Reset Board		-	R	-
Programmable Delays
	16	40h	Delay Ch 0		8	W	R**	0
	17	44h	Delay Ch 1		8	W	R**	0
	18	48h	Delay Ch 2		8	W	R**	0
	19	4Ch	Delay Ch 3		8	W	R**	0
	20	50h	Delay Ch 4		8	W	R**	0
	21	54h	Delay Ch 5		8	W	R**	0
	22	58h	Delay Ch 6		8	W	R**	0
	23	5Ch	Delay Ch 7		8	W	R**	0
	24	60h	Delay Ch 8		8	W	R**	0
	25	64h	Delay Ch 9		8	W	R**	0
	26	68h	Delay Ch 10		8	W	R**	0
	27	6Ch	Delay Ch 11		8	W	R**	0
	28	70h	Delay Ch 12		8	W	R**	0
	29	74h	Delay Ch 13		8	W	R**	0
	30	78h	Delay Ch 14		8	W	R**	0
	31	7Ch	Delay Ch 0-14 (all)		8	W	R**	0

* At reset the HD is set to Trigger_Mode

** Reading of Delay Units is done 1 bit at a time (LSB first in DB0), and MUST be done for all 8 bits of the Delay Unit to maintain the delay setting. This is because the Delay Unit actually shifts the data out serially, and it is fed back to the input, and needs to be shifted all the way back to its original position.

Register Details

Data: 0x00

Load this register with data to be programmed to the HELIX Modules. The data organised with the top 4 bits indicating channel and the lower 20 the data.

	Channel	Data
binary	0000	00000000000000000000

Channel 15 (1111b) is used as a broadcast mode to program all HELIX Modules connected to that 'Driver.

Feedback(2,1,0): 0x04,0x08,0x0C

The feedback registers contain the result of a serial download, without channel info. It is physically connected to the trigger/serial_data line and is a good test of HD download operation.

It holds the bits as they were sent in 4, 8, 8 bit sections:

Feedback2 = msNibble,

Feedback1 = midByte

Feedback0 = lsByte,).

Status Register: 0x10

Returns the status of the system. Is held zero during a reset.

Status Bits
0	Serial Download Busy
1	Test Sent (1 = yes)
2	Trigger Sent (1 = yes)
3	Mode (Serial/nTrig)
4	Clock On

Trigger Counter: 0x14

This is an 8bit (255) counter for counting triggers. Reset by a Write.

Test Pulse Mask: 0x18

This register masks (enables) the Test_Pulse for each channel.

1 = Test_Pulse enabled.

Serial Load Sent: 0x1C

Bit set to 1 if that particular channel has issued a SerialLoad pulse. Reset by a Write.