Proton Calorimetry/Meetings/2020/05/27

From PBTWiki

(Difference between revisions)
Jump to: navigation, search
(Created page with "== Minutes for UCL Proton Calorimetry Meetings, 27th May (Everyone is working from home) == === Present === '''Simon Jolly''','''Laurent Kelleter''', '''Saad Shaikh''', '''Raf...")
(Saad Shaikh)
Line 9: Line 9:
=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
-
 
+
*Read and gave feedback on chapters 6-8 of Laurent's thesis.
 +
**Will read remaining chapters over the week.
 +
*Continuing with learning FPGA programming (slow progress):
 +
**Tested 'WM controller' code given by Matt Warren, unsure if working, will contact him again.
 +
**Udemy course lectures not that helpful so far, but now onto lab exercises which might be better.
 +
**Found some Vivado-related training material on [https://www.xilinx.com/support/university/vivado/vivado-teaching-material.html Xilinx University Program], will work through this.
 +
**No response (yet) from Electrical Engineering about accessing course material.
 +
*Discussion about taking on MSci student to work on FPGA communication with computer
 +
**Could be done in parallel with work in communication between FPGA and ADC.
 +
**Hypothetical discussion, continue work as is but might be worth discussing feasibility of loading fitting procedures onto FPGA with Matt.
 +
**On a similar note, need to ask Matt about High-Level Synthesis, which appears to offer framework for C/C++ code to be translated to HDL.
=== [[ELogs/LaurentKelleter|Laurent Kelleter]] ===
=== [[ELogs/LaurentKelleter|Laurent Kelleter]] ===

Revision as of 14:30, 27 May 2020

Contents

Minutes for UCL Proton Calorimetry Meetings, 27th May (Everyone is working from home)

Present

Simon Jolly,Laurent Kelleter, Saad Shaikh, Raffaella radogna

Raffaella Radogna

Saad Shaikh

  • Read and gave feedback on chapters 6-8 of Laurent's thesis.
    • Will read remaining chapters over the week.
  • Continuing with learning FPGA programming (slow progress):
    • Tested 'WM controller' code given by Matt Warren, unsure if working, will contact him again.
    • Udemy course lectures not that helpful so far, but now onto lab exercises which might be better.
    • Found some Vivado-related training material on Xilinx University Program, will work through this.
    • No response (yet) from Electrical Engineering about accessing course material.
  • Discussion about taking on MSci student to work on FPGA communication with computer
    • Could be done in parallel with work in communication between FPGA and ADC.
    • Hypothetical discussion, continue work as is but might be worth discussing feasibility of loading fitting procedures onto FPGA with Matt.
    • On a similar note, need to ask Matt about High-Level Synthesis, which appears to offer framework for C/C++ code to be translated to HDL.

Laurent Kelleter

Personal tools