Proton Calorimetry/Meetings/2020/06/03: Difference between revisions
(Created page with "== Minutes for UCL Proton Calorimetry Meetings, 3rd June (Everyone is working from home) == === Present === '''Simon Jolly''','''Laurent Kelleter''', '''Saad Shaikh''', '''Raf...") |
SaadShaikh (talk | contribs) |
||
| Line 9: | Line 9: | ||
=== [[ELogs/SaadShaikh|Saad Shaikh]] === | === [[ELogs/SaadShaikh|Saad Shaikh]] === | ||
*Finished reading and giving feedback on Laurent's thesis. | |||
*Tested He and C fitting using GSI DDDs as reference. | |||
**Can't say much about quality of fitting and Bragg curve reconstruction as GSI data uses a ripple filter and has different energy steps to HIT. Need to compare with actual HIT FLUKA simulation. | |||
*Finished Udemy online course on FPGA programming. | |||
**Some useful introductory exercises using basic I/O on Zybo board beyond "Hello World" Blinky exercise. | |||
**Will move onto Xilinx University Programme material to continue training. | |||
*Front-end boards have been made by CosyLab! | |||
**Will analyse datasheet for TI DDC232 to understand I/O signals and present report on timeline for operation. | |||
*Need to get serial interface working to send commands from computer to FPGA. | |||
**Have downloaded Tera Term terminal emulator, will find example code to get it working. | |||
**Need to buy USB-UART converter expansion module for Zybo Z7 to communicate with FPGA without having to go through on-board processor. | |||
*Will start going through example Verilog code for DDC264EVM FPGA serial interface. | |||
=== [[ELogs/LaurentKelleter|Laurent Kelleter]] === | === [[ELogs/LaurentKelleter|Laurent Kelleter]] === | ||
Revision as of 08:59, 4 June 2020
Minutes for UCL Proton Calorimetry Meetings, 3rd June (Everyone is working from home)
Present
Simon Jolly,Laurent Kelleter, Saad Shaikh, Raffaella radogna
Raffaella Radogna
Saad Shaikh
- Finished reading and giving feedback on Laurent's thesis.
- Tested He and C fitting using GSI DDDs as reference.
- Can't say much about quality of fitting and Bragg curve reconstruction as GSI data uses a ripple filter and has different energy steps to HIT. Need to compare with actual HIT FLUKA simulation.
- Finished Udemy online course on FPGA programming.
- Some useful introductory exercises using basic I/O on Zybo board beyond "Hello World" Blinky exercise.
- Will move onto Xilinx University Programme material to continue training.
- Front-end boards have been made by CosyLab!
- Will analyse datasheet for TI DDC232 to understand I/O signals and present report on timeline for operation.
- Need to get serial interface working to send commands from computer to FPGA.
- Have downloaded Tera Term terminal emulator, will find example code to get it working.
- Need to buy USB-UART converter expansion module for Zybo Z7 to communicate with FPGA without having to go through on-board processor.
- Will start going through example Verilog code for DDC264EVM FPGA serial interface.