Proton Calorimetry/Meetings/2020/06/17: Difference between revisions
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* Provided comments for Laurent's chapter 9, chapter 2, Abstract, and Introduction. | * Provided comments for Laurent's chapter 9, chapter 2, Abstract, and Introduction. | ||
* Started reading about FPGA programming and digital circuit | * Started reading about FPGA programming and digital circuit | ||
** [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/2019_Book_IntroductionToDigitalSystemsDe.pdf Introduction To Digital Systems] | ** [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/2019_Book_IntroductionToDigitalSystemsDe.pdf Introduction To Digital Systems Design] | ||
** [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/2019_Book_IntroductionToLogicCircuitsLog.pdf Introduction to Logic Circuits & Logic Designwith Verilog] | |||
** [http://www.hep.ucl.ac.uk/pbt/wikiData/teaching/FPGA_books/2019_Book_QuickStartGuideToVerilog.pdf Quick StartGuide to Verilog] | |||
* Will finalise a first draft of her project proposal for fellowships | * Will finalise a first draft of her project proposal for fellowships | ||
Revision as of 10:01, 24 June 2020
Minutes for UCL Proton Calorimetry Meetings, 17th June (Everyone is working from home)
Present
Simon Jolly, Laurent Kelleter, Saad Shaikh, Raffaella Radogna
Raffaella Radogna
- Installed Xilinx - Vivado Design Suite on Windows
- Matt Warren generated the license key
- Provided comments for Laurent's chapter 9, chapter 2, Abstract, and Introduction.
- Started reading about FPGA programming and digital circuit
- Will finalise a first draft of her project proposal for fellowships
Saad Shaikh
- Old MacBook Pro died – now set up on DAQ laptop.
- Waiting on Ruben to respond regarding purchasing new laptop.
- Using Xilinx Clocking Wizard to generate different clock frequencies – still testing this.
- Need to finish serial UART interface example project.
- Need to convert UCF constraints file provided by TI to XDC in order to use in Vivado.