Minutes for UCL Proton Calorimetry Meetings, 5th August
Simon Jolly, Saad Shaikh, Raffaella Radogna, Fern Pannell
- Working on FIFO interface between DDC232 data and UART transmitter.
- Using Xilinx FIFO Generator IP but need to debug.
- Then need to instantiate processor for DMA from FIFO.
- Tutorial about Vivado IP integrator should give details about processor instantiation and workflow with Vitis.
- Managed to simulate FPGA response for blinking LED tutorial
- Now on the UART interface tutorial.
- Started looking and running Saad's code
- Had a meeting with the head of physics department at Sussex university
- Sussex is happy to support fellowship applications for Royal society URF and also suggested to try STFC ERF
- Need to understand with Ruben if UCL will support the URF application