Minutes for UCL Proton Calorimetry Meetings, 4th November
Simon Jolly, Raffaella Radogna, Saad Shaikh, Fern Pannell
- Presented quickly preliminary results about PD output slides showing results (updated version)
- Managed to run Nexys Video USB tutorial at around 50 Mb/s.
- Will start working on implementing USB interface in DDC232 FPGA design.
- Added functionality to send ASCII commands to set FSR remotely.
- Will investigate adding some functionality to set different integration times without reconfiguring FPGA.
- Results from LED tests at UCL show increasing fluctuation/noise with longer integration times and smaller FSR - unsure why this is the case. Also observe 0 values in channels, which should not be possible.
- Tested integration time of 2000us with 350pC FSR using ILA: confirmed that CONV remains in sync with CLK and could see many 0s being sent on DOUT under low light levels.
- Could be low light levels with LED.
- Will continue to test setup at UCL with Raffy.