Survey of SCT latency budget

The overall latency is the time from the interaction until the L1Accept trigger signal is received by the front-end pipeline. The table is a summary of the latency in Bunch Crossings and nanoseconds, including which group has the final say in some sense on the latency value.

BC ns Latency Item Latency Responsibility
77.91947Central Trigger Processor output ATLAS Level-1 Trigger
0.4 10Fanout module ATLAS Timing, Trigger & Control
1.6 408m cable . . . . . CTP -> TTCvi ATLAS Technical Coordination
0.1 3TTC vme interface module ATLAS Timing, Trigger & Control
0.1 30.6m cable . . TTCvi -> TTCvx ATLAS Timing, Trigger & Control
0.9 22TTC vme transmitter module ATLAS Timing, Trigger & Control
6.4 16032m fibre . . . TTCvx -> TTCrx ATLAS Technical Coordination
3.0 75TTC receiver chip ATLAS Timing, Trigger & Control
2.0 50Timing Interface Module SCT Off-Detector Electronics
0.2 5Backplane of ROD crate SCT Off-Detector Electronics
3.0 75Read-Out Driver module SCT Off-Detector Electronics
0.5 13Back Of Crate card SCT Off-Detector Electronics
2.0 50Bi-Phase Mark chip SCT Links
19.4 48597m fibre . . . ROD -> Detector ATLAS Technical Coordination
1.0 25DORIC decoder chip SCT Links
7.0 175ABC(D) readout chip SCT Front-End Electronics
6.5 162SCT Contingency SCT Electronics Coordinator
132.03300 Total ( = Pipeline Length )

Last update: 23 June 2004 (last budget change: 6 June 1999)

John Lane (UCL) email: