SCT/Pixel TIM-RCC Interface Specification
September 29, 2000
Draft 0.4 by John Lane
Abstract
This document is a preliminary draft of the SCT/Pixel
interface specification between TIM and RCC. Feedback is welcome.
Introduction
The TTC Interface Module (TIM) communicates with a local processor,
the ROD Crate Controller (RCC), via a VME slave interface.
This specification should satisfy the interface requirements set out in
the RCC requirements document
[ref. RCC_requirements]
and the TIM requirements document
[ref. TIM_requirements].
Registers
The TIM has writeable control registers and readable status registers,
which the RCC uses to configure TIM and control its stand-alone operation.
The RCC has control by programmed i/o of the following stand-alone operations
on TIM:
- Internal hardware-generated repetitive signals
- Sequencer memory and operation
- VME-generated command signals
- Function and signal enables
This specification is supported by a separate description of the TIM registers
[ref. TIM_registers].
Address Map
The TIM has an A16 address space of 64K bytes, using address lines A15 - A0,
offset by a base address, which uses address lines A31 - A16.
The RCC has read and write access to TIM as 16-bit words.
The VME address is given as hexadecimal bytes in the following address map.
| Address | Field
|
|---|
| 0000 - 003E | Register address space
|
| 0040 - 7FFE | Reserved address space
|
| 8000 - FFFE | Sequencer RAM
|
VME interface
- Standard VME signals and pin assignments are used.
- The VME slave interface supports A32/D16 and A24/D16 access protocols.
- The base address offset is address lines A31 - A16, selected by switches.
- Address A0 is not used and always assumed to be zero.
- VME access is D16 data transfers only, ie 16-bit words.
- Address modifier codes for user and system data access are supported.
- Block transfer, read-modify-write and address-only cycles
are not supported.
- VME interrupts are release on acknowledge (ROAK) type,
with adjustable priority level (IRQ 1 to 7)
and adjustable D16 interrupt vector (STATUS/ID).
References
RCC_requirements http://www.hep.phy.cam.ac.uk/atlas/hill/rcc_tim.html
TIM_requirements http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_requirements.html
TIM_registers http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_registers.html
History:
0.1 30Jul99 JBL First draft
0.2 13Jul00 JBL Major rewrite
0.3 21Jul00 JBL Minor rewrite
0.4 29Sep00 JBL Define interrupts; Pixel too
Last update: 29 September 2000
by John Lane (UCL) email:
jbl@hep.ucl.ac.uk
http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_interface_RCC.html