TIM registers

Address Map
Offset by Base Address (A31 - A16)
Address	D16 Field
0000 - 003E	Register address space
0040 - 00FE	TIM3 Extra Register address space
0100 - 01FE	TIM3 FPGA1 Register address space
0200 - 7FFE	Reserved address space
8000 - FFFE	First word of Sequencer RAM Last word of Sequencer RAM


Register Address Map
Offset	Read/ Write	No	Name	Init Value	CPLD/FPGA
`0x00`	R/W	0	Signal Enables	`0`	2/2
`0x02`	R/W	1	Command & Mode	`0`	2/2
`0x04`	R/W	2	Burst Count	`0`	3/2
`0x06`	R/W	3	Frequency Select	`0`	3/2
`0x08`	R/W	4	Trigger Window	`0`	3/2
`0x0A`	R/W	5	Delay	`0`	2/2
`0x0C`	R	6	Status	`0x8A80`	3/2
`0x0E`	R	7	FIFO Status	`0x4040`	5/2
`0x10`	R(/W)	8	Trigger ID Lo	`0xFFFF`	4a/2
`0x12`	R(/W)	9	Trigger ID Hi	`0x00FF`	4a/2
`0x14`	R(/W)	10	Trigger BCID	`0`	4b/2
`0x16`	R(/W)	11	Trigger Type ID	`0`	4b/2
`0x18`	R/W	12	Run Enables	`0`	6/2
`0x1A`	R/W	13	Sequencer Control	`0`	7/2
`0x1C`	R/W	14	Sequencer End	`0`	7/2
`0x1E`	R/W	15	RODBusy Mask	`0`	8/2
`0x20`	R	16	RODBusy Status	`0`	8/2
`0x22`	R/Z	17	RODBusy Latch	`0`	8/2
`0x24`	R/Z	18	RODBusy Monitor	`0`	8/2
`0x26`	R/Z	19	TTC Data	`0`	9/2
`0x28`	R/W	20	TTC Select	`0`	9/2
`0x2A`	R/Z	21	TTC BCID	`0`	4b/2
`0x2C`	R/W	22	TTCrx Control	`0`	9/2
`0x2E`	R	23	TTC Status	`0`	9/2
`0x30`	R/Z	24	TIM Output Latch	`0`	6/2
`0x32`	R	25	TIM ID	`-`	5/2
`0x34`	-	26	reserved	`-`	-
`0x36`	-	27	reserved	`-`	-
`0x38`	-	28	reserved	`-`	-
`0x3A`	-	29	reserved	`-`	-
`0x3C`	-	30	reserved	`-`	-
`0x3E`	-	31	reserved	`-`	-

TIM-3 Only - Extra Registers Address Map
Offset	Read/ Write	No	Name	Init Value	FPGA
`0x40`	-	32	reserved	`-`	2
`0x42`	R/W	33	Enables3	`0`	2
`0x44`	-	34	reserved	`-`	2
`0x46`	R/W	35	Control	`0`	2
`0x48`	-	36	reserved	`-`	2
`0x4A`	R	37	Status3	`0x0640`	2
`0x4C`	R/Z	38	Status Change Latch	`0x0004`	2
`0x4E`	R/Z	39	Status3 Change Latch	`0x0400`	2
`0x50`	-	40	reserved	`-`	2
`0x52`	R/W	41	QPLL Control	`0x00B0`	2
`0x54`	-	42		`-`	2
`0x56`	R/W	43	Busy Enable3	`0x1000`	2
`0x58`	-	44	reserved	`-`	2
`0x5A`	R	45	Busy Status3	`0x8400`	2
`0x5C`	-	46	reserved	`-`	2
`0x5E`	R/Z	47	Busy Status Change Latch	`0x0300`	2
`0x60`	R/Z	48	Overall Busy Count Lo	`-`	2
`0x62`	R/Z	49	Overall Busy Count Hi	`-`	2
`0x64`	R/Z	50	Overall Busy Count Ex	`-`	2
`0x66`	-	51	reserved	`-`	2
`0x68`	R/W	52	FFTV Busy Duration	`40000`	2
`0x6A`	R/W	53	FFTV Match Threshhold	`10`	2
`0x6C`	R/W	54	FFTV Period Min	`533`	2
`0x6E`	R/W	55	FFTV Period Max	`2666`	2
`0x70`	R/W	56	FFTV Match Decay Period	`2766`	2
`0x72`	R/W	57	FFTV Period Match Tolerance	`40`	2
`0x74`	R/Z	58	FFTV Count Lo	`0`	2
`0x76`	R/Z	59	FFTV Count Hi	`0`	2
`0x78`	R/Z	60	FFTV Count Ex	`0`	2
`0x7A`	-	61	reserved	`-`	2
`0x7C`	R/Z	62	FFTV Trigger Count Lo	`0`	2
`0x7E`	R/Z	63	FFTV Trigger Count Hi	`0`	2
`0x80`	-	64	reserved	`0`	2
`0x82`	-	65	reserved	`0x4000`	2
`0x84`	R/Z	66	Veto ID Counter Lo	`0`	2
`0x86`	R/Z	67	Veto ID Counter Hi	`0`	2
`0x88`	-	68	reserved	`-`	2
`0x8A`	-	69	reserved	`-`	2
`0x8C`	-	70	reserved	`-`	2
`0x8E`	R/Z	71	Burst Count Hi	`0`	2
`0x90`	-	72	reserved	`0`	2
`0x92`	-	73	reserved	`0`	2
`0x94`	R	74	F2 Timestamp Lo	`-`	2
`0x96`	R	75	F2 Timestamp Hi	`-`	2
`0x98`	-	76	reserved	`0`	2
`0x9A`	-	77	reserved	`0`	2
`0x9C`	R/W	78	F2 Debug Control	`0`	2
`0x9E`	R	79	F2 Debug Status	`-`	2

Registers

TIM RESET means power-up reset, push-button reset, or vRESET command bit
reserved bits are either Read/Write or = 0 if Read only
undefined bits are not implemented and read as any value

0x00. Signal Enables Register [Jump Back to Index]
Signal Enables - `ENABLES`		Stand-alone External/Internal Signal Enables - R/W

Bits	Field	Function
0	-	reserved=0
1	EnIntTRIG	Enable internal repetitive trigger
2	EnIntECR	Enable internal repetitive ECReset
3	EnIntBCR	Enable internal repetitive BCReset
4	EnRandom	Enable internal trigger randomizer
5	EnIntFER	Enable internal repetitive FEReset
6	EnWindow	Enable trigger window
7	EnIntBusy	Enable internal Busy
8	EnExtClk	Enable external clock inputs
9	EnExtTRIG	Enable external trigger inputs
10	EnExtECR	Enable external ECReset inputs
11	EnExtBCR	Enable external BCReset inputs
12	EnExtCAL	Enable external Calibrate inputs
13	EnExtFER	Enable external FEReset inputs
14	EnExtSEQ	Enable external Sequencer Go inputs
15	EnExtBusy	Enable external Busy inputs
Register is set to 0 by Reset. Note: external means ECL or NIM front-panel inputs. EnExtCLK disables the internal clock. Note: IntECR is only available if the internal ECR = FER link is inserted (this is the default hardware setup).

0x02. Command & Mode Register [Jump Back to Index]
Command & Mode - `COMMAND`			Commands and Mode Settings - R/W

Bits	Mode	Field	Function
0	-	-	reserved=0
1	edge	vTRIG	Single trigger
2	edge	vECR	Single ECReset
3	edge	vBCR	Single BCReset
4	edge	vCAL	Single Calibrate strobe
5	edge	vFER	Single FEReset
6	edge	vSpare	Single Spare command
7	level	vBusy	Set Busy
8	level	vRodBusy	Set RodBusy
9	level	vBurstMode	Set BURST mode - disable triggers
10	edge	vBurstGo	Start BURST triggers - Int or Ext
11	-	-	reserved=0
12	level	EnRunMode	Enable Run Mode
13	level	EnTestBusy	Enable Busy set by next trigger (TestBusy)
14	level	ClrTestBusy	Clear TestBusy
15	edge	vReset	Overall TIM RESET
Register is set to 0 by Reset. Note: a command bit has one of two modes of operation: 1. level : command is asserted while the bit is set (to 1) 2. edge : command is generated by setting the bit (from 0 to 1, ie the bit must be cleared to re-enable operation)

0x04. Burst Count Register [Jump Back to Index]
Burst Count - `BURST`		Burst Count - R/W

Bits	Field	Function
0-15	BurstCount	Number of triggers in BURST
Register is set to 0 by Reset.

0x06. Frequency Select Register [Jump Back to Index]
Frequency Select - `FREQUENCY`		Trigger/ECR Oscillator Frequency Select - R/W

Bits	Field	Function
0-4	IntTRIGfreq	Internal trigger look-up table
5-7	-	unused = 0
8-12	IntFERfreq	Internal ECR/FER look-up table
13-15	-	unused = 0
Register is set to 0 by Reset.

IntTRIGfreq lookup table
Bits (7:0) Hex		Multiplier
Bits (7:0) Hex		x1	x10	x100	x1000
Freq (Hz)	600	11	09	01	00
	300	1A	12	0A	02
	200	1B	13	0B	03
	150	1C	14	0C	04
	120	1D	15	0D	05
	100	1E	16	0E	06
	60	19	11	09	01
	50	1F	17	0F	07

IntFERfreq lookup table
Bits (15:8) Hex		Multiplier
Bits (15:8) Hex		x1	x10	x100	x1000
Freq (Hz)	0.060	11	09	01	00
	0.030	1A	12	0A	02
	0.020	1B	13	0B	03
	0.015	1C	14	0C	04
	0.012	1D	15	0D	05
	0.010	1E	16	0E	06
	0.006	19	11	09	01
	0.005	1F	17	0F	07

Notes:
1. Example: Write 0E06 hex for triggers at 100 kHz and front-end resets at 1 Hz.
2. If the EnRandom bit is set, the average frequency of the random triggers is one quarter of the above internal trigger frequency table.

0x08. Trigger Window Register [Jump Back to Index]
Trigger Window - `WINDOW`		Trigger Window Control - R/W

Bits	Field	Function
0- 5	WinSize	Trigger window size (0.5ns steps)
6-7	-	reserved=0
8-13	WinDelay	Trigger window delay (0.5ns steps)
14-15	-	reserved=0
Register is set to 0 by Reset. Note: the Trigger Window register is for External Trigger input only.

0x0A. Delay Register [Jump Back to Index]
Delay - `DELAYS`		Stand-alone Mode Delays - R/W

Bits	Field	Function
0- 7	TrigDelay	Stand-alone trigger pipeline delay (clock steps)
8-13	ClkDelay	Stand-alone clock delay (0.5ns steps)
14-15	-	reserved=0
Register is set to 0 by Reset.

0x0C. Status Register [Jump Back to Index]
Status - `STATUS`		General Status - R

Bits	Field	Function
0	ExtBusy	Front-panel Busy Input (post-enable)
1	MExtBusyout	Masked ExtBusy Output
2	Busy	TIM stopping triggers internally
3	Busyout	Front-panel Busy Output
4	BurstBusy	Burst Ready, awaiting Burst-Go
5	SeqSrcAct	Sequencer Source Running
6	SeqSinkAct	Sequencer Sink Running
7	RodBusyout	Front-panel RodBusy Output
8	TTCClkOK	TTC system clock present
9	SAClkOK	Stand-alone clock present
10	RunMode	TTC system operation
11	SaMode	Stand-alone operation
12	-	reserved=0
13	TIMOK	Selected Clock is running.
14	TestBusy	Test-Busy Triggered
15	LaserInterlock	Laser Interlock on (n/c on TIM3: pulled high)

0x0E. FIFO Status Register [Jump Back to Index]
FIFO Status - `FIFO`		FIFO Status - R

Bits	Field	Function
0- 5	IDcount	Event ID FIFO Count
6	IDEF	Event ID Empty Flag
7	IDFF	Event ID Full Flag
8-13	TTcount	Trigger Type FIFO Count
14	TTEF	Trigger Type Empty Flag
15	TTFF	Trigger Type Full Flag

0x10. Trigger ID Lo Register [Jump Back to Index]
Trigger ID Lo - `L1IDL`			Trigger Number LSW - R(/W)

Bits	Mode	Field	Function
0-15	R	L1IDlo	Last trigger number (bits 0-15)
0-15	(R/W)	L1IDlo	Load last trigger number (next-1)
Register is set to 0xFFFF by Reset.

0x12. Trigger ID Hi Register [Jump Back to Index]
Trigger ID Hi - `L1IDH`			Trigger Number MSB/ ECR-ID - R(/W)

Bits	Mode	Field	Function
0- 7	R	L1IDhi	Last trigger number (bits 16-23)
0- 7	(R/W)	L1IDhi	Load last trigger number (next-1)
8-15	R	ECRID	ECR counter
Register is set to 0x00FF by Reset.

0x14. Trigger BCID Register [Jump Back to Index]
Trigger BCID - `BCID`			Trigger Bunch Crossing - R(/W)

Bits	Mode	Field	Function
0-11	R	BCID	Bunch Crossing number of last trigger
12-15	R/W	Offset	BCID offset
Register is set to 0 by Reset.

0x16. Trigger Type ID Register [Jump Back to Index]
Trigger Type ID - `TTID`		Trigger Type - R(/W)

Bits	Field	Function
0- 7	TTID1	TTC Trigger Type
8-11	TTID2	TIM Trigger Type
12-15	-	undefined
Register is set to 0 by Reset.

0x18. Run Enables Register [Jump Back to Index]
Run Enables - `RUN_ENABLE`		TTC and Other Enables - R/W

Bits	Field	Function
0	EnTTCClk	Enable TTC clock
1	EnL1A	Enable TTC L1Accept Trigger
2	EnECR	Enable TTC ECReset
3	EnBCR	Enable TTC BCReset
4	EnCAL	Enable TTC Calibrate Strobe
5	EnFER	Enable TTC FEReset
6	EnSpare	Enable TTC Spare command
7	EnRodBusy	Enable RodBusy into Busyout
8	EnExtRodBusy	Enable external RodBusy input
9	EnID	Enable trigger & bunch ID numbers
10	EnTYPE	Enable trigger type
11	-	reserved=0
12	-	reserved=0
13	-	reserved=0
14	EnSaECR	Enable counter ECR
15	EnSaBCR	Enable counter BCR
Register is set to 0 by Reset.

0x1A. Sequencer Control Register [Jump Back to Index]
Sequencer Control - `SEQ_CTL`			Sequencer Control - R/W

Bits	Mode	Field	Function
0	level	EnSeqTRIG	Enable L1Accept trigger
1	level	EnSeqECR	Enable ECReset
2	level	EnSeqBCR	Enable BCReset
3	level	EnSeqCAL	Enable Calibrate strobe
4	level	EnSeqID	Enable SerialID
5	level	EnSeqTT	Enable SerialTT
6	level	EnSeqFER	Enable FEReset
7	level	EnSeqSpare	Enable Spare command
8	-	-	reserved=0
9	level	SeqRESET	Reset Sequencer
10	edge	SeqGO	Start Sequencer
11	level	EnCyclic	Enable cyclic operation
12	-	-	reserved=0
13	level	SinkRESET	Reset Sink
14	edge	SinkGO	Start Sink (and Source)
15	level	EnStartSink	Enable Sink trigger
Register is set to 0 by Reset. Note: a sequencer control bit has one of two modes of operation: 1. level : command or enable is asserted while the bit is set (to 1) 2. edge : command is generated by setting the bit (from 0 to 1, ie the bit must be cleared to re-enable operation)

0x1C. Sequencer End Register [Jump Back to Index]
Sequencer End - `SEQ_END`		Sequencer End Count Value - R/W

Bits	Field	Function
0-13	EndAddr	End/Recycle address
14-15	-	reserved=0
Register is set to 0 by Reset. Note: Counts from 0 - e.g. nClocks = (End+1)

0x1E. RODBusy Mask Register [Jump Back to Index]
RODBusy Mask - `RB_MASK`		ROD Mask - R/W

Bits	Field	Function
0-15	RODmask	RodBusy mask (16 slots: 5-12, 14-21)
Register is set to 0 by Reset. Note: the ROD bits are in the order of ROD slot number, eg bit 0 is slot 5 in the ROD crate, bit 7 is slot 12, bit 8 is slot 14, etc.

0x20. RODBusy Status Register [Jump Back to Index]
RODBusy Status - `RB_STAT`		RODBusy Status - R

Bits	Field	Function
0-15	RodBusy	RodBusy status (16 slots: 5-12, 14-21)

0x22. RODBusy Latch Register [Jump Back to Index]
RODBusy Latch - `RB_LATCH`		RODBusy Latch - R/Z

Bits	Field	Function
0-15	RODlatch	RodBusy latch (16 slots: 5-12, 14-21)
Register is set to 0 by Reset or by a WRITE. Note: the ROD bits are in the order of ROD slot number, eg bit 0 is slot 5 in the ROD crate.

0x24. RODBusy Monitor Register [Jump Back to Index]
RODBusy Monitor - `RB_MON`		RODBusy Monitor - R/Z

Bits	Field	Function
0-15	RODmonitor	RodBusy monitor (16 slots: 5-12, 14-21)
Register is set to 0 by Reset or by a WRITE. Note: the ROD bits are in the order of ROD slot number, eg bit 0 is slot 5 in the ROD crate.

0x26. TTC Data Register [Jump Back to Index]
TTC Data - `TTC_DATA`		TTC Data Monitor - R/Z

Bits	Field	Function
0- 7	Dout	Long-format data
8-15	SubAddr	Sub-address
Register is set to 0 by Reset or by a WRITE.

0x28. TTC Select Register [Jump Back to Index]
TTC Select - `TTC_SELECT`		TTC Data Monitor Select - R/W

Bits	Field	Function
0- 3	DQselect	Select long-format Data Qualifier
4-15	-	undefined=0
Register is set to 0 by Reset.

0x2A. TTC BCID Register [Jump Back to Index]
TTC BCID - `TTC_BCID`		Last TTC BCID Received - R/Z

Bits	Field	Function
0-11	TTC_BCID	TTC bunch number
12-15	-	undefined=0
Register is set to 0 by Reset or by a WRITE.

0x2C. TTCrx Control Register [Jump Back to Index]
TTCrx Control - `TTCRX_CTL`		TTCrx Control Register (I2C) - R/W

Bits	Field	Function
0- 7	Data	TTCrx data (read or write)
9-12	Pointer	TTCrx register number
13	Read	I2C Read (not Write)
14	Enable	T2: I2C clock enable/T3 R: Error Status, W: Abort
15	Control	R: I2C Busy / W: I2C Go
Register is set to 0 by Reset.

0x2E. TTC Status Register [Jump Back to Index]
TTC Status - `TTC_STATUS`		TTC Status - R

Bits	Field	Function
0	BCntRes	BCReset
1	EvCntRes	ECReset
2	Brcst(2)	FEReset bit - system message
3	Brcst(3)	Broadcast bit - system message
4	Brcst(4)	Broadcast bit - system message
5	Brcst(5)	Broadcast bit - system message
6	Brcst(6)	Calibrate bit - user message
7	Brcst(7)	Broadcast bit - user message
8	L1Accept	Trigger
9	BrcstStr1	Broadcast strobe - system message
10	BrcstStr2	Broadcast strobe - user message
11	DoutStr	Long-format data strobe
12	DbErrStr	Double error or frame error occured
13	SinErrStr	Single error occured
14	TTCReady	TTCrx operating correctly
15	-	reserved=0

0x30. TIM Output Latch Register [Jump Back to Index]
TIM Output Latch - `TIM_OUTPUT`		TIM Backplane Signals Output Latch - R/Z

Bits	Field	Function
0	TTCout0	L1Accept trigger
1	TTCout1	ECReset
2	TTCout2	BCReset
3	TTCout3	Calibrate strobe
4	TTCout4	SerialID
5	TTCout5	SerialTT
6	TTCout6	FEReset
7	TTCout7	Spare command
8-15	-	reserved=0
Register is set to 0 by Reset or by a WRITE.

0x32. TIM ID Register [Jump Back to Index]
TIM ID - `TIM_ID`		Hardware and Firmware ID - R

Bits	Field	Function
0- 7	SerialNo	Serial number
8-15	Version	Version number

0x42. Enables3 Register [Jump Back to Index]
Enables3 - `ENABLES3`		TIM3 Specific Enables - R/W

Bits	Field	Function
0-2	-	Sets user mode - controls detector unique functions (none as yet!)
3	-	reserved=0
4	L1IDroECRen	Enable L1ID rollover to increment ECR-ID
5	QpllControlEn	Enable output QPLL lines to TTCrq (see qpll_ctl)
6	-	Enable Randomiser (version 2)
7	-	reserved=0
8	TrigSeqModeEn	Stand-alone trigs set to generate SeqGo (only)
9	-	reserved=0
10	-	reserved=0
11	-	reserved=0
12	-	reserved=0
13	-	reserved=0
14	-	reserved=0
15	-	reserved=0
Register is set to 0 by Reset.

0x46. Control Register [Jump Back to Index]
Control - `CONTROL`		General Control - R/W

Bits	Field	Function
0	-	reserved=0
1	-	reserved=0
2	-	reserved=0
3	-	reserved=0
4-7	-	Average frequency of Randomiser 2
8	-	reserved=0
9	-	reserved=0
10	-	reserved=0
11	-	reserved=0
12	-	reserved=0
13	-	reserved=0
14	-	reserved=0
15	-	reserved=0
Register is set to 0 by Reset.

0x4A. Status3 Register [Jump Back to Index]
Status3 - `STATUS3`		TIM3 Specific Status bits - R

Bits	Field	Function
0	TTCReady3	TTCrx operating correctly
1	QpllPresent	TTCrq/QPLL chip present
2	QpllError	QPLL Chip Error
3	QpllLocked	QPLL Locked
4	TtcClkOK3	TTC clock is present
5	-	reserved=0
6	SaClkOK3	SA clock is present
7	TtcClkEnOK	TTC Clock Selected and Running ('TT' LED)
8	ExtClkEnOK	Ext Clock Selected and Running
9	IntClkEnOK	Internal Clock Selected and Running
10	PllStable	Clock PLL(s) stable after switching clocks
11	-	reserved=0
12	-	reserved=0
13	-	reserved=0
14	spare_in	Spare Input
15	spare_link	Spare Link

0x4C. Status Change Latch Register [Jump Back to Index]
Status Change Latch - `STATUS_LCH`		Status Change Latch - R/Z

Bits	Field	Function
0-15	Status Change Latch	Latches changes in Status Register (6) since last write
Register is set to 0x0004 by Reset or by a WRITE.

0x4E. Status3 Change Latch Register [Jump Back to Index]
Status3 Change Latch - `STAT3_LCH`		Status3 Change Latch - R/Z

Bits	Field	Function
0-15	Status3 Change Latch	Latches changes in Status3 since last write
Register is set to 0x0400 by Reset or by a WRITE.

0x52. QPLL Control Register [Jump Back to Index]
QPLL Control - `QPLL_CTL`		QPLL Control - R/W

Bits	Field	Function
0-3	QpllF0Select	QPLL f0 Select (bits 3:0)
4	QpllAutorestart	QPLL Auto-restart/f0 sel bit 4
5	nQpllReset	QPLL Reset/f0 Select bit 5
6	QpllExtControl	QPLL External Control Enable
7	QpllMode	QPLL Mode
8	-	reserved=0
9	-	reserved=0
10	-	reserved=0
11	-	reserved=0
12	-	reserved=0
13	-	reserved=0
14	-	reserved=0
15	-	reserved=0
Register is set to 0x00B0 by Reset.

0x56. Busy Enable3 Register [Jump Back to Index]
Busy Enable3 - `BUSY_EN3`		Busy Enable3 - R/W

Bits	Field	Function
0	enRBbusy	Enable RodBusy into Busy
1	enXRBbusy	Enable External-RodBusy into Busy
2	enVRBbusy	Enable VME-RodBusy into Busy
3	enXBbusy	Enable External-Busy into Busy
4	enVBbusy	Enable VME-Busy into Busy
5	-	reserved=0
6	-	reserved=0
7	-	reserved=0
8	enRBbusyout	Enable RodBusy into Busyout
9	enXRBbusyout	Enable External-RodBusy into Busyout
10	enVRBbusyout	Enable VME-RodBusy into Busyout
11	enXBbusyout	Enable External-Busy into Busyout
12	enVBbusyout	Enable VME-Busy into Busyout
13	enBSTBbusyout	Enable Burst-Busy into Busyout
14	enTSTBbusyout	Enable Test-Busy into Busyout
15	enDTBbusyout	Enable Deadtime-Busy into Busyout
Register is set to 0x1000 by Reset.

0x5A. Busy Status3 Register [Jump Back to Index]
Busy Status3 - `BUSY_STAT3`		Busy Status3 - R

Bits	Field	Function
0	RodBusy	RB: OR of all RodBusy backplane inputs (post masking)
1	ExtRodBusy	XRB: External RodBusy (post-enable)
2	vRodBusy3	VRB: VME-RodBusy
3	ExtBusy3	XB: Front Panel Busy Input (post-enable)
4	vBusy3	VB: VME-Busy
5	BurstBusy3	BSTB: Burst Ready, awaiting Burst-Go
6	TestBusy3	TSTB: Test-Busy Triggered
7	DeadTimeBusy	DTB: Stand-Alone Signal Dead-Time
8	ClkSwitchBusy	Timeout after clock-switch/reset to ensure downstream stable
9	Busy3	TIM stopping triggers internally
10	RodBusyout3	Front-panel RodBusy Output
11	Busyout3	Front-panel Busy Output
12	MExtBusyout3	Front-panel Masked ExtBusy Output
13	-	reserved=0
14	FFVetoOn	Fixed Frequency Trigger Veto On
15	FFTVLinkStat	FFTV Disable Link Inserted

0x5E. Busy Status Change Latch Register [Jump Back to Index]
Busy Status Change Latch - `BSTAT3_LCH`		Catches changes in BSTAT3 since last reset/clear - R/Z

Bits	Field	Function
0-15	Busy Status Change Latch	Catches changes in BSTAT3 since last reset/clear
Register is set to 0x0300 by Reset or by a WRITE.

0x60. Overall Busy Count Lo Register [Jump Back to Index]
Overall Busy Count Lo - `BCOUNTL`		Overall Busy Count Lo - R/Z

Bits	Field	Function
0-15	Overall Busy Count Lo	Overall Busy Count Lo
Register is set to - by Reset or by a WRITE.

0x62. Overall Busy Count Hi Register [Jump Back to Index]
Overall Busy Count Hi - `BCOUNTH`		Overall Busy Count Hi - R/Z

Bits	Field	Function
0-15	Overall Busy Count Hi	Overall Busy Count Hi
Register is set to 0x0300 by Reset or by a WRITE.

0x64. Overall Busy Count Ex Register [Jump Back to Index]
Overall Busy Count Ex - `BCOUNTX`		Overall Busy Count Ex - R/Z

Bits	Field	Function
0-15	Overall Busy Count Ex	Overall Busy Count Ex
Register is set to - by Reset or by a WRITE.

0x68. FFTV Busy Duration Register [Jump Back to Index]
FFTV Busy Duration - `FV_VETOLEN`		FFTV Busy Duration - R/W

Bits	Field	Function
0-15	FFTV Busy Duration	FFTV Busy Duration
Register is set to 40000 by Reset.

0x6A. FFTV Match Threshhold Register [Jump Back to Index]
FFTV Match Threshhold - `FV_MATCH`		FFTV Match Threshhold - R/W

Bits	Field	Function
0-15	FFTV Match Threshhold	FFTV Match Threshhold
Register is set to 10 by Reset.

0x6C. FFTV Period Min Register [Jump Back to Index]
FFTV Period Min - `FV_P_MIN`		Period Minimim (clks) - R/W

Bits	Field	Function
0-15	FFTV Period Min	Period Minimim (clks)
Register is set to 533 by Reset.

0x6E. FFTV Period Max Register [Jump Back to Index]
FFTV Period Max - `FV_P_MAX`		Period Maximum (clks) - R/W

Bits	Field	Function
0-15	FFTV Period Max	Period Maximum (clks)
Register is set to 2666 by Reset.

0x70. FFTV Match Decay Period Register [Jump Back to Index]
FFTV Match Decay Period - `FV_OFLOW`		Match Decay Period - R/W

Bits	Field	Function
0-15	FFTV Match Decay Period	Match Decay Period
Register is set to 2766 by Reset.

0x72. FFTV Period Match Tolerance Register [Jump Back to Index]
FFTV Period Match Tolerance - `FV_DELTAT`		FFTV Period Match Tolerance - R/W

Bits	Field	Function
0-15	FFTV Period Match Tolerance	FFTV Period Match Tolerance
Register is set to 40 by Reset.

0x74. FFTV Count Lo Register [Jump Back to Index]
FFTV Count Lo - `FV_COUNTL`		FFTV Count Lo - R/Z

Bits	Field	Function
0-15	FFTV Count Lo	Counts clocks when FFTVeto is asserted (15:0)
Register is set to 0 by Reset or by a WRITE.

0x76. FFTV Count Hi Register [Jump Back to Index]
FFTV Count Hi - `FV_COUNTH`		FFTV Count Hi - R/Z

Bits	Field	Function
0-15	FFTV Count Hi	Counts clocks when FFTVeto Asserted (31:16)
Register is set to 0 by Reset or by a WRITE.

0x78. FFTV Count Ex Register [Jump Back to Index]
FFTV Count Ex - `FV_COUNTX`		FFTV Count Ex - R/Z

Bits	Field	Function
0-15	FFTV Count Ex	Counts clocks when FFTVeto Asserted (47:32)
Register is set to 0 by Reset or by a WRITE.

0x7C. FFTV Trigger Count Lo Register [Jump Back to Index]
FFTV Trigger Count Lo - `FV_TCOUNTL`		Number of Triggers FFTVeto'd LSW - R/Z

Bits	Field	Function
0-15	FFTV Trigger Count Lo	Counts number of Triggers FFTVeto'd (15:0)
Register is set to 0 by Reset or by a WRITE.

0x7E. FFTV Trigger Count Hi Register [Jump Back to Index]
FFTV Trigger Count Hi - `FV_TCOUNTH`		Number of Triggers FFTVeto'd MSW - R/Z

Bits	Field	Function
0-15	FFTV Trigger Count Hi	Counts number of Triggers FFTVeto'd (31:0)
Register is set to 0 by Reset or by a WRITE.

0x84. Veto ID Counter Lo Register [Jump Back to Index]
Veto ID Counter Lo - `FV_IDL`		Counts Number of time Veto is Generated LSW - R/Z

Bits	Field	Function
0-15	Veto ID Lo	Counts number of times FFTVeto is Asserted (15:0)
Register is set to 0 by Reset or by a WRITE.

0x86. Veto ID Counter Hi Register [Jump Back to Index]
Veto ID Counter Hi - `FV_IDH`		Counts Number of time Veto is Generated MSW - R/Z

Bits	Field	Function
0-15	Veto ID Hi	Counts number of times FFTVeto is Asserted (31:16)
Register is set to 0 by Reset or by a WRITE.

0x8E. Burst Count Hi Register [Jump Back to Index]
Burst Count Hi - `BURST_HI`		Burst Counter MSW - R/Z

Bits	Field	Function
0-15	Burst Count Hi	Burst Counter MSW
Register is set to 0 by Reset or by a WRITE. Note: Used in Conjuction with BURST register. Enable L1ID-rollover-to-ECRID (ENABLES3,4) to count 32 bit L1ID

0x94. F2 Timestamp Lo Register [Jump Back to Index]
F2 Timestamp Lo - `TSTAMPL`		F2 Timestamp LSW - R

Bits	Field	Function
0-15	F2 Timestamp Lo	F2 Timestamp LSW

0x96. F2 Timestamp Hi Register [Jump Back to Index]
F2 Timestamp Hi - `TSTAMPH`		F2 Timestamp MSW - R

Bits	Field	Function
0-15	F2 Timestamp Hi	F2 Timestamp MSW

0x9C. F2 Debug Control Register [Jump Back to Index]
F2 Debug Control - `DEBUG_CTL`		F2 Debug Control - R/W

Bits	Field	Function
0-3	-	reserved=0
4	-	reserved=0
5	-	reserved=0
6	-	reserved=0
7	-	reserved=0
8	CSBdisable	Disable Clk-Switch Busy
9	SARBdisable	Disable SA-Mode setting RodBusy
10	-	reserved=0
11	-	reserved=0
12	FVdisable	FFTV Veto Disable (needs link in place too)
13	-	reserved=0
14	-	reserved=0
15	-	reserved=0
Register is set to 0 by Reset.

0x9E. F2 Debug Status Register [Jump Back to Index]
F2 Debug Status - `DEBUG_STAT`		F2 Debug Status - R

Bits	Field	Function
0-3	-	reserved=0
4	-	reserved=0
5	-	reserved=0
6	-	reserved=0
7	-	reserved=0
8	-	reserved=0
9	-	reserved=0
10	-	reserved=0
11	-	reserved=0
12	-	reserved=0
13	-	reserved=0
14	-	reserved=0
15	-	reserved=0

Sequencer RAM

Sequencer RAM Address Map

Address	Byte Field (D16 access only)
8000	First byte of Source data
8001	First byte of Sink data
...	...
FFFE	Last byte of Source data
FFFF	Last byte of Sink data

Notes:
1. The source and sink memories are each 16K bytes long, interleaved with the source being the least significant byte of each 16-bit word, giving 32K bytes (16K words) of sequencer memory in total. 2. The memories have no reset and have undefined values after a power-up cycle; to be safe they should be filled with zeros after each TIM RESET.

Sequencer RAM
VME Address: 8000-FFFE		R/W

bit	Field	Function
0	SourceTRIG	Source L1Accept trigger
1	SourceECR	Source ECReset
2	SourceBCR	Source BCReset
3	SourceCAL	Source Calibrate strobe
4	SourceID	Source SerialID
5	SourceTT	Source SerialTT
6	SourceFER	Source FEReset
7	SourceSpare	Source Spare command
8	SinkTRIG	Sink L1Accept trigger
9	SinkECR	Sink ECReset
10	SinkBCR	Sink BCReset
11	SinkCAL	Sink Calibrate strobe
12	SinkID	Sink SerialID
13	SinkTT	Sink SerialTT
14	SinkFER	Sink FEReset
15	SinkSpare	Sink Spare command

TIM Registers 2005.11

*** Development Snapshot: Attempting to be Valid for Firmware Version 11.***

Contents

Address Map

IntTRIGfreq lookup table

IntFERfreq lookup table

* Development Snapshot: Attempting to be Valid for Firmware Version 11.*