Proton Calorimetry/Experimental Runs/2021/Apr1

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|10 || P, P, P || Yellow trace shows DVALID at FPGA, green shows CLK of first board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. || <div class="image150px" style="text-align: center;">
|10 || P, P, P || Yellow trace shows DVALID at FPGA, green shows CLK of first board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3564.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3564.JPG]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3564.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3564.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3566.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3566.JPG]</div>
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|11 || 3, 1, 4, 2 || board rotation and sweep covering of photodiodes || <div class="image150px" style="text-align: center;">
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|11 || P, R, P || Blue trace shows DOUT of first board at J2, purple shows DOUT of second board at J3, green shows DOUT of third at J3 || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run11.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run11.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3567.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3567.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3568.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3568.JPG]</div>
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|12 || 3, 4, 2, 1 || board rotation and sweep covering of photodiodes || <div class="image150px" style="text-align: center;">
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|12 || P, P, P, R || Yellow trace shows DVALID of first board at J2, blue shows DOUT of first board at J2, purple shows CLK of third board at J3, green shows CLK of fourth board at J3. || <div class="image150px" style="text-align: center;"> [http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3572.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3572.JPG]</div>
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|13 || 3, 2, 1, 4 || board rotation and sweep covering of photodiodes || <div class="image150px" style="text-align: center;">
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|13 || P, P, P, R || Blue trace shows DOUT of first board at J2, purple shows DOUT of third board at J3, green shows DOUT of fourth board at J3. || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run13.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run13.png]</div>
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|14 || P, P, P, R || Yellow trace shows DVALID of first board at J2, blue shows DCLK of first board at J2, purple shows DCLK of third board at J3, green shows DCLK of fourth board at J3. || <div class="image150px" style="text-align: center;">[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3574.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3574.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3575.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3575.JPG]</div>
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|15 || P, P, P, R || Yellow trace shows DVALID of first board at J2, blue shows 12V of first board at J2, purple shows DCLK of third board J3, green shows 12V of fourth board at J3. || <div class="image150px" style="text-align: center;"> [http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3576.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3576.JPG]</div> <div class="image150px" style="text-align: center;"> [http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3577.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3577.JPG]</div>
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|16 || N/A || Yellow shows CLK pin directly from FPGA without any board connected. || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3578.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3578.JPG]</div> <div class="image150px" style="text-align: center;">
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Revision as of 12:24, 7 April 2021

Daisy chain tests of second DDC232 prototype in D109

Aim: Debug "mirroring" issues when daisy-chaining more than 2 DDC232s boards. Test signal quality across boards using 500MHz oscilloscope.

Notes

  • 3 DDC232 boards have S12915-16R photodiodes.
  • 1 DDC232 board has 1k ohm resistors.
  • In the runs below, boards are enumerated right to left, with the right-most board (1st board) connected to the FPGA.
  • In the configuration column, P = board with photodiodes and R = board with resistors. The first board listed in this column is connected to the FPGA.
  • In all runs, an integration time of 170us and full-scale range of 350pC is used.

Traces saved in /unix/www/html/pbt/wikiData/images/DDC232/20210401

Run Board Configuration Scope Trace Description Oscilloscope Trace
1 P Yellow trace shows DVALID at FPGA, blue shows DVALID at J2 of DDC232 board.
IMG_3548.JPG
IMG_3549.JPG
2 P Yellow trace shows DVALID at FPGA, green shows CLK at J2 of DDC232 board, purple shows 12V at J2 of DDC232 board.
IMG_3550.JPG
3 P Yellow trace shows DVALID at FPGA, purple trace shows DOUT at J2 of DDC232 board.
IMG_3551.JPG
IMG_3552.JPG
IMG_3553.JPG
4 P Green trace shows CLK at J2 of DDC232 board, blue trace shows DCLK at J2 of DDC232 board.
IMG_3554.JPG
5 P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows 12V of 1st board at J2.
IMG_3555.JPG
IMG_3556.JPG
6 P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. The last trace shows the end of a readout cycle.
IMG_3557.JPG
IMG_3558.JPG
IMG_3559.JPG
IMG_3560.JPG
7 P, R Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. The trace shows the transition from photodiode data bits to resistor data bits in the readout cycle.
IMG_3561.JPG
8 P, P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, purple shows 12V of 1st board at J2.
IMG_3562.JPG
9 P, P, P Green trace shows CLK of 1st board at J2, blue shows DCLK of first board at J2.
IMG_3563.JPG
10 P, P, P Yellow trace shows DVALID at FPGA, green shows CLK of first board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2.
IMG_3564.JPG
IMG_3566.JPG
11 P, R, P Blue trace shows DOUT of first board at J2, purple shows DOUT of second board at J3, green shows DOUT of third at J3
IMG_3567.JPG
IMG_3568.JPG
12 P, P, P, R Yellow trace shows DVALID of first board at J2, blue shows DOUT of first board at J2, purple shows CLK of third board at J3, green shows CLK of fourth board at J3.
IMG_3572.JPG
13 P, P, P, R Blue trace shows DOUT of first board at J2, purple shows DOUT of third board at J3, green shows DOUT of fourth board at J3.
IMG_3573.JPG
14 P, P, P, R Yellow trace shows DVALID of first board at J2, blue shows DCLK of first board at J2, purple shows DCLK of third board at J3, green shows DCLK of fourth board at J3.
IMG_3574.JPG
IMG_3575.JPG
15 P, P, P, R Yellow trace shows DVALID of first board at J2, blue shows 12V of first board at J2, purple shows DCLK of third board J3, green shows 12V of fourth board at J3.
IMG_3576.JPG
IMG_3577.JPG
16 N/A Yellow shows CLK pin directly from FPGA without any board connected.
IMG_3578.JPG
IMG_3579.JPG
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