Proton Calorimetry/Experimental Runs/2021/Apr1

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'''Notes'''
'''Notes'''
*3 DDC232 boards have S12915-16R photodiodes.
*3 DDC232 boards have S12915-16R photodiodes.
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*4th DDC232 board has 1k ohm resistors.
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*1 DDC232 board has 1k ohm resistors.
*In the runs below, boards are enumerated right to left, with the right-most board (1st board) connected to the FPGA.
*In the runs below, boards are enumerated right to left, with the right-most board (1st board) connected to the FPGA.
 +
*In the configuration column, P = board with photodiodes and R = board with resistors. The first board listed in this column is connected to the FPGA.
*In all runs, an integration time of 170us and full-scale range of 350pC is used.
*In all runs, an integration time of 170us and full-scale range of 350pC is used.
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'''Traces saved in [http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/20210401 /unix/www/html/pbt/wikiData/images/DDC232/20210401]'''
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'''Traces saved in [http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401 /unix/www/html/pbt/wikiData/images/DDC232/20210401]'''
{|class="wikitable"
{|class="wikitable"
!Run
!Run
!Board Configuration
!Board Configuration
-
!Description
+
!Scope Trace Description
-
!Video
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!Oscilloscope Trace
|-
|-
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|1 || 3, 1 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Boards initially facing downwards but rotated upwards to expose to room lighting. Sweep begins around 20s mark. Note that there is no mirroring and both boards behave as expected. || <div class="image150px" style="text-align: center;">
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|1 || P || Yellow trace shows DVALID at FPGA, blue shows DVALID at J2 of DDC232 board. || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run01.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run01.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3548.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3548.JPG]</div> <div class="image150px" style="text-align: centert;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3549.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3549.JPG]</div>
|-
|-
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|2 || 3, 4 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Boards initially facing downwards but rotated upwards to expose to room lighting. Sweep begins around 10s mark. Note similar behaviour to above.  || <div class="image150px" style="text-align: center;">
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|2 || P || Yellow trace shows DVALID at FPGA, green shows CLK at J2 of DDC232 board, purple shows 12V at J2 of DDC232 board.  || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run02.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run02.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3550.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3550.JPG]</div>
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|3 || 3, 2 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Boards initially facing downwards but rotated upwards to expose to room lighting. Sweep begins around 5s mark. Note that channels 1-16 show no output as they have been replaced with resistors; also, there is no mirroring. || <div class="image150px" style="text-align: center;">
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|3 || P || Yellow trace shows DVALID at FPGA, purple trace shows DOUT at J2 of DDC232 board. || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run03.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run03.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3551.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3551.JPG]</div> <div class="image150px" style="text-align: center;">
 +
[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3552.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3552.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3553.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3553.JPG]</div>
|-
|-
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|4 || 3, 1, 4 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Boards initially facing downwards but rotated upwards to expose to room lighting: boards rotated repeatedly to examine signal dropouts on board 4. Sweep begins around 47s mark. Note that the mirroring is the <b>lowest</b> of the photodiode pairs on boards 1 and 4. Note also that very noisy signals and signal dropouts are seen on board 4 (photodiodes 1-16) and that this is <b>not</b> replicated on board 1; so whatever is causing this noisy behaviour does not contribute to the mirroring. Compare this to run 2 above where these noisy signals and dropouts are <b>not</b> seen. || <div class="image150px" style="text-align: center;">
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|4 || P || Green trace shows CLK at J2 of DDC232 board, blue trace shows DCLK at J2 of DDC232 board. || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run04.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run04.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3554.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3554.JPG]</div>
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|5 || 3, 4, 1 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Reording of boards from run 4 above. Boards initially facing downwards but rotated upwards to expose to room lighting. Sweep begins around 25s mark. Note that the behaviour is similar to run 4 with board 4 still noisy and that this noise is not mirrored but that the low signals are mirrored between boards 1 and 4. || <div class="image150px" style="text-align: center;">
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|5 || P, P || Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows 12V of 1st board at J2. || <div class="image150px" style="text-align: center;">
-
[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run05.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run05.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3555.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3555.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3556.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3556.JPG]</div>
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|6 || 3, 4, 1 || Swept uncovering of each photodiode in turn. Sweep begins near the start of the video but it only seen in the signals once board 1 is fully uncovered and board 4 starts to be uncovered. Mirroring appears to be connected to <b>lowest</b> output, not largest, for mirrored pairs. || <div class="image150px" style="text-align: center;">
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|6 || P, P || Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. The last trace shows the end of a readout cycle. || <div class="image150px" style="text-align: center;">
-
[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run06.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run06.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3557.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3557.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3558.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3558.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3559.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3559.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3560.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3560.JPG]</div>
|-
|-
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|7 || 3, 4, 1 || Swept uncovering of each photodiode in turn - in opposite direction to run 6 - followed by board rotation and swept covering with finger. Note that board 4 shows zero output during uncovering due to signal dropouts associated with rotation. Low signals around 1m25s mark are a results of covering photodiodes partially with a finger. || <div class="image150px" style="text-align: center;">
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|7 || P, R || Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. The trace shows the transition from photodiode data bits to resistor data bits in the readout cycle. || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run07.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run07.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3561.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3561.JPG]</div>
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|8 || 4, 3, 1 || Swept uncovering of each photodiode in turn followed by board rotation and swept covering with finger. Repeat of run 7 above but with board reordering. Note that board 4 <b>no longer shows noise when rotated</b> now that its the last board in the chain. || <div class="image150px" style="text-align: center;">
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|8 || P, P, P || Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, purple shows 12V of 1st board at J2.|| <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run08.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run08.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3562.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3562.JPG]</div>
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|9 || 3, 4, 2 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Now includes board 2 with resistor-shorted photodiode connections. Note that neither boards 4 or 2 show any output, corroborating that low values are mirrored despite board 4 being exposed to light. || <div class="image150px" style="text-align: center;">
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|9 || P, P, P || Green trace shows CLK of 1st board at J2, blue shows DCLK of first board at J2. || <div class="image150px" style="text-align: center;">
-
[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run09.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run09.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3563.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3563.JPG]</div>
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|10 || 3, 2, || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Reording of boards from run 9 above: note that the behaviour is similar with no output from boards 2 and 4. || <div class="image150px" style="text-align: center;">
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|10 || P, P, P || Yellow trace shows DVALID at FPGA, green shows CLK of first board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. || <div class="image150px" style="text-align: center;">
-
[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run10.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run10.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3564.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3564.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3566.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3566.JPG]</div>
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|11 || 3, 1, 4, 2 || board rotation and sweep covering of photodiodes || <div class="image150px" style="text-align: center;">
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|11 || P, R, P || Blue trace shows DOUT of first board at J2, purple shows DOUT of second board at J3, green shows DOUT of third at J3 || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run11.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run11.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3567.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3567.JPG]</div> <div class="image150px" style="text-align: center;">
 +
[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3568.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3568.JPG]</div>
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|12 || 3, 4, 2, 1 || board rotation and sweep covering of photodiodes || <div class="image150px" style="text-align: center;">
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|12 || P, P, P, R || Yellow trace shows DVALID of first board at J2, blue shows DOUT of first board at J2, purple shows CLK of third board at J3, green shows CLK of fourth board at J3. || <div class="image150px" style="text-align: center;"> [http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3572.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3572.JPG]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run12.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run12.png]</div>
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|13 || 3, 2, 1, 4 || board rotation and sweep covering of photodiodes || <div class="image150px" style="text-align: center;">
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|13 || P, P, P, R || Blue trace shows DOUT of first board at J2, purple shows DOUT of third board at J3, green shows DOUT of fourth board at J3. || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run13.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run13.png]</div>
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3573.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3573.JPG]</div>
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|-
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|14 || P, P, P, R || Yellow trace shows DVALID of first board at J2, blue shows DCLK of first board at J2, purple shows DCLK of third board at J3, green shows DCLK of fourth board at J3. || <div class="image150px" style="text-align: center;">[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3574.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3574.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3575.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3575.JPG]</div>
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|-
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|15 || P, P, P, R || Yellow trace shows DVALID of first board at J2, blue shows 12V of first board at J2, purple shows DCLK of third board J3, green shows 12V of fourth board at J3. Second image has yellow and purple showing DCLK of different boards (unsure which ones). || <div class="image150px" style="text-align: center;"> [http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3576.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3576.JPG]</div> <div class="image150px" style="text-align: center;"> [http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3577.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3577.JPG]</div>
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|-
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|16 || N/A || Yellow shows CLK pin directly from FPGA without any board connected. || <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3578.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3578.JPG]</div> <div class="image150px" style="text-align: center;">
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[http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3579.JPG http://www.hep.ucl.ac.uk/pbt/wikiData/images/DDC232/20210401/IMG_3579.JPG]</div>
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Latest revision as of 12:28, 7 April 2021

Daisy chain tests of second DDC232 prototype in D109

Aim: Debug "mirroring" issues when daisy-chaining more than 2 DDC232s boards. Test signal quality across boards using 500MHz oscilloscope.

Notes

  • 3 DDC232 boards have S12915-16R photodiodes.
  • 1 DDC232 board has 1k ohm resistors.
  • In the runs below, boards are enumerated right to left, with the right-most board (1st board) connected to the FPGA.
  • In the configuration column, P = board with photodiodes and R = board with resistors. The first board listed in this column is connected to the FPGA.
  • In all runs, an integration time of 170us and full-scale range of 350pC is used.

Traces saved in /unix/www/html/pbt/wikiData/images/DDC232/20210401

Run Board Configuration Scope Trace Description Oscilloscope Trace
1 P Yellow trace shows DVALID at FPGA, blue shows DVALID at J2 of DDC232 board.
IMG_3548.JPG
IMG_3549.JPG
2 P Yellow trace shows DVALID at FPGA, green shows CLK at J2 of DDC232 board, purple shows 12V at J2 of DDC232 board.
IMG_3550.JPG
3 P Yellow trace shows DVALID at FPGA, purple trace shows DOUT at J2 of DDC232 board.
IMG_3551.JPG
IMG_3552.JPG
IMG_3553.JPG
4 P Green trace shows CLK at J2 of DDC232 board, blue trace shows DCLK at J2 of DDC232 board.
IMG_3554.JPG
5 P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows 12V of 1st board at J2.
IMG_3555.JPG
IMG_3556.JPG
6 P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. The last trace shows the end of a readout cycle.
IMG_3557.JPG
IMG_3558.JPG
IMG_3559.JPG
IMG_3560.JPG
7 P, R Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. The trace shows the transition from photodiode data bits to resistor data bits in the readout cycle.
IMG_3561.JPG
8 P, P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, purple shows 12V of 1st board at J2.
IMG_3562.JPG
9 P, P, P Green trace shows CLK of 1st board at J2, blue shows DCLK of first board at J2.
IMG_3563.JPG
10 P, P, P Yellow trace shows DVALID at FPGA, green shows CLK of first board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2.
IMG_3564.JPG
IMG_3566.JPG
11 P, R, P Blue trace shows DOUT of first board at J2, purple shows DOUT of second board at J3, green shows DOUT of third at J3
IMG_3567.JPG
IMG_3568.JPG
12 P, P, P, R Yellow trace shows DVALID of first board at J2, blue shows DOUT of first board at J2, purple shows CLK of third board at J3, green shows CLK of fourth board at J3.
IMG_3572.JPG
13 P, P, P, R Blue trace shows DOUT of first board at J2, purple shows DOUT of third board at J3, green shows DOUT of fourth board at J3.
IMG_3573.JPG
14 P, P, P, R Yellow trace shows DVALID of first board at J2, blue shows DCLK of first board at J2, purple shows DCLK of third board at J3, green shows DCLK of fourth board at J3.
IMG_3574.JPG
IMG_3575.JPG
15 P, P, P, R Yellow trace shows DVALID of first board at J2, blue shows 12V of first board at J2, purple shows DCLK of third board J3, green shows 12V of fourth board at J3. Second image has yellow and purple showing DCLK of different boards (unsure which ones).
IMG_3576.JPG
IMG_3577.JPG
16 N/A Yellow shows CLK pin directly from FPGA without any board connected.
IMG_3578.JPG
IMG_3579.JPG
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