Proton Calorimetry/Experimental Runs/2021/Apr1

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Daisy chain tests of second DDC232 prototype in D109

Aim: Debug "mirroring" issues when daisy-chaining more than 2 DDC232s boards. Test signal quality across boards using 500MHz oscilloscope.

Notes

  • 3 DDC232 boards have S12915-16R photodiodes.
  • 4th DDC232 board has 1k ohm resistors.
  • In the runs below, boards are enumerated right to left, with the right-most board (1st board) connected to the FPGA.
  • In the configuration column, P = board with photodiodes and R = board with resistors. The first board listed in this column is connected to the FPGA.
  • In all runs, an integration time of 170us and full-scale range of 350pC is used.

Traces saved in /unix/www/html/pbt/wikiData/images/DDC232/20210401

Run Board Configuration Scope Trace Description Oscilloscope Trace
1 P Yellow trace shows DVALID at FPGA, blue shows DVALID at J2 of DDC232 board.
IMG_3548.JPG
IMG_3549.JPG
2 P Yellow trace shows DVALID at FPGA, green shows CLK at J2 of DDC232 board, purple shows 12V at J2 of DDC232 board.
IMG_3550.JPG
3 P Yellow trace shows DVALID at FPGA, purple trace shows DOUT at J2 of DDC232 board.
IMG_3551.JPG
IMG_3552.JPG
IMG_3553.JPG
4 P Green trace shows CLK at J2 of DDC232 board, blue trace shows DCLK at J2 of DDC232 board.
IMG_3554.JPG
5 P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows 12V of 1st board at J2.
IMG_3555.JPG
IMG_3556.JPG
6 P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. The last trace shows the end of a readout cycle.
IMG_3557.JPG
IMG_3558.JPG
IMG_3559.JPG
IMG_3560.JPG
7 P, R Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. The trace shows the transition from photodiode data bits to resistor data bits in the readout cycle.
IMG_3561.JPG
IMG_3564.JPG
8 P, P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, purple shows 12V of 1st board at J2.
IMG_3562.JPG
9 P, P, P Green trace shows CLK of 1st board at J2, blue shows DCLK of first board at J2.
IMG_3563.JPG
10 3, 2, 4 Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Reording of boards from run 9 above: note that the behaviour is similar with no output from boards 2 and 4.
Run10.png
11 3, 1, 4, 2 board rotation and sweep covering of photodiodes
Run11.png
12 3, 4, 2, 1 board rotation and sweep covering of photodiodes
Run12.png
13 3, 2, 1, 4 board rotation and sweep covering of photodiodes
Run13.png
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