Minutes for UCL Proton Calorimetry Meetings, 24th June
Simon Jolly, Laurent Kelleter, Saad Shaikh, Raffaella Radogna
- Wrote a 2 pages draft of project proposal about the development and production of an integrated QA device for PBT.
- Now in touch with the UCL BEAMS research support team to discuss opportunities
- Booked a 1 to 1 appointment for Wed 1st July
- FPGA board dispatched on June 17th. Arrival at IT inward office of exchange on June 22nd.
- Successfully used Xilinx Clocking Wizard to customise FPGA system clock.
- 120 MHz looks like a good frequency to generate signals needed for DDC232.
- ALMOST got serial terminal interface between PC and FPGA working.
- Following example project designed to echo serial input in Tera Term.
- Need to sit with Matt to debug project.
- Unsure how useful TI example FPGA code will be - quite difficult to understand at this point.
- Simon will clarify with Ruben how much time Matt can spend on PBT.
- Probably best to purchase new laptop after next revision of Intel-based MacBook Pros - likely to happen end of 2020.
- Still waiting on Ruben to respond.
- Old MacBook Pro to be sent to MR Systems for repair. Will get Simon in touch with MR.