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TimModule.cxx

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//File: TimModule.cxx

#include <iostream>  // for debug only

using namespace std;

#include "TimModule.h"

// Namespace for the common routines for SCT and PIXEL ROD software.

namespace SctPixelRod {

// ************************* Class TimException ******************************


TimException::TimException( std::string descriptor, int data1, int data2 ) :
             BaseException( descriptor ) {

  m_data1 = data1;
  m_data2 = data2;
  setType( TIM );
}

void TimException::what( std::ostream& os ) {

  os << "TimException: " << getDescriptor() << endl;
  os << "Data1: " << getData1() << endl;
  os << "Data2: " << getData2() << endl;
}

// ************************* Class TimModule *********************************

// Constructors, destructor, and assignment

// ------------------------- Constructor -------------------------------------


TimModule::TimModule( UINT32 baseAddr, UINT32 mapSize, VmeInterface & vme ) :
           VmeModule( baseAddr, mapSize, vme ) {

  m_serialNumber = 0xFFFFFFFF;  // Set in initialize

  if (&vme == 0) throw TimException( "TimModule has no VmeInterface", 0, 0 );

  try {
    m_vmePort = new VmePort( baseAddr, mapSize, VmeInterface::A32, vme );

    m_vmePort->setExceptionTrapping( true );
  }
  catch (bad_alloc) {
    throw TimException( "TimModule caught bad_alloc", 0, 0 );
  }
  catch (VmeException x) {
    throw TimException( "TimModule caught VmeException",
                        x.getErrorClass(), x.getErrorCode() );
  }
}

// ------------------------- Destructor --------------------------------------

TimModule::~TimModule() {

  delete m_vmePort;
  m_vmePort = 0;
}

// ---------------------------------------------------------------------------

// Member methods

// ------------------------- initialize --------------------------------------

void TimModule::initialize() {

  // enable serial output streams
  regLoad( TIM_REG_RUN_ENABLES, TIM_BIT_EN_ID | TIM_BIT_EN_TYPE );
  regLoad( TIM_REG_COMMAND, 0 );                    // ensure stand-alone mode
  regLoad( TIM_REG_TRIGGER_BCID, TIM_BCID_OFFSET << 12 );  // set BCID offset
  fetchTimID();                                          // read serial number
}

// ------------------------- reset -------------------------------------------

void TimModule::reset() {

  regLoad( TIM_REG_COMMAND, TIM_BIT_VRESET );
}

// ------------------------- status ------------------------------------------

void TimModule::status() {

  cout << "status" << endl;

  cout << " Serial Number: " << m_serialNumber;
  cout << " Version: "       << m_firmware;
  cout << endl;
  hex(cout);
  cout << " L1ID: "   << fetchL1ID();
  cout << " BCID: "   << regFetch( TIM_REG_TRIGGER_BCID );
  cout << " status: " << regFetch( TIM_REG_STATUS );
  cout << endl;
  dec(cout);
}

// ------------------------- fetchL1ID ---------------------------------------
UINT32 TimModule::fetchL1ID() {

  const UINT32 lo = regFetch( TIM_REG_TRIGGER_IDLO );
  const UINT32 hi = regFetch( TIM_REG_TRIGGER_IDHI );
  UINT32 l1id;

  if (m_firmware < 9) l1id = (lo & 0x0FFF) + ((hi & 0x0FFF) << 12);
  else                l1id = (lo & 0xFFFF) + ((hi & 0x00FF) << 16);
  return l1id;
}

// ------------------------- fetchTimID --------------------------------------

UINT16 TimModule::fetchTimID() {

  const UINT16 timID = regFetch( TIM_REG_TIM_ID );

  m_serialNumber = timID & 0xFF;
  m_firmware     = timID >> 8;
  return timID;
}

// ------------------------- intTrigStart ------------------------------------

void TimModule::intTrigStart( const TimMaskFrequency frequency ) {

  loadByteLo( TIM_REG_FREQUENCY, frequency );
  loadBitSet( TIM_REG_ENABLES, TIM_BIT_EN_INT_TRIG );
}

// ------------------------- intTrigStop -------------------------------------

void TimModule::intTrigStop(void) { //*** void

  loadBitClear( TIM_REG_ENABLES, TIM_BIT_EN_INT_TRIG );
}

// ------------------------- issueCommand ------------------------------------

void TimModule::issueCommand( const TimBitCommand mask ) {

  if (mask >  TIM_VSPA) loadBitClear( TIM_REG_COMMAND, mask );
  loadBitSet( TIM_REG_COMMAND, mask );
  if (mask >  TIM_VSPA) loadBitClear( TIM_REG_COMMAND, mask );
}

// ------------------------- issueVCAL ---------------------------------------

void TimModule::issueVCAL( const UINT8 pipelineDelay ) {

  loadByteLo(   TIM_REG_DELAY, pipelineDelay );
  issueCommand( TIM_VCAL );
}

// ------------------------- loadBitSet --------------------------------------

void TimModule::loadBitSet( const TimRegister addr, const UINT16 mask ) {

  UINT16 value = vmeFetch( addr );
  vmeLoad( addr, value | mask );
}

// ------------------------- loadBitClear ------------------------------------

void TimModule::loadBitClear( const TimRegister addr, const UINT16 mask ) {

  UINT16 value = vmeFetch( addr );
  vmeLoad( addr, value & ~mask );
}

// ------------------------- loadByteHi --------------------------------------

void TimModule::loadByteHi( const TimRegister addr, const UINT8 byte ) {

  UINT16 value = vmeFetch( addr );
  vmeLoad( addr, (value & 0x00FF) | (byte << 8) );
}

// ------------------------- loadByteLo --------------------------------------

void TimModule::loadByteLo( const TimRegister addr, const UINT8 byte ) {

  UINT16 value = vmeFetch( addr );
  vmeLoad( addr, (value & 0xFF00) | byte );
}

// ------------------------- regFetch ----------------------------------------

UINT16 TimModule::regFetch( const TimRegister addr ) {

  UINT16 data = vmeFetch( addr );
  return data;
}

// ------------------------- regLoad -----------------------------------------

void TimModule::regLoad( const TimRegister addr, const UINT16 data ) {

  vmeLoad( addr, data );
}

// ------------------------- seqRun ------------------------------------------

void TimModule::seqRun( const UINT16 size ) {

  regLoad( TIM_REG_SEQ_END,     size - 1 );
  regLoad( TIM_REG_SEQ_CONTROL, TIM_BIT_SEQ_RESET );
  regLoad( TIM_REG_SEQ_CONTROL, 0 );
  regLoad( TIM_REG_SEQ_CONTROL, TIM_BIT_SEQ_GO | TIM_BIT_SEQ_EN_ALL );
  // all outputs enabled
}

// ------------------------- seqFetch ----------------------------------------

void TimModule::seqFetch( const UINT16 size, UINT16 buffer[] ) {

  for (int i = 0; i < size; i++) {
    buffer[i] = vmeFetch( TIM_SEQ_ADDR + i*2 );
  }
}

// ------------------------- seqLoad -----------------------------------------

void TimModule::seqLoad( const UINT16 size, const UINT16 buffer[] ) {

  UINT16 data;
  for (int i = 0; i < size; i++) {
    data = buffer[i];
    vmeLoad( TIM_SEQ_ADDR + i*2, data );
  }
}

// ------------------------- vmeFetch ----------------------------------------

UINT16 TimModule::vmeFetch( const UINT32 addr )
                  throw (VmeException &) {

  UINT16 data = 0;
  try {
    data = m_vmePort->read16( addr );
  }
  catch (VmeException & vmeFailed) {
    // Leave critical section before re-throwing the error
    throw vmeFailed;
  }
  return data;
}

// ------------------------- vmeLoad -----------------------------------------

void TimModule::vmeLoad( const UINT32 addr, const UINT16 data )
                throw (VmeException & ) {

  try {
    m_vmePort->write16( addr, data );
//debug  throw VmeException(VmeException::BUS_ERROR, 1, m_vmePort);
  }
  catch (VmeException & vmeFailed) {
    // Leave critical section before re-throwing the error
    throw vmeFailed;
  }
}

} // End namespace SctPixelRod

// ------------------------- Overload operator<< -----------------------------

using namespace SctPixelRod;

namespace std {

ostream& operator<<( ostream& os, TimModule& tim ) {

  os << "TIM status" << endl;

  os << " Serial Number: " << tim.getSerialNumber();
  os << " Version: "       << tim.getFirmware() << endl;
  hex(cout);
  os << " L1ID: "   << tim.fetchL1ID();
  os << " BCID: "   << tim.regFetch( TIM_REG_TRIGGER_BCID );
  os << " status: " << tim.regFetch( TIM_REG_STATUS );
  os << endl;

  return os;
}

} // End namespace std

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