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SctPixelRod Namespace Reference


Compounds

class  SctPixelRod::TimException
 TimException: a general exception class for TIM errors. More...

class  SctPixelRod::TimModule
 TimModule: A derived class for VME TIM modules. More...

struct  SctPixelRod::TimScanControl
 Structure definition for control of scanning Sequencer buffer. More...

struct  SctPixelRod::TimScanResults
 Structure definition for results of scanning Sequencer buffer. More...

class  SctPixelRod::TimSequin
 TimSequin: A class for TIM Sequencer information. More...


Enumerations

enum  TimTimingSCT {
  TIM_L1A_DEADTIME = 3,
  TIM_ECR_DEADTIME = 7,
  TIM_BCR_DEADTIME = 7,
  TIM_CAL_DEADTIME = 27,
  TIM_BCID_OFFSET = 6
}
 Define timing in clock cycles for SCT, Pixel is different. More...

enum  TimRegister {
  TIM_REG_ENABLES = 0x00,
  TIM_REG_COMMAND = 0x02,
  TIM_REG_BURST_COUNT = 0x04,
  TIM_REG_FREQUENCY = 0x06,
  TIM_REG_WINDOW = 0x08,
  TIM_REG_DELAY = 0x0A,
  TIM_REG_STATUS = 0x0C,
  TIM_REG_FIFO_STATUS = 0x0E,
  TIM_REG_TRIGGER_IDLO = 0x10,
  TIM_REG_TRIGGER_IDHI = 0x12,
  TIM_REG_TRIGGER_BCID = 0x14,
  TIM_REG_TRIGGER_TYPE = 0x16,
  TIM_REG_RUN_ENABLES = 0x18,
  TIM_REG_SEQ_CONTROL = 0x1A,
  TIM_REG_SEQ_END = 0x1C,
  TIM_REG_ROD_MASK = 0x1E,
  TIM_REG_ROD_BUSY = 0x20,
  TIM_REG_ROD_LATCH = 0x22,
  TIM_REG_ROD_MONITOR = 0x24,
  TIM_REG_TTC_DATA = 0x26,
  TIM_REG_TTC_SELECT = 0x28,
  TIM_REG_TTC_BCID = 0x2A,
  TIM_REG_TTC_RX = 0x2C,
  TIM_REG_TTC_STATUS = 0x2E,
  TIM_REG_OUTPUT = 0x30,
  TIM_REG_TIM_ID = 0x32
}
 Define register offsets in bytes. More...

enum  TimBitEnables {
  TIM_BIT_EN_INT_TRIG = 0x0002,
  TIM_BIT_EN_INT_ECR = 0x0004,
  TIM_BIT_EN_INT_BCR = 0x0008,
  TIM_BIT_EN_RANDOM = 0x0010,
  TIM_BIT_EN_INT_FER = 0x0020,
  TIM_BIT_EN_WINDOW = 0x0040,
  TIM_BIT_EN_INT_BUSY = 0x0080,
  TIM_BIT_EN_EXT_CLK = 0x0100,
  TIM_BIT_EN_EXT_TRIG = 0x0200,
  TIM_BIT_EN_EXT_ECR = 0x0400,
  TIM_BIT_EN_EXT_BCR = 0x0800,
  TIM_BIT_EN_EXT_CAL = 0x1000,
  TIM_BIT_EN_EXT_FER = 0x2000,
  TIM_BIT_EN_EXT_SEQ = 0x4000,
  TIM_BIT_EN_EXT_BUSY = 0x8000
}
 Define register bits as masks. More...

enum  TimMaskFrequency {
  TIM_MASK_TRIG_100_KHZ = 0x0006,
  TIM_MASK_TRIG_10_0KHZ = 0x000E,
  TIM_MASK_TRIG_1_00KHZ = 0x0016,
  TIM_MASK_TRIG_0_10KHZ = 0x001E,
  TIM_MASK_FER_10_00HZ = 0x0600,
  TIM_MASK_FER_1_000HZ = 0x0E00,
  TIM_MASK_FER_0_100HZ = 0x1600,
  TIM_MASK_FER_0_010HZ = 0x1E00
}
enum  TimBitBackplane {
  TIM_L1A = 0x01,
  TIM_ECR = 0x02,
  TIM_BCR = 0x04,
  TIM_CAL = 0x08,
  TIM_SID = 0x10,
  TIM_STT = 0x20,
  TIM_CMD = 0xCF,
  TIM_RES = 0xC0,
  TIM_FER = 0x40,
  TIM_SPA = 0x80,
  TIM_TRG = 0x31
}
 Applies to Sequencer and Output. More...

enum  TimBitCommand {
  TIM_VTRG = 0x02,
  TIM_VECR = 0x04,
  TIM_VBCR = 0x08,
  TIM_VCAL = 0x10,
  TIM_VFER = 0x20,
  TIM_VSPA = 0x40,
  TIM_BIT_VRESET = 0x8000
}
 Applies to Command register. More...

enum  TimBitRunEnables {
  TIM_BIT_EN_ID = 0x0200,
  TIM_BIT_EN_TYPE = 0x0400
}
enum  TimBitSeqControl {
  TIM_BIT_SEQ_EN_ALL = 0x00FF,
  TIM_BIT_SEQ_RESET = 0x0200,
  TIM_BIT_SEQ_GO = 0x0400,
  TIM_BIT_EN_CYCLIC = 0x0800
}
enum  Name { NONE = -999 }

Variables

const INT32 TIM_L1ID_FIRST = 0
 triggers. More...

const INT32 TIM_SEQ_SIZE = 0x4000
 bytes. More...

const INT32 TIM_SEQ_ADDR = 0x8000
 bytes. More...

const int s_masks [2] = { TIM_SID, TIM_STT }
const int s_words [2] = { 2, 1 }
const int s_bits [2][2] = {{ 24, 12 },{ 10, 0 }}

Enumeration Type Documentation

enum SctPixelRod::Name
 

Enumeration values:
NONE 

Definition at line 27 of file TimSequin.cxx.

Referenced by timKeyword.

enum SctPixelRod::TimBitBackplane
 

Applies to Sequencer and Output.

Enumeration values:
TIM_L1A  Level-1 Accept trigger.
TIM_ECR  Event Counter Reset.
TIM_BCR  Bunch Counter Reset.
TIM_CAL  Calibrate strobe.
TIM_SID  Serial event ID.
TIM_STT  Serial Trigger Type.
TIM_CMD  Commands available.
TIM_RES  Commands reserved.
TIM_FER  Front-End Reset - reserved.
TIM_SPA  Spare command - reserved.
TIM_TRG  Trigger and serial streams.

Definition at line 113 of file TimDefine.h.

Referenced by SctPixelRod::TimSequin::addByBunch, and SctPixelRod::TimSequin::addByIndex.

enum SctPixelRod::TimBitCommand
 

Applies to Command register.

Enumeration values:
TIM_VTRG  Single VME Trigger.
TIM_VECR  Single VME ECR.
TIM_VBCR  Single VME BCR.
TIM_VCAL  Single VME CAL.
TIM_VFER  Single VME FER.
TIM_VSPA  Single VME SPA.
TIM_BIT_VRESET 

Definition at line 127 of file TimDefine.h.

Referenced by SctPixelRod::TimModule::issueCommand.

enum SctPixelRod::TimBitEnables
 

Define register bits as masks.

Enumeration values:
TIM_BIT_EN_INT_TRIG  Enable internal repetitive Trigger.
TIM_BIT_EN_INT_ECR  Enable internal repetitive ECReset.
TIM_BIT_EN_INT_BCR  Enable internal repetitive BCReset.
TIM_BIT_EN_RANDOM  Enable internal trigger randomizer.
TIM_BIT_EN_INT_FER  Enable internal repetitive FEReset.
TIM_BIT_EN_WINDOW  Enable trigger window.
TIM_BIT_EN_INT_BUSY  Enable internal Busy.
TIM_BIT_EN_EXT_CLK  Enable external inputs: clock.
TIM_BIT_EN_EXT_TRIG  Enable external inputs: trigger.
TIM_BIT_EN_EXT_ECR  Enable external inputs: ECReset.
TIM_BIT_EN_EXT_BCR  Enable external inputs: BCReset.
TIM_BIT_EN_EXT_CAL  Enable external inputs: Calibrate.
TIM_BIT_EN_EXT_FER  Enable external inputs: FEReset.
TIM_BIT_EN_EXT_SEQ  Enable external inputs: Sequencer Go.
TIM_BIT_EN_EXT_BUSY  Enable external inputs: Busy.

Definition at line 82 of file TimDefine.h.

enum SctPixelRod::TimBitRunEnables
 

Enumeration values:
TIM_BIT_EN_ID 
TIM_BIT_EN_TYPE 

Definition at line 138 of file TimDefine.h.

enum SctPixelRod::TimBitSeqControl
 

Enumeration values:
TIM_BIT_SEQ_EN_ALL 
TIM_BIT_SEQ_RESET 
TIM_BIT_SEQ_GO 
TIM_BIT_EN_CYCLIC 

Definition at line 143 of file TimDefine.h.

enum SctPixelRod::TimMaskFrequency
 

Enumeration values:
TIM_MASK_TRIG_100_KHZ 
TIM_MASK_TRIG_10_0KHZ 
TIM_MASK_TRIG_1_00KHZ 
TIM_MASK_TRIG_0_10KHZ 
TIM_MASK_FER_10_00HZ 
TIM_MASK_FER_1_000HZ 
TIM_MASK_FER_0_100HZ 
TIM_MASK_FER_0_010HZ 

Definition at line 101 of file TimDefine.h.

Referenced by SctPixelRod::TimModule::intTrigStart.

enum SctPixelRod::TimRegister
 

Define register offsets in bytes.

Enumeration values:
TIM_REG_ENABLES 
TIM_REG_COMMAND 
TIM_REG_BURST_COUNT 
TIM_REG_FREQUENCY 
TIM_REG_WINDOW 
TIM_REG_DELAY 
TIM_REG_STATUS 
TIM_REG_FIFO_STATUS 
TIM_REG_TRIGGER_IDLO 
TIM_REG_TRIGGER_IDHI 
TIM_REG_TRIGGER_BCID 
TIM_REG_TRIGGER_TYPE 
TIM_REG_RUN_ENABLES 
TIM_REG_SEQ_CONTROL 
TIM_REG_SEQ_END 
TIM_REG_ROD_MASK 
TIM_REG_ROD_BUSY 
TIM_REG_ROD_LATCH 
TIM_REG_ROD_MONITOR 
TIM_REG_TTC_DATA 
TIM_REG_TTC_SELECT 
TIM_REG_TTC_BCID 
TIM_REG_TTC_RX 
TIM_REG_TTC_STATUS 
TIM_REG_OUTPUT 
TIM_REG_TIM_ID 

Definition at line 51 of file TimDefine.h.

Referenced by SctPixelRod::TimModule::loadBitClear, SctPixelRod::TimModule::loadBitSet, SctPixelRod::TimModule::loadByteHi, SctPixelRod::TimModule::loadByteLo, SctPixelRod::TimModule::regFetch, and SctPixelRod::TimModule::regLoad.

enum SctPixelRod::TimTimingSCT
 

Define timing in clock cycles for SCT, Pixel is different.

Enumeration values:
TIM_L1A_DEADTIME 
TIM_ECR_DEADTIME 
TIM_BCR_DEADTIME 
TIM_CAL_DEADTIME 
TIM_BCID_OFFSET 

Definition at line 33 of file TimDefine.h.

Variable Documentation

const int SctPixelRod::s_bits[2][2] = {{ 24, 12 },{ 10, 0 }} [static]
 

Definition at line 31 of file TimSequin.cxx.

Referenced by SctPixelRod::TimSequin::addTrigger, and SctPixelRod::TimSequin::scan.

const int SctPixelRod::s_masks[2] = { TIM_SID, TIM_STT } [static]
 

Definition at line 29 of file TimSequin.cxx.

Referenced by SctPixelRod::TimSequin::addTrigger, and SctPixelRod::TimSequin::scan.

const int SctPixelRod::s_words[2] = { 2, 1 } [static]
 

Definition at line 30 of file TimSequin.cxx.

Referenced by SctPixelRod::TimSequin::addTrigger, and SctPixelRod::TimSequin::scan.

const INT32 SctPixelRod::TIM_L1ID_FIRST = 0
 

triggers.

Definition at line 41 of file TimDefine.h.

Referenced by SctPixelRod::TimSequin::addByIndex, SctPixelRod::TimSequin::reset, and SctPixelRod::TimSequin::scan.

const INT32 SctPixelRod::TIM_SEQ_ADDR = 0x8000
 

bytes.

Definition at line 47 of file TimDefine.h.

Referenced by SctPixelRod::TimModule::seqFetch, and SctPixelRod::TimModule::seqLoad.

const INT32 SctPixelRod::TIM_SEQ_SIZE = 0x4000
 

bytes.

Sequencer RAM is 16K bytes for both source and sink memory. They are accessed together as 16K 16-bit words.

Definition at line 46 of file TimDefine.h.

Referenced by SctPixelRod::TimSequin::addTrigger, damon, SctPixelRod::TimSequin::fill, SctPixelRod::TimSequin::reset, SctPixelRod::TimSequin::scanDefaults, SctPixelRod::TimSequin::setBuffer, test, and timKeyword.

Generated on Sun Jun 27 19:57:36 2004 for TimModule by doxygen1.2.14 written by Dimitri van Heesch, © 1997-2002